With Multiple Gate Structure (epo) Patents (Class 257/E29.264)
E Subclasses
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Publication number: 20120168878Abstract: Disclosed is a field effect transistor (FET), in which ohmic body contact(s) are placed relatively close to the active region. The FET includes a semiconductor layer, where the active region and body contact region(s) are defined by a trench isolation structure and where a body region is below and abuts the active region, the trench isolation structure and the body contact region(s). A gate traverses the active region. Dummy gate(s) are on the body contact region(s). A contact extends through each dummy gate to the body contact region below. Dielectric material isolates the contact(s) from the dummy gate(s). During processing, the dummy gate(s) act as blocks to ensure that the body contact regions are not implanted with source/drain dopants or source/drain extension dopants and, thereby to ensure that the body contacts, as formed, are ohmic. Also disclosed are an integrated circuit structure with stacked FETs, having such ohmic body contacts, and associated methods.Type: ApplicationFiled: January 4, 2011Publication date: July 5, 2012Applicant: International Business Machines CorporationInventors: Michel J. Abou-Khalil, William F. Clark, JR., Yun Shi
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Publication number: 20120168877Abstract: A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Inventors: Niloy Mukherjee, Gilbert Dewey, Marko Radosavljevic, Robert S. Chau, Matthew V. Metz
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Patent number: 8211771Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.Type: GrantFiled: August 24, 2011Date of Patent: July 3, 2012Assignee: Intel CorporationInventors: Ravi Pillarisetty, Jack Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung
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Publication number: 20120161230Abstract: A disclosed MOS transistor has a drain region offset from a gate electrode structure, wherein the gate electrode structure includes at least a first gate electrode and a second gate electrode such that the second gate electrode is located at the drain side of the first gate electrode and the second gate electrode is isolated from the first gate electrode by an insulation film, and wherein the first and second gate electrodes are formed respectively on a first gate insulation film and a second gate insulation film having an increased thickness as compared with the first gate insulation film.Type: ApplicationFiled: October 11, 2011Publication date: June 28, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shigeo Satoh, Takae Sukegawa
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Patent number: 8207582Abstract: Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.Type: GrantFiled: January 5, 2009Date of Patent: June 26, 2012Assignee: Micron Technology, Inc.Inventor: Jaydeb Goswami
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Patent number: 8203182Abstract: A FinFET (100) comprises a fin-shaped layer-section (116) of a single-crystalline active semiconductor layer (104) extending on an insulating substrate layer (106) along a longitudinal fin direction between, a source layer-section (122), and a drain layer-section (124) of the single-crystalline active semiconductor layer (104). Furthermore, two separate gate-electrode layers (138.1, 138.2) are provided, which do not form sections of the single-crystalline active semiconductor layer, each of the gate-electrode layers facing one of the opposite side faces of the fin-shaped layer-section (116). Each gate-electrode layer is connected with a respective separate gate contact (154, 156).Type: GrantFiled: March 6, 2008Date of Patent: June 19, 2012Assignees: NXP B.V., ST Microelectronics (Crolles 2) SASInventors: Markus Gerhard Andreas Muller, Philippe Coronel
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Patent number: 8198677Abstract: MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias.Type: GrantFiled: July 8, 2009Date of Patent: June 12, 2012Assignee: Fairchild Semiconductor CorporationInventors: Peter H. Wilson, Steven Sapp
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Patent number: 8193572Abstract: An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.Type: GrantFiled: December 24, 2009Date of Patent: June 5, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Chi-Nan Li, Cheong Min Hong
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Patent number: 8193567Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.Type: GrantFiled: December 11, 2008Date of Patent: June 5, 2012Assignee: Intel CorporationInventors: Jack T. Kavalieros, Justin K. Brask, Brian S. Doyle, Uday Shah, Suman Datta, Mark L. Doczy, Matthew V. Metz, Robert S. Chau
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Patent number: 8188546Abstract: Disclosed are embodiments of a semiconductor structure that includes one or more multi-gate field effect transistors (MUGFETs), each MUGFET having one or more semiconductor fins. In the embodiments, a dopant implant region is incorporated into the upper portion of the channel region of a semiconductor fin in order to selectively modify (i.e., decrease or increase) the threshold voltage within that upper portion relative to the threshold voltage in the lower portion and, thereby to selectively modify (i.e., decrease or increase) device drive current. In the case of a multiple semiconductor fins, the use of implant regions, the dopant conductivity type in the implant regions and/or the sizes of the implant regions can be varied from fin to fin within a multi-fin MUGFET or between different single and/or multi-fin MUGFETs so that individual device drive current can be optimized. Also disclosed herein are embodiments of a method of forming the semiconductor structure.Type: GrantFiled: August 18, 2009Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Publication number: 20120126325Abstract: A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin
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Publication number: 20120126327Abstract: A resonator and a method for manufacturing a resonator are provided. The method may include doping a wafer, and forming on the wafer a substrate, a drain electrode, a source electrode, a gate electrode, and at least one nanowire.Type: ApplicationFiled: November 22, 2011Publication date: May 24, 2012Applicants: KOREA UNIVERSITY INDUSTRIAL & ACADEMIC COLLABORATION FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: In Sang SONG, Sung Woo HWANG, Yun Kwon PARK, Byeong Kwon JU, Jae Sung RIEH, Jea Shik SHIN, Hee Tae KIM
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Patent number: 8183101Abstract: The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.Type: GrantFiled: November 17, 2009Date of Patent: May 22, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Robert Mulfinger, Andy Wei, Jan Hoentschel, Andrew Waite
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Publication number: 20120119297Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin.Type: ApplicationFiled: January 23, 2012Publication date: May 17, 2012Applicant: INFINEON TECHNOLOGIES AGInventor: Thomas Schulz
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Publication number: 20120119278Abstract: A semiconductor device includes a semiconductor substrate and a first gate structure. The semiconductor substrate has a first groove and a first pillar defined by the first groove. The first groove and the first pillar are adjacent to each other. The first gate structure is disposed in the first groove. The first gate structure includes a first gate insulating film and a first gate electrode. The first gate structure is separated by a first gap from the first pillar.Type: ApplicationFiled: November 15, 2011Publication date: May 17, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Noriaki MIKASA
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Patent number: 8174055Abstract: Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and having a top surface and side surfaces, forming a gate substantially perpendicular to the fin structure over a portion of the top and side surfaces, for example over a center portion, forming a planarizing layer over the gate, the fin structure, and the substrate, removing the planarizing layer from the substrate, gate, and fin structure down to the height of the fin structure, and forming spacers on the fin structure and on the planarizing layer, adjacent the gate.Type: GrantFiled: February 17, 2010Date of Patent: May 8, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Douglas Bonser, Catherine B. Labelle
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Patent number: 8169033Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.Type: GrantFiled: June 17, 2011Date of Patent: May 1, 2012Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Patent number: 8164137Abstract: Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (?) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.Type: GrantFiled: September 10, 2009Date of Patent: April 24, 2012Assignee: Electronics and Telecommunication Research InstituteInventors: Young Kyun Cho, Tae Moon Roh, Jong Dae Kim
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Patent number: 8164145Abstract: A three-dimensional double channel transistor configuration is provided in which a second channel region may be embedded into the body region of the transistor, thereby providing a three-state behavior, which may therefore increase functionality of conventional three-dimensional transistor architectures. The double channel three-dimensional transistors may be used for forming a static RAM cell with a reduced number of transistors, while also providing scalability by taking advantage of the enhanced controllability of FinFETS and nano pipe transistor architectures.Type: GrantFiled: April 17, 2009Date of Patent: April 24, 2012Assignee: GlobalFoundries, Inc.Inventor: Frank Wirbeleit
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Patent number: 8154081Abstract: A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree in the lateral direction than the vertical direction. The process may include second etching the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded hard mask. The thinned semiconductor fin may have a characteristic dimension that can exceed photolithography limits. Electronic devices may include the thinned semiconductor fin as part of a field effect transistor.Type: GrantFiled: January 31, 2011Date of Patent: April 10, 2012Assignee: Micron Technology, Inc.Inventors: Mark Fischer, T. Earl Allen, H. Montgomery Manning
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Publication number: 20120068183Abstract: To provide a power MISFET using oxide semiconductor. A gate electrode, a source electrode, and a drain electrode are formed so as to interpose a semiconductor layer therebetween, and a region of the semiconductor layer where the gate electrode and the drain electrode do not overlap with each other is provided between the gate electrode and the drain electrode. The length of the region is from 0.5 ?m to 5 ?m. In such a power MISFET, a power source of 100 V or higher and a load are connected in series between the drain electrode and the source electrode, and a control signal is input to the gate electrode.Type: ApplicationFiled: September 19, 2011Publication date: March 22, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Yasuhiko Takemura
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Publication number: 20120061753Abstract: A semiconductor device includes: a drain layer; a drift layer provided on the drain layer; a base region provided on the drift layer; a source region selectively provided on a surface of the base region; a first gate; a field-plate; a second gate; a drain electrode; and a source electrode. The first gate electrode is provided in each of a plurality of first trenches via a first insulating film. The first trenches penetrate from a surface of the source region through the base region and contact the drift layer. The field-plate electrode is provided in the first trench under the first gate electrode via a second insulating film. The second gate electrode is provided in a second trench via a third insulating film. The second trench penetrates from the surface of the source region through the base region and contacts the drift layer between the first trenches.Type: ApplicationFiled: March 21, 2011Publication date: March 15, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Tatsuya NISHIWAKI
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Publication number: 20120061662Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.Type: ApplicationFiled: August 30, 2011Publication date: March 15, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Hiromichi GODO, Satoshi KOBAYASHI
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Publication number: 20120061763Abstract: A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.Type: ApplicationFiled: September 2, 2011Publication date: March 15, 2012Inventors: Bo-young LEE, Jong-wan Choi, Jin-gi Hong, Myoung-bum Lee
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Patent number: 8120115Abstract: A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced).Type: GrantFiled: March 7, 2008Date of Patent: February 21, 2012Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: William G. Vandenberghe, Anne S. Verhulst
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Publication number: 20120032732Abstract: A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator (SOI) substrate. The method also includes implanting impurities into the substrate for adjusting a threshold voltage. The method provides a nitride film overlying a surface region of the substrate and selectively etches the silicon nitride film to form a nitride cap region. The method etches the silicon layer to form a first and a second silicon fin regions. The nitride cap region is maintained on a portion of a surface region of the first silicon fin region. The method includes forming a gate dielectric, depositing a polysilicon film, and planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop. The method etches the polysilicon film to form gate electrodes. The method forms elevated source and drain regions.Type: ApplicationFiled: January 6, 2011Publication date: February 9, 2012Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: DeYuan Xiao, Guo Qing Chen, Roger Lee
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Patent number: 8110877Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.Type: GrantFiled: December 19, 2008Date of Patent: February 7, 2012Assignee: Intel CorporationInventors: Niloy Mukherjee, Gilbert Dewey, Matthew V. Metz, Jack Kavalieros, Robert S. Chau
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Patent number: 8110458Abstract: In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.Type: GrantFiled: April 19, 2010Date of Patent: February 7, 2012Assignee: Intel CorporationInventors: Been-Yih Jin, Jack T. Kavalieros, Matthew V. Metz, Marko Radosavlievic, Robert S. Chau
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Publication number: 20120025315Abstract: The uniformity of transistor characteristics may be enhanced for transistors having incorporated therein a strain-inducing semiconductor material by using appropriately positioned dummy gate electrode structures. To this end, the dummy gate electrode structures may be positioned such that these structures may connect to or may overlap with the edge of the active region, thereby preserving a portion of the initial semiconductor material of the active region at the edge thereof upon forming the corresponding cavities.Type: ApplicationFiled: June 7, 2011Publication date: February 2, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Stephan Kronholz, Gunda Beernink, Maciej Wiatr
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Publication number: 20120025314Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method for forming the semiconductor device includes forming one or more buried gates in a semiconductor substrate, forming a landing plug between the buried gates, forming a bit line region exposing the landing plug over the semiconductor substrate, forming a glue layer in the bit line region, forming a bit line material in the bit line region, and removing the glue layer formed at inner sidewalls of the bit line region, and burying an insulation material in a part where the glue layer is removed. A titanium nitride (TiN) film formed at sidewalls of the damascene bit line is removed, so that resistance of the bit line is maintained and parasitic capacitance of the bit line is reduced, resulting in the improvement of device characteristics.Type: ApplicationFiled: December 27, 2010Publication date: February 2, 2012Applicant: Hynix Semiconductor Inc.Inventor: Chan Woo KIM
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Publication number: 20120018781Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.Type: ApplicationFiled: September 29, 2011Publication date: January 26, 2012Inventors: Mantu K. Hudait, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Jack T. Kavalieros
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Patent number: 8101509Abstract: A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.Type: GrantFiled: February 10, 2011Date of Patent: January 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-hoon Son, Si-young Choi, Jong-wook Lee
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Publication number: 20120007183Abstract: A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.Type: ApplicationFiled: July 8, 2010Publication date: January 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Josephine B. Chang, Dechao Guo, Shu-Jen Han, Chung-Hsun Lin
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Publication number: 20120007184Abstract: A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased.Type: ApplicationFiled: September 20, 2011Publication date: January 12, 2012Applicant: Hynix Semiconductor Inc.Inventor: Byung-Duk LEE
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Patent number: 8093659Abstract: The invention provides a three-dimensional stacked fin metal oxide semiconductor (SF-MOS) device (10,30) comprising a protrusion or fin structure with a plurality of stacked semiconductor regions (3,5,12), in which a second semiconductor region (5,12) is separated from a first semiconductor region (3,5) by an isolation region (4,11). A gate isolation layer (8) extends at least over the sidewalls of the protrusion (7) and a gate electrode extends over the gate isolation layer (8). The gate electrode comprises a plurality of gate regions (13,14,15) wherein each gate region (13,14,15) extends over another semiconductor region (3,5,12). In this way each gate region (13,14,15) influences the conduction channel of another semiconductor region (3,5,12) and hence adds another degree of freedom with which the performance of the SF-MOS device (10,30) can be optimized. The invention further provides a method of manufacturing the SF-MOS device (10,30) according to the invention.Type: GrantFiled: January 22, 2007Date of Patent: January 10, 2012Assignee: NXP B.V.Inventor: Sebastien Nuttinck
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Publication number: 20120001263Abstract: In replacement gate approaches for forming sophisticated high-k metal gate electrode structures in a late manufacturing stage, the exposing of the placeholder material may be accomplished on the basis of a substantially uniform interlayer dielectric material, for instance in the form of a silicon nitride material, which may have a similar removal rate compared to the dielectric cap material, the spacer elements and the like of the gate electrode structures. Consequently, a pronounced degree of recessing of the interlayer dielectric material may be avoided, thereby reducing the risk of forming metal residues upon removing any excess material of the gate metal.Type: ApplicationFiled: December 16, 2010Publication date: January 5, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Ralf Richter, Kai Frohberg
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Publication number: 20120001256Abstract: A semiconductor device includes: a first insulator pillar surrounding an active region; a second insulator pillar with a second side surface opposed in a y direction to a first side surface of the first insulator pillar on the active region side; an insulating film covering top surfaces of first and second insulator pillars; a second gate electrode electrically connected to the first gate electrode, covering at least the first and second side surfaces; and a gate contact plug in a contact hole and electrically connected to a top surface of the second gate electrode, the insulating film and the second gate electrode being exposed in a bottom of the contact hole. A distance between first and second side surfaces<a length of the gate contact plug in the y direction. The gate contact plug is electrically connected to the second gate electrodes between the first and second side surfaces.Type: ApplicationFiled: June 27, 2011Publication date: January 5, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Kazuhiro NOJIMA
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Publication number: 20110316084Abstract: A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material to expose the temporary spacer gates and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material. The method additionally includes filling the space between the active regions and above the remaining portion of the dielectric material with a gate material.Type: ApplicationFiled: September 9, 2011Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent A. ANDERSON, Edward J. NOWAK
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Publication number: 20110316083Abstract: A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region.Type: ApplicationFiled: June 25, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Pranita Kulkarni
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Patent number: 8084822Abstract: Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer.Type: GrantFiled: September 30, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Kiran V. Chatty, Robert J. Gauthier, Jr., Jed Hickory Rankin, Robert R. Robison, William Robert Tonti
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Patent number: 8080847Abstract: In one embodiment of the present invention an array of power transistors on a semiconductor chip has repeating patterns of two “wave” gates which have alternating longer and shorter horizontal sections which are offset mirror images of each other together with a third straight horizontal section. Alternating source and drain regions lie between adjacent gates. Contacts are located adjacent each side of sections of the “wave” gates which connect the ends of the horizontal sections of the “wave” gates.Type: GrantFiled: April 8, 2009Date of Patent: December 20, 2011Assignee: Fairchild Semiconductor CorporationInventor: Steven Leibiger
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Patent number: 8076204Abstract: A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region.Type: GrantFiled: April 22, 2010Date of Patent: December 13, 2011Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Publication number: 20110291196Abstract: Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.Type: ApplicationFiled: January 31, 2011Publication date: December 1, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Andy Wei, Vivien Schroeder, Thilo Scheiper, Thomas Werner, Johannes Groschopf
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Publication number: 20110284965Abstract: Reducing external resistance of a multi-gate device using spacer processing techniques is generally described.Type: ApplicationFiled: August 8, 2011Publication date: November 24, 2011Inventors: Ravi Pillarisetty, Uday Shah, Brian S. Doyle, Jack T. Kavalieros
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Publication number: 20110284874Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: ApplicationFiled: April 30, 2009Publication date: November 24, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Naoki Yutani
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Patent number: 8063447Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.Type: GrantFiled: August 6, 2008Date of Patent: November 22, 2011Assignee: Intel CorporationInventors: Ravi Pillarisetty, Jack Kavalieros, Marko Radosavljevic, Benjamin Chu-Kung
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Publication number: 20110272753Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.Type: ApplicationFiled: October 23, 2009Publication date: November 10, 2011Inventors: Kota Funayama, Hiraku Chakihara, Yasushi Ishii
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Patent number: 8053841Abstract: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.Type: GrantFiled: February 2, 2010Date of Patent: November 8, 2011Assignee: Hynix Semiconductor Inc.Inventors: Se-Aug Jang, Heung-Jae Cho, Kwan-Yong Lim, Tae-Yoon Kim
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Publication number: 20110266625Abstract: Gate failures in sophisticated high-k metal gate electrode structures formed in an early manufacturing stage may be reduced by forming a protective liner material after the incorporation of a strain-inducing semiconductor alloy and prior to performing any critical wet chemical processes. In this manner, attacks in the sensitive gate materials after the incorporation of the strain-inducing semiconductor material may be avoided, without influencing the further processing of the device. In this manner, very sophisticated circuit designs may be applied in sophisticated gate first approaches.Type: ApplicationFiled: December 8, 2010Publication date: November 3, 2011Applicant: GLOBALFOUNDRIES INC.Inventors: Richard Carter, Sven Beyer, Markus Lenski, Patrick Press
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Patent number: 8049214Abstract: A pair of split-gate fin field effect transistors (finFETs) in an IC, each containing a signal gate and a control gate, in which an adjustable voltage source, preferably in the form of a digital-to-analog-converter (DAC), is connected to the control gate of one of the finFETs, is disclosed. Threshold measurement circuits on the signal gates enable a threshold adjustment voltage from the adjustable voltage source to reduce the threshold mismatch between the finFETs. Adding a second DAC to the second finFET allows a simpler DAC design. Threshold correction may be performed during the operational life of the IC. Implementations in a differential input stage of an amplifier and in a current mirror circuit are described.Type: GrantFiled: August 10, 2009Date of Patent: November 1, 2011Assignee: Texas Instruments IncorporatedInventor: Andrew Marshall