Abstract: A transistor includes a trench formed in a semiconductor substrate. A conductive spacer is formed in the trench and offset from a first sidewall of the trench. A dielectric material is formed in the trench and surrounds the conductive spacer. A drift region is formed in the semiconductor substrate adjacent to the first sidewall and a first portion of a second sidewall of the trench. A drain region is formed in the drift region adjacent to a second portion of the second sidewall. A first gate region overlaps a portion of the drift region and is formed separate from the conductive spacer.

Abstract: A semiconductor device including a source region formed at one main face of a semiconductor substrate; a drain region formed at the one main face and connected to the source region through a channel region; a gate electrode formed above the channel region; a drift layer formed at the one main face at a position between a lower portion of the gate electrode and the drain region; a trench including an opening in which one end is at the lower portion of the gate electrode and another end is at a position adjacent to the drain region, the trench being formed in the semiconductor substrate at a predetermined depth from the one main face to cut vertically across the drift layer; and an electrical field weakening portion, provided at vicinity of the one end, that weaken an electrical field generated between the source region and the drain region.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor; and a capacitor having a first conductive layer and a second conductive layer and disposed on a second region of the second nitride semiconductor layer. Wherein the first conductive layer of the capacitor and the first source electrode have a first material, and the second conductive layer of the capacitor and the first field plate have a second material.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a gate structure, a drift region, a drain region, and an isolation structure. The gate structure is disposed on the semiconductor substrate. The drift region is disposed in the semiconductor substrate and partially disposed at a side of the gate structure. The drain region is disposed in the drift region. The isolation structure is at least partially disposed in the drift region. A part of the isolation structure is disposed between the drain region and the gate structure. The isolation structure includes a curved bottom surface.

Abstract: A semiconductor device includes an active region which is surrounded by a device isolation region on a semiconductor substrate and which extends in a first direction; a silicon pillar which separates the active region along the first direction into a first lower diffusion layer and a second lower diffusion layer; a first gate electrode covering a first side face of the silicon pillar which is located on a side of the first lower diffusion layer; a second gate electrode covering a second side face of the silicon pillar which is located on a side of the second lower diffusion layer; a conductive layer provided on a top face of the silicon pillar; and a device isolation insulating film contacting with a third side face of the silicon pillar which is different from the first side face and the second side face.

Abstract: Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor. Ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.

Abstract: A semiconductor device includes a semiconductor substrate with a trench, a body region under the trench with majority carrier dopants of a first type, and a transistor, including a source region under the trench with majority carrier dopants of a second type, a drain region spaced from the trench with majority carrier dopants of the second type, a gate structure in the trench proximate a channel portion of a body region, and an oxide structure in the trench proximate a side of the gate structure.

Abstract: Described are plasma immersion ion implantation methods that use multiple precursor gases, particularly for the purpose of controlling an amount of a specific atomic dopant species that becomes implanted into a workpiece relative to other atomic species that also become implanted into the workpiece during the implantation process.

Abstract: A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.

Abstract: A substrate treatment method for treating a substrate, includes: (a) applying a coating solution to a front surface of the substrate by a spin coating method to form a coating film; (b) supplying a solvent for the coating solution to a projection of the coating film formed at a front surface peripheral edge of the substrate at (a); and (c) rotating the substrate in a state where the supply of the solvent is stopped, to move a top of the projection to an outside in a radial direction of the substrate. (b) and (c) are repeatedly performed. The projection is a buildup of the coating solution protruding from the coating film.

Abstract: The present disclosure relates to a transistor device having source and drain regions within a substrate. A gate electrode is between the source and drain regions. A spacer has a lower lateral portion along an upper surface of the substrate between the gate electrode and the drain region, a vertical portion extending along a sidewall of the gate electrode, and an upper lateral portion extending from the vertical portion to an outermost sidewall directly over the gate electrode. A field plate is disposed along an upper surface and a sidewall of the spacer and is separated from the gate electrode and the substrate by the spacer. A first ILD layer overlies the substrate, the gate electrode, and the field plate. A first conductive contact has opposing outermost sidewalls intersecting a first horizontally extending surface of the field plate between the gate electrode and the drain region.

Abstract: The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.

Abstract: An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.

Abstract: A semiconductor device includes a first transistor group including first transistors, wherein each of the first transistors includes a first gate, and a first source and a first drain disposed symmetrically at both sides of the first gate and having a bent form; and a second transistor group including second transistors, wherein each of the second transistors includes a second gate, and a second source and a second drain disposed symmetrically at both sides of the second gate and having a bent form, wherein the first source and the first drain are bent in a direction opposite to a direction in which the second source and the second drain are bent.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type; a first electrode electrically connected to the first semiconductor layer; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type selectively provided on the second semiconductor layer; a second electrode electrically connected to the second semiconductor layer and the third semiconductor layer; a third electrode and a floating electrode provided from an upper surface side of the third semiconductor layer through the third semiconductor layer and the second semiconductor layer to the first semiconductor layer via a first insulating film; a second insulating film provided between the second electrode and the third electrode, the second electrode and the floating electrode.

Abstract: The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.

Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.

Abstract: An isolated device is formed in a substrate in which is formed a high voltage device. The isolated device includes: an isolated well formed in the substrate by a lithography process and an ion implantation process used in forming the high voltage device; a gate formed on the substrate; a source and a drain, which are located in the isolated well at both sides of the gate respectively; a drift-drain region formed beneath the substrate surface, wherein the gate and the drain are separated by the drift-drain region, and the drain is in the drift-drain region; and a mitigation region, which is formed in the substrate and has a shallowest portion located at least below 90% of a depth of the drift-drain region as measured from the substrate surface, wherein the mitigation region and the drift-drain region are defined by a same lithography process.

Abstract: A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line.

Abstract: A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.

Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.

Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.

Abstract: In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

Abstract: An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.

Abstract: A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.

Abstract: A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided.

Abstract: Disclosed herein is a device for electrostatic discharge protection. According to the present invention, the device for electrostatic discharge protection comprises a semiconductor substrate, a plurality of element isolation films formed in predetermined regions on the semiconductor substrate, a gate formed in a predetermined region on the semiconductor substrate between the element isolation films, a well pick-up region formed in a predetermined region on the semiconductor substrate between the element isolation films, a source formed in a predetermined region on the semiconductor substrate between the element isolation film and the gate, and drains of a triple structure, which are formed in a predetermined region on the semiconductor substrate between the gate and the element isolation film. Furthermore, the gate, the well pick-up region and the source are connected to a ground line, and the drain is connected to a power line. Accordingly, a stable and good ESD protection performance can be implemented.

Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.

Abstract: A semiconductor device includes: a p-type active region; a gate electrode traversing the active region; an n-type LDD region having a first impurity concentration and formed from a drain side region to a region under the gate electrode; a p-type channel region having a second impurity concentration and formed from a source side region to a region under the gate electrode to form an overlap region with the LDD region under the gate electrode, the channel region being shallower than the LDD region; an n-type source region formed outside the gate electrode; and an n+-type drain region having a third impurity concentration higher than the first impurity concentration formed outside and spaced from the gate electrode, wherein an n-type effective impurity concentration of an intermediate region between the gate electrode and the n+-type drain region is higher than an n-type effective impurity concentration of the overlap region.

Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.

Abstract: A semiconductor device comprises a vertical MOS transistor including a semiconductor substrate having a silicon pillar, a gate electrode formed along a sidewall of the silicon pillar, a gate insulating film formed between the gate electrode and the silicon pillar, an upper diffusion layer formed on the top of the silicon pillar, and a lower diffusion layer formed lower than the upper diffusion layer in the semiconductor substrate; and a pad electrically connected to the lower diffusion layer. Breakdown occurs between the lower diffusion layer and the semiconductor substrate when a surge voltage is applied.

Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; and a gate electrode over the gate dielectric. A first source/drain region is adjacent the gate dielectric, wherein the first source/drain region is a semiconductor region and of a first conductivity type. A second source/drain region is on an opposite side of the channel region than the first source/drain region, wherein the second source/drain region is a metal region. A pocket region of a second conductivity type opposite the first conductivity type is horizontally between the channel region and the second source/drain region.

Abstract: In an extended drain MOS device used in high voltage applications, switching characteristics are improved by providing for at least one base contact in the active region in the extended drain space.

Abstract: According to one embodiment, a semiconductor device including a tunnel FET, includes a gate electrode, which is formed on a first semiconductor layer formed of Si1?XGeX (0<x?1) through a gate insulating film, a source electrode, which is formed of a compound of a second semiconductor formed mainly using Ge and a metal, a drain electrode, which is formed of a compound of the first semiconductor layer and the metal, and a silicon (Si) thin film, which is formed between the source electrode and the first semiconductor layer. An edge portion of the source electrode and an edge portion of the drain electrode have a positional relationship of Asymmetrical to the gate electrode. The edge portion of the drain electrode is far away from an edge portion of the gate electrode toward a gate external direction compared with the edge portion of the source electrode.

Abstract: According to an exemplary embodiment, a MOS transistor, such as an LDMOS transistor, includes a gate having a first side situated immediately adjacent to at least one source region and at least one body tie region. The MOS transistor further includes a drain region spaced apart from a second side of the gate. The MOS transistor further includes a body region in contact with the at least one body tie region, where the at least one body tie region is electrically connected to the at least one source region. The MOS transistor further includes a lightly doped region separating the drain region from the second side of the gate. The lightly doped region can isolate the body region from an underlying substrate.

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TPET, the drain region comprises p-doped silicon, while the source region comprises n-doped SiC.

Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract: A semiconductor device includes: an active region defined by a device isolation layer on and/or over a substrate; a second conductive well on and/or over the active region; an extended drain formed at one side of the second conductive well; a gate electrode on and/or over the second conductive well and the extended drain; and a source and a drain formed at both sides of the gate electrode, in which extended regions are formed at the corners of the second conductive well under the gate electrode.

Abstract: A via contact is provided to a diffusion region at a top surface of a substrate which includes a single-crystal semiconductor region. The via contact includes a first layer which consists essentially of a silicide of a first metal in contact with the diffusion region at the top surface. A dielectric region overlies the first layer, the dielectric region having an outer surface and an opening extending from the outer surface to the top surface of the substrate. A second layer lines the opening and contacts the top surface of the substrate in the opening, the second layer including a second metal which lines a sidewall of the opening and a silicide of the second metal which is self-aligned to the top surface of the substrate in the opening. A diffusion barrier layer overlies the second layer within the opening. A third layer including a third metal overlies the diffusion barrier layer and fills the opening.

Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.

Abstract: A semiconductor device and its method of manufacture are provided. Embodiments forming an active region in a semiconductor substrate, wherein the active region is bounded by an isolation region; forming a first doped region within the active region; forming a gate electrode over the active region, wherein the gate electrode overlies a portion of the first doped region; forming at least one dielectric layer over sidewalls of the gate electrode; forming a pair of spacers on the dielectric layer; and forming a second doped region substantially within the portion of the first doped region adjacent the one of the spacers and spaced apart from the one of the spacers. The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor.

Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.

Abstract: A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.