Abstract: A thin film transistor (TFT) is provided, which includes a gate, a semiconductor layer, an insulation layer, a source and a drain. The semiconductor layer has a first end and a second end opposite to the first end. The insulation layer is disposed between the gate and the semiconductor layer. The source clamps the first end of the semiconductor layer and the drain clamps the second end of the semiconductor layer.

Abstract: Methods and apparatus provide for a transistor, including: a semiconductor layer including molecules, protons, and/or ions, etc. diffused therein from a photoactive material; a channel disposed on or in the semiconductor layer; a source disposed on or in the semiconductor layer; a drain disposed on or in the semiconductor layer; and a gate electrically coupled to the semiconductor layer.

Abstract: A method and system for setting the direction of pinned layers in a magnetic junction are described. In one aspect, a magnetic field greater than the coercivity of the layers in a pinned layer but less than the coupling field between the layers is applied. In another aspect the pinned layers are switched from an anti-dual state to a dual state using a spin transfer torque current. In another aspect, a magnetic junction having a partial perpendicular anisotropy (PPMA) layer in the pinned layer is provided. In some aspects, the PPMA layer is part of a synthetic antiferromagnetic structure. In some embodiments, a decoupling layer is provided between the PPMA layer and another ferromagnetic layer in the pinned layer.

Abstract: Disclosed is a semiconductor device wherein device characteristics are improved by applying a strong stress to a channel region. The semiconductor device includes a semiconductor substrate, a gate insulating film formed over a first plane of the semiconductor substrate, a gate electrode formed over the gate insulating film, a gate sidewall insulating film formed over the sidewall of the gate electrode, source/drain diffusion layer regions into which impurities are implanted, the source/drain diffusion layer regions being adjacent to a channel region formed in the semiconductor substrate below the gate electrode, and a stress applying film formed over the source/drain diffusion layer regions except over the upper part of the gate electrode; and recesses or protrusions are formed in the region where the source/drain diffusion layer regions are formed over the first plane of the semiconductor substrate.

Abstract: To provide a semiconductor device with a TFT, capable of reducing the electric resistance of a power supply wiring without increasing the off-current. The semiconductor device includes an insulating film with a surface; a semiconductor layer which is formed over the surface of the insulating film and which includes a channel region and a pair of source/drain regions and sandwiching the channel region; and a power supply wiring for supplying power to the source region. A concave portion is formed in the surface of the insulating film. The power supply wiring includes a layer formed from the same layer as the semiconductor layer, and has a first portion formed over the surface of the insulating film and a second portion formed in the concave portion. The bottom of the second portion is covered with an insulator.

Abstract: Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may have a top electrical contact that is physically and electrically connected to sidewalls of the array of nanostructures (e.g., nanocolumns). The top electrical contact may be located such that light can enter or leave the nanostructures without passing through the top electrical contact. Therefore, the top electrical contact can be opaque to light having wavelengths that are absorbed or generated by active regions in the nanostructures. The top electrical contact can be made from a material that is highly conductive, as no tradeoff needs to be made between optical transparency and electrical conductivity. The device could be a solar cell, LED, photo-detector, etc.

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle ?1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle ?2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract: The invention relates to a method for forming a pattern on a substrate (S) with an upper surface and a lower surface which comprises the steps of depositing a first layer (E1) of an opaque material on the upper surface of the substrate (S), depositing a photosensitive layer (R) such that part of the photosensitive layer (R) covers at least part of the first layer (E1), exposing the photosensitive layer (R) to a light beam (L), the light beam (L) impinging on the lower surface of the substrate (S) under an oblique angle (?) of incidence, removing the exposed region of the photosensitive layer (R), depositing a second layer (E2) of an opaque material such that part of the second layer (E2) covers a remaining region of the photosensitive layer (R), and removing at least a part of the remaining region of the photosensitive layer (R).

Abstract: A transistor includes a gate electrode, a gate insulating layer, a semiconductor layer including an amorphous oxide, source-drain electrodes, and a protective layer on a substrate. The semiconductor layer includes a first region corresponding to a region in which the source-drain electrodes are formed, and a second region not corresponding to the region in which the source-drain electrodes are formed. At least the first region includes a crystalline component having a composition different from the composition of the amorphous oxide in the second region.

Abstract: An oxide semiconductor thin-film transistor, comprising: a source electrode and a drain electrode formed on a substrate; a composite semiconductor active layer formed between the source electrode and the drain electrode; a gate dielectric layer formed on the source electrode, the composite semiconductor active layer and the drain electrode; and a gate electrode formed on the gate dielectric layer and corresponding to the composite semiconductor active layer; wherein the composite semiconductor active layer comprises a low carrier-concentration first oxide semiconductor layer and a high carrier-concentration second oxide semiconductor layer.

Abstract: This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: A method is for producing an asymmetric architecture semiconductor device. The device includes a substrate, and in stacked relation, a first photosensitive layer, a non-photosensitive layer, and a second photosensitive layer. The method includes a first step of exposing a first zone in each of the photosensitive layers by a first beam of electrons traversing the non-photosensitive layer. A second step includes exposing at least one second zone of one of the two photosensitive layers by a second beam of electrons or photons or ions, thereby producing a widening of one of the first zones compared to the other first zone such that the second zone is in part superimposed on one of the first zones.

Abstract: Oxide semiconductor thin film transistors (TFT) and methods of manufacturing the same are provided. The methods include forming a channel layer on a substrate, forming source and drain electrodes at opposing sides of the channel layer, and oxidizing a surface of the channel layer by placing an oxidizing material in contact with the surface of the channel layer, reducing carriers on the surface of the channel layer. Due to the oxidizing agent treatment of the surface of the channel layer, excessive carriers that are generated naturally, or during the manufacturing process, may be more effectively controlled.

Abstract: An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a layer with high crystallinity which is formed later in a microcrystalline semiconductor film. Further, the layer including an impurity element is used as a channel formation region. Furthermore, a layer which does not include an impurity element imparting one conductivity type or a layer which has an impurity element imparting one conductivity type at an extremely lower concentration than other layers, is provided between a pair of semiconductor films including an impurity element functioning as a source region and a drain region and the layer including an impurity element functioning as a channel formation region.

Abstract: A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure (114). Source and drain regions (140, 142) are then formed (26) within the semiconductor substrate (102) on opposing sides of the channel (122) with a phosphorus dopant.

Abstract: Phosphorus is implanted into a crystalline semiconductor film by an ion dope method. However, a concentration of phosphorus required for gettering is 1×1020/cm3 or higher which hinders recrystallization by later anneal, and thus this becomes a problem. Also, when phosphorus is added at a high concentration, processing time required for doping is increased and throughput in a doping step is reduced, and thus this becomes a problem. The present invention is characterized in that impurity regions to which an element belonging to the group 18 of the periodic table is added are formed in a semiconductor film having a crystalline structure and gettering for segregating in the impurity regions a metal element contained in the semiconductor film is performed by heat treatment. Also, a one conductivity type impurity may be contained in the impurity regions.

Abstract: A semiconductor device having high electrical characteristics is manufactured at low cost and with high throughput. A semiconductor film is crystallized or activated by being irradiated with a laser beam emitted from one fiber laser. Alternatively, laser beams are emitted from a plurality of fiber lasers and coupled by a coupler to be one laser beam, and then a semiconductor film is irradiated with the coupled laser beam so as to be crystallized or activated.

Abstract: MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.

Abstract: Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.

Abstract: In a semiconductor substrate (1), impurity material, for example a metal, is distributed in a layer-like zone (3) in such a way that said zone reflects radiation (6), which is generated or detected by an optoelectronic component, for example. Said layer-like zone (3) is fabricated by implantation of the impurity material into the substrate (1) and subsequent heat treatment for crystallization of the impurity material. Such a substrate is suitable in particular for avoiding the penetration of radiation (6), which is generated for example by radiation-emitting structures (5) applied to the substrate, by reflection in a region of the substrate (1) near the surface and thus for reducing the absorption losses.

Abstract: Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

Abstract: In a display device including thin film transistors formed on an insulation substrate, the thin film transistor includes a semiconductor layer, a gate electrode and a gate insulation film which is interposed between the semiconductor layer and the gate electrode. The gate insulation film includes at least one layer of deposition film which is deposited by a deposition method, and the carbon concentration of the gate insulation film which is formed without interposing other deposition film deposited by a deposition method between the one deposition film and the semiconductor layer has the distribution in which the carbon concentration is smaller at a side close to the semiconductor layer than at a side remote from the semiconductor layer.

Abstract: A pixel structure controlled by a scan line and a data line on a substrate is provided. The pixel structure comprises a thin film transistor, a resistance wire, a first pixel electrode, and a second pixel electrode, which are disposed on the substrate. Additionally, the thin film transistor is electrically connected to the scan line, the data line, and the resistance wire. Further, the first pixel electrode is electrically connected to the thin film transistor and the second pixel electrode is electrically connected to the thin film transistor by the resistance wire. Especially, a method of manufacturing a pixel structure is also provided.

Abstract: A method of manufacturing a thin-film semiconductor device substrate includes a step of forming a non-single crystalline semiconductor thin film on a base layer, and an annealing step of irradiating the non-single crystalline semiconductor thin film with an energy beam to enhance crystallinity of a non-single crystalline semiconductor constituting the non-single crystalline semiconductor thin film. The annealing step includes simultaneously irradiating the non-single crystalline semiconductor thin film with a plurality of energy beams to form a plurality of unit regions each including at least one irradiated region irradiated with the energy beam and at least one non-irradiated region that is not irradiated with the energy beam.