Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

Abstract: Disclosed is a semiconductor device, including: a substrate of a first conductivity type that is a base for the semiconductor device; a high voltage junction field effect transistor, JFET, over the substrate, wherein the JFET including a plurality of parallel conductive layers; and a first conductive layer of the second conductivity type of the parallel conductive layers stretching over the substrate. On top of the first conductive layer of the second conductivity type is arranged a plurality of layers forming the parallel conductive layers with channels formed by a plurality of doped epitaxial layers of the second conductivity type with a plurality of gate layers of the first conductivity type on both sides thereof; wherein a lowermost layer of the first conductivity type is arranged in the form of consecutive dots with different lengths and distances between them.

Abstract: A transistor having a vertical structure can include a substrate, a first electrode disposed on the substrate, a second electrode disposed on the substrate, an insulation pattern disposed between the first electrode and the second electrode, an active layer connected between the first electrode and the second electrode, a channel area of the active layer disposed along a side surface of the insulation pattern and around an upper edge of the insulation pattern, a gate electrode disposed on the active layer, and a gate insulating film disposed between the gate electrode and the active layer.

Abstract: The present invention provides the compound represented by Formula 1, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode, and electronic device thereof, and by employing the compound represented by Formula 1 in the organic material layer, the driving voltage of the organic electric element can be lowered, and the luminous efficiency and life time of the electric element can be improved.

Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.

Abstract: A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device. Embodiments of the disclosed invention include spacers made from different materials, having different or substantially equal thicknesses.

Abstract: The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes a SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.

Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.

Abstract: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and the drain region. In another embodiment device destruction at high voltages is prevented by ballasting the FinFET. Specifically, resistance is optimized in the fin between the gate and both the source and drain regions (e.g., by increasing fin length, by blocking source/drain implant from the fin, and by blocking silicide formation on the top surface of the fin) so that the FinFET is operable at a predetermined maximum voltage.

Abstract: An organic EL display including a plurality of pixels each having, in order from a substrate side, a first electrode, an organic layer including a light emission layer, and a second electrode; an auxiliary wiring disposed in a periphery region of each of the plurality of pixels and conducted to the second electrode; and another auxiliary wiring disposed apart from the auxiliary wiring at least in a part of outer periphery of a formation region of the auxiliary wiring in a substrate surface.

Abstract: An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

Abstract: According to an exemplary embodiment, a MOS transistor, such as an LDMOS transistor, includes a gate having a first side situated immediately adjacent to at least one source region and at least one body tie region. The MOS transistor further includes a drain region spaced apart from a second side of the gate. The MOS transistor further includes a body region in contact with the at least one body tie region, where the at least one body tie region is electrically connected to the at least one source region. The MOS transistor further includes a lightly doped region separating the drain region from the second side of the gate. The lightly doped region can isolate the body region from an underlying substrate.

Abstract: A technology is capable of simplifying a process of manufacturing an asymmetric device in forming a Tunneling Field Effect Transistor (TFET) structure. A method for manufacturing a semiconductor device comprises forming a conductive pattern over a semiconductor substrate, implanting impurity ions with the conductive pattern as a mask to form a first junction region in the semiconductor substrate, forming a first insulating film planarized with the conductive pattern over the first junction region, etching the top of the conductive pattern to expose a sidewall of the first insulating film, forming a spacer at the sidewall of the first insulating film disposed over the conductive pattern, etching the conductive pattern with the spacer as an etching mask to form a gate pattern, and forming a second junction region in the semiconductor substrate with the gate pattern as a mask.

Abstract: According to one exemplary embodiment, an asymmetric transistor includes a channel region having a drain-side channel portion and a source-side channel portion. The asymmetric transistor can be an asymmetric MOSFET. The source-side channel portion can comprise silicon, for example. The drain-side channel portion can comprise germanium, for example. The asymmetric transistor comprises a vertical heterojunction situated between the drain-side channel portion and the source-side channel portion. According to this exemplary embodiment, the bandgap of the source-side channel portion is higher than the bandgap of the drain-side channel portion and the carrier mobility of the drain-side channel portion is higher than the carrier mobility of the source-side channel portion. The transistor can further include a gate oxide layer situated over the drain-side channel portion and the source-side channel portion, and can also include a gate situated over the gate oxide layer.

Abstract: Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E).

Abstract: Provided is a manufacturing method for an offset MOS transistor capable of operating safely even under a voltage of 50 V or higher. In the offset MOS transistor which includes a LOCOS oxide film, the LOCOS oxide film formed in a periphery of a drain diffusion layer, in which a high withstanding voltage is required, is etched, and the drain diffusion layer is formed so as to spread into a surface region of a semiconductor substrate located below a region in which the LOCOS oxide film is thinned. As a result, end portions of the drain diffusion layer are covered by an offset diffusion layer, whereby electric field concentration occurring in a region of a lower portion of the drain diffusion layer can be relaxed.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: An LCD device is disclosed, to minimize the signal distortion by decreasing the instability of voltage in a-Si:H TFT of a gate driving signal output unit, which includes a signal controller for outputting first and second control signals Q and /Q; a pull-up transistor between a clock signal terminal CLK and a gate driving signal output terminal for receiving the first control signal Q, the pull-up transistor having a first gate electrode, a first source electrode and a first drain electrode, wherein the pull-up transistor has an asymmetric structure in a first area of the first source electrode overlapped with the first gate electrode and a second area of the first drain electrode overlapped with the first gate electrode; and a pull-down transistor connected between the gate driving signal output terminal and a ground voltage terminal, wherein the pull-down transistor receives the second control signal.

Abstract: Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics.

Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.

Abstract: The present invention provides an organic EL display and a method of manufacturing the same capable of assuring excellent electric connection between an auxiliary wiring and a second electrode without using large-scale equipment. The organic EL display includes: a plurality of pixels each having, in order from a substrate side, a first electrode, an organic layer including a light emission layer, and a second electrode; an auxiliary wiring disposed in a periphery region of each of the plurality of pixels and conducted to the second electrode; and another auxiliary wiring disposed apart from the auxiliary wiring at least in a part of outer periphery of a formation region of the auxiliary wiring in a substrate surface.

Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.

Abstract: A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.

Abstract: A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and implanting ions in the substrate at an angle (?) to form a source region and a drain region in the substrate, wherein the angle (?) is oblique relative to the source region.

Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

Abstract: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and the drain region. In another embodiment device destruction at high voltages is prevented by ballasting the FinFET. Specifically, resistance is optimized in the fin between the gate and both the source and drain regions (e.g., by increasing fin length, by blocking source/drain implant from the fin, and by blocking silicide formation on the top surface of the fin) so that the FinFET is operable at a predetermined maximum voltage.

Abstract: A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: A semiconductor structure includes a symmetric metal-oxide-semiconductor (MOS) transistor comprising a first and a second asymmetric MOS transistor. The first asymmetric MOS transistor includes a first gate electrode, and a first source and a first drain adjacent the first gate electrode. The second asymmetric MOS transistor includes a second gate electrode, and a second source and a second drain adjacent the second gate electrode. The first gate electrode is connected to the second gate electrode, wherein only one of the first source and the first drain is connected to only one of the respective second source and the second drain.

Abstract: An LCD device is disclosed, to minimize the signal distortion by decreasing the instability of voltage in a—Si:H TFT of a gate driving signal output unit, which includes a signal controller for outputting first and second control signals Q and /Q; a pull-up transistor between a clock signal terminal CLK and a gate driving signal output terminal for receiving the first control signal Q, the pull-up transistor having a first gate electrode, a first source electrode and a first drain electrode, wherein the pull-up transistor has an asymmetric structure in a first area of the first source electrode overlapped with the first gate electrode and a second area of the first drain electrode overlapped with the first gate electrode; and a pull-down transistor connected between the gate driving signal output terminal and a ground voltage terminal, wherein the pull-down transistor receives the second control signal.

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium.

Abstract: A structure and method of forming a body contact for a semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.

Abstract: A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.

Abstract: The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type source/drain extension and a first P-type pocket region extend from the P region toward the N region with the pocket region located under the source/drain extension and extending under the gate. A second N-type source/drain extension and a second P-type pocket region extend from the N region toward the P region with the pocket region located under the source/drain extension and extending under the gate. Preferably, the gate itself is heavily doped so that one half of the gate on the side adjacent the heavily doped P region is also heavily doped with dopants of P-type conductivity and the other half of the gate on the side adjacent the heavily doped N region is also heavily doped with dopants of N-type conductivity.

Abstract: By providing a substantially non-damaged semiconductor region between a pre-amorphization region and the gate electrode structure, an increase of series resistance at the drain side during the re-crystallization may be reduced, thereby contributing to overall transistor performance, in particular in the linear operating mode. Thus, symmetric and asymmetric transistor architectures may be achieved with enhanced performance without unduly adding to overall process complexity.

Abstract: According to one embodiment of the present invention, a method of forming a semiconductor device is provided, the method including: forming a substrate; forming a first gate on the substrate; forming a mask layer on the substrate, the mask layer including a first window covering an area within which the first gate is formed so that the first gate divides the substrate exposed by the first window into a first region and a second region; and doping the exposed substrate using rays inclined with respect to the substrate top surface, where the position of the first gate with respect to a border of the first window is chosen such that the inclined doping rays impinge more on the first region than on the second region.

Abstract: Image sensor devices are provided having reduced dark current generation characteristics. These image sensor devices include a semiconductor substrate and a photo-detector therein (e.g., P-N photodiode). The photo-detector includes a charge-generating region therein that is configured to convert photons received by the photo-detector into charge carriers. A first transistor, which has a terminal configured to receive the charge carriers generated by the photo-detector, is also provided. The first transistor includes a first gate electrode and a first pair of lightly doped source and drain regions of unequal width on opposite sides of the first gate electrode. This first transistor may be a three-terminal device and the terminal that is configured to receive the charge carriers may be selected from a group consisting of a gate, source and drain terminals. In particular, the first transistor may be configured as a reset transistor or as a source-follower transistor.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device, such as a field effect transistor, that includes a spacer shaped metal gate located over a channel within a semiconductor substrate that separates a plurality of source and drain regions within the semiconductor substrate. Within the semiconductor structure, the plurality of source and drain regions is asymmetric with respect to the spacer shaped metal gate. The particular semiconductor structure may be fabricated using a self aligned dummy gate method that uses a portion of a spacer as a self alignment feature when forming the spacer shaped metal gate, which may have a sub-lithographic linewidth.

Abstract: It is an object of the present invention to manufacture a thin film transistor having a required property without complicating steps and devices. It is another object of the present invention to provide a technique for manufacturing a semiconductor device having high reliability and better electrical characteristics with a higher yield at lower cost. In the present invention, a lightly doped impurity region is formed in a source region side or a drain region side of a semiconductor layer covered with a gate electrode layer in a thin film transistor. The semiconductor layer is doped diagonally to the surface thereof using the gate electrode layer as a mask to form the lightly doped impurity region. Therefore, the properties of the thin film transistor can be minutely controlled.

Abstract: A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.

Abstract: It is an object to improve operation characteristics and reliability of a semiconductor device. A semiconductor device which includes an island-shaped semiconductor film having a channel-formation region, a first low-concentration impurity region, a second low-concentration impurity region, and a high-concentration impurity region including a silicide layer; a gate insulating film; a first gate electrode overlapping with the channel-formation region and the first low-concentration impurity region with the gate insulating film interposed therebetween; a second gate electrode overlapping with the channel-formation region with the gate insulating film and the first gate electrode interposed therebetween; and a sidewall formed on side surfaces of the first gate electrode and the second gate electrode. In the semiconductor device, a thickness of the gate insulating film is smaller in a region over the second low-concentration impurity region than in a region over the first low-concentration impurity region.

Abstract: Sidewall spacers on the gate of a MOS device are formed from stressed material so as to provide strain in the channel region of the MOS device that enhances carrier mobility. In a particular embodiment, the MOS device is in a CMOS cell that includes a second MOS device. The first MOS device has sidewall spacers having a first (e.g., tensile) type of residual mechanical stress, and the second MOS device has sidewall spacers having a second (e.g., compressive) type of residual mechanical stress. Thus, carrier mobility is enhanced in both the PMOS portion and in the NMOS portion of the CMOS cell.

Abstract: A manufacturing method for a display device having a first conductive type thin film transistor and a second conductive type thin film transistor, comprising the steps of: in formation regions for a first conductive type thin film transistor and a second conductive type thin film transistor forming a semiconductor layer, a first insulating film covering the semiconductor layer and a gate electrode disposed on the first insulating film so as to intersect the semiconductor layer, on substrate having first conductive type impurity regions on both outer sides of a channel region of the semiconductor layer below the gate electrode forming a second insulating film, in the second insulating film and the first insulating film forming a contact hole for a drain electrode and a source electrode, in the formation region for the second conductive type thin film transistor forming electrodes and a second conductive type impurity region.

Abstract: In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.

Abstract: A method of fabricating a high voltage MOS transistor with a medium operation voltage on a semiconductor wafer. The transistor has a double diffused drain (DDD) and a medium operation voltage such as 6 to 10 volts, which is advantageous for applications having both low and higher operation transistor devices. The second diffusion region of the DDD is self-aligned to the spacer on the sidewalls of the gate and gate dielectric, so that the transistor size may be decreased.

Abstract: A crystalline semiconductor film in which the position and size of a crystal grain is controlled is fabricated, and the crystalline semiconductor film is used for a channel formation region of a TFT, so that a high performance TFT is realized. An island-like semiconductor layer is made to have a temperature distribution, and a region where temperature change is gentle is provided to control the nucleus generation speed and nucleus generation density, so that the crystal grain is enlarged. In a region where an island-like semiconductor layer 1003 overlaps with a base film 1002, a thick portion is formed in the base film 1002. The volume of this portion increases and heat capacity becomes large, so that a cycle of temperature change by irradiation of a pulse laser beam to the island-like semiconductor layer becomes gentle (as compared with other thin portion).

Abstract: An unstable factor that the orientation of liquid crystal is fixed and left after a drive power source is turned off is reduced, preferable display quality is realized, and long term reliability is improved. After the drive power source is turned off, in order to block an electric field produced by charges left in a first electrode (485), a second electrode 492 is provided to overlap the first electrode. The first electrode is overlapped at 70% or more of its area with the second electrode. In addition, when the first electrode is used as an electrode composing a retaining capacitor 505, the retaining capacitor is overlapped at 90% or more of its area with the second electrode.

Abstract: A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gate electrode; a control gate electrode provided on the second gate insulation film; a source layer and a drain layer that are provided in the semiconductor substrate, the source layer and the drain layer respectively being provided either side of a channel region which is below the floating gate electrode; a source electrode that is electrically connected to the source layer; a buffer film provided on the drain layer; and a memory cell including a drain electrode electrically connected to the drain layer through the buffer film, wherein when viewing the surface of the semiconductor substrate from above, an overlapped area between the floating gate electrode and the drain layer is smaller than an overlapped area between the floating gate electrode an

Abstract: The present invention discloses a high-speed flat panel display with a long lifetime, wherein thin film transistors in a pixel array portion in which a plurality of pixels are arranged and a driving circuit portion for driving the pixels of the pixel array portion, have different resistance values than each other or have different geometric structures than each other. The flat panel display comprises a pixel array portion where a plurality of pixels are arranged, and a driving circuit portion for driving the pixels of the pixel array portion. The thin film transistors in the pixel array portion and the driving circuit portion have different resistance values in their gate regions or drain regions than each other, or have different geometric structures than each other. One of the thin film transistors in the pixel array portion and the thin film transistors in the driving circuit has zigzag shape in its gate region or drain region or has an offset region.