Abstract: A photosensitive imaging device and a method for forming a semiconductor device are provided. The method includes: providing a first device layer formed on a first substrate, wherein a conductive top bonding pad layer is formed on the first device layer; providing a continuous second device layer formed on a second substrate, wherein a continuous conductive adhesion layer is formed on the continuous second device layer; bonding the first device layer with the second device layer, where the top bonding pad layer on the first device layer is directly connected with the conductive continuous adhesion layer on the continuous second device layer; removing the second substrate; selectively etching the continuous second device and the continuous conductive adhesion layer to form a groove array; and filling up the groove array with an insulation material to form a plurality of second devices. Alignment accuracy may be improved.

Abstract: Semiconductor devices and methods of forming the same. The method includes providing a semiconductor substrate having a channel layer over the substrate. A capping layer including silicon and having a first thickness is formed over the channel layer. The capping layer is partially oxidized to form an oxidized portion of the capping layer. The oxidized portion of the capping layer is removed to form a thinned capping layer having a second thickness less than the first thickness.

Abstract: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.

Abstract: Transistors, semiconductor memory cells having a transistor and methods of forming the same are provided, the transistors may include a semiconductor substrate having a first semiconductor region. A gate pattern may be disposed on the first semiconductor region. Spacer patterns may each be disposed on a sidewall of the gate pattern. Second semiconductor regions and a third semiconductor regions may be disposed in the semiconductor substrate. The second semiconductor regions may be disposed under the spacer patterns. The third semiconductor regions may be disposed adjacent to the second semiconductor regions. The first semiconductor region may have a higher impurity ion concentration than the second semiconductor regions.

Abstract: An object is to provide a transistor in which light deterioration is suppressed as much as possible and electrical characteristics are stable, and a semiconductor device including the transistor. The attention focuses on the fact that light is reflected by a film used for forming a transistor and multiple interaction occurs. When the optical thickness of the film which causes the reflection is roughly an odd multiple of ?0/4 or roughly an even multiple of ?0/4, reflectance in a wavelength region of light which is absorbed by an oxide semiconductor is increased without a loss of a function of the film with respect to the transistor, whereby the amount of light absorbed by the oxide semiconductor is reduced and an effect of reducing light deterioration is increased.

Abstract: A thin film transistor comprising: a substrate; a gate electrode on the substrate; a gate insulation film on the gate electrode; an oxide semiconductor layer on the gate insulation film; a channel protection film on the oxide semiconductor layer; source and drain electrodes on the channel protection film; and a passivation film on the source and drain electrodes, wherein, (a) each of the gate insulation film, and passivation film comprises a laminated structure and includes a first layer made of aluminum oxide and a second layer made of an insulation material including silicon, and (b) the passivation film covers edges of the oxide semiconductor layer. The transistor is capable of suppressing desorption of oxygen and from the oxide semiconductor layer and reducing the time for film formation thereof.

Abstract: A thin film transistor having a channel region including a nanoconductor layer. The nanoconductor layer can be a dispersed monolayer of nanotubes or nanowires formed of carbon. The thin film transistor generally includes a gate terminal insulated by a dielectric layer. The nanoconductor layer is placed on the dielectric layer and a layer of semiconductor material is developed over the nanoconductor layer to form the channel region of the thin film transistor. A drain terminal and a source terminal are then formed on the semiconductor layer. At low field effect levels, the operation of the thin film transistor is dominated by the semiconductor layer, which provides good leakage current performance. At high field effect levels, the charge transfer characteristics of the channel region are enhanced by the nanoconductor layer such that the effective mobility of the thin film transistor is enhanced.

Abstract: A semiconductor device of the present invention includes: a lower electrode (110); a contact layer (130) including a first contact layer (132), a second contact layer (134) and a third contact layer (136) overlapping with a semiconductor layer (120); and an upper electrode (140) including a first upper electrode (142), a second upper electrode (144) and a third upper electrode (146). The second contact layer (134) includes a first region (134a), and a second region (134b) separate from the first region (134a), and the second upper electrode (144) is directly in contact with the semiconductor layer (120) in a region between the first region (134a) and the second region (134b) of the second contact layer (134).

Abstract: Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls.

Abstract: A thin-film transistor (TFT) substrate having reduced defects is fabricated using a reduced number of masks. The TFT substrate includes gate wiring formed on a substrate. The gate wiring includes a gate electrode. A semiconductor pattern is formed on the gate wiring. An etch-stop pattern is formed on the semiconductor pattern. Data wiring includes a source electrode which is formed on the semiconductor pattern and the etch-stop pattern. Each of the gate wiring and the data wiring includes a copper-containing layer and a buffer layer formed on or under the copper-containing layer.

Abstract: A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

Abstract: A transistor device having a metallic source electrode, a metallic drain electrode, a metallic gate electrode and a channel in a deposited semiconductor material, the transistor device comprising: a first layer comprising the metallic gate electrode, a first metal portion of the metallic source electrode and a first metal portion of the metallic drain electrode; a second layer comprising a second metal portion of the metallic source electrode, a second metal portion of the metallic drain electrode, the deposited semiconductor material and dielectric material between the semiconductor material and the metallic gate electrode; and a third layer comprising a substrate, wherein the first, second and third layers are arranged in order such that the second layer is positioned between the first layer and the third layer.

Abstract: A thin film transistor includes a gate electrode formed on a substrate, a semiconductor pattern overlapped with the gate electrode, a source electrode overlapped with a first end of the semiconductor pattern and a drain electrode overlapped with a second end of the semiconductor pattern and spaced apart from the source electrode. The semiconductor pattern includes an amorphous multi-elements compound including a II B element and a VI A element or including a III A element and a V A element and having an electron mobility no less than 1.0 cm2/Vs and an amorphous phase, wherein the VI A element excludes oxygen. Thus, a driving characteristic of the thin film transistor may be improved.

Abstract: An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.

Abstract: Provided are a thin film transistor that is capable of suppressing desorption of oxygen and others from an oxide semiconductor layer, and reducing the time to be taken for film formation, and a display device provided therewith. A gate insulation film 22, a channel protection layer 24, and a passivation film 26 are each in the laminate configuration including a first layer 31 made of aluminum oxide, and a second layer 32 made of an insulation material including silicon (Si). The first and second layers 31 and 32 are disposed one on the other so that the first layer 31 comes on the side of an oxide semiconductor layer 23. The oxide semiconductor layer 23 is sandwiched on both sides by the first layers 31 made of aluminum oxide, thereby suppressing desorption of oxygen and others, and stabilizing the electrical characteristics of a TFT 20.

Abstract: A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconductor and opposite to each other. The semiconductor includes a first portion disposed between the input electrode and the output electrode and having a first crystallinity, and a second portion connected with the first portion, which overlaps the input electrode or the output electrode, and having a second crystallinity. The first crystallinity is higher than the second crystallinity.

Abstract: In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.

Abstract: An electronic device is presented, such as a thin film transistor. The device comprises a patterned electrically-conductive layer associated with an active element of the electronic device. The electrically-conductive layer has a pattern defining an array of spaced-apart electrically conductive regions. This technique allows for increasing an electric current through the device.

Abstract: A thin film transistor using oxide semiconductor for a channel, which may be controlled such that threshold voltage is positive and may be improved in reliability is provided. The thin film transistor includes a gate electrode, a pair of source/drain electrodes, an oxide semiconductor layer forming a channel and provided between the gate electrode and the pair of source/drain electrodes, a first insulating film as a gate insulating film provided on the oxide semiconductor layer on a side near the gate electrode, and a second insulating film provided on the oxide semiconductor layer on a side near the pair of source/drain electrodes. One or both of the first insulating film and the second insulating film includes an aluminum oxide having a film density of 2.70 g/cm3 or more and less than 2.79 g/cm3.

Abstract: A thin film transistor having a channel region including a nanoconductor layer. The nanoconductor layer can be a dispersed monolayer of nanotubes or nanowires formed of carbon. The thin film transistor generally includes a gate terminal insulated by a dielectric layer. The nanoconductor layer is placed on the dielectric layer and a layer of semiconductor material is developed over the nanoconductor layer to form the channel region of the thin film transistor. A drain terminal and a source terminal are then formed on the semiconductor layer. At low field effect levels, the operation of the thin film transistor is dominated by the semiconductor layer, which provides good leakage current performance. At high field effect levels, the charge transfer characteristics of the channel region are enhanced by the nanoconductor layer such that the effective mobility of the thin film transistor is enhanced.

Abstract: In a liquid crystal display (LCD) device having a thin film transistor (TFT), the TFT includes a source electrode, a drain electrode and a semiconductor layer. At least one of the source electrode and drain electrode includes a first layer including copper and a second layer forming an oxide layer and covering the first layer. The semiconductor layer has a substantially linear current-voltage relationship with said source electrode or drain electrode including said first and second layers, when a voltage is applied between the semiconductor layer and said source electrode or drain electrode.

Abstract: A field effect transistor for detecting an analyte having a thiol group includes a substrate, a source region and a drain region formed apart from each other on the substrate, the source region and the drain region being doped such that a polarity of the source and drain region is opposite to a polarity of the substrate, a channel region disposed between the source region and the drain region, an insulating layer formed of an electrically insulating material and disposed on the channel region, a gold layer disposed on the insulating layer and a reference electrode disposed apart from the gold layer.

Abstract: A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.

Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a channel and a gate electrode. The drain electrode is spaced from the source electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The channel includes a plurality of carbon nanotube wires, one end of each carbon nanotube wire is connected to the source electrode, and opposite end of each the carbon nanotube wire is connected to the drain electrode.

Abstract: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a method for manufacturing a highly-reliable semiconductor device, which is not destructed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element layer having a semiconductor element formed using a non-single crystal semiconductor layer, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element layer and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are firmly fixed together.

Abstract: A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

Abstract: A thin film transistor includes a gate electrode formed on a substrate, a semiconductor pattern overlapped with the gate electrode, a source electrode overlapped with a first end of the semiconductor pattern and a drain electrode overlapped with a second end of the semiconductor pattern and spaced apart from the source electrode. The semiconductor pattern includes an amorphous multi-elements compound including a II B element and a VI A element or including a III A element and a V A element and having an electron mobility no less than 1.0 cm2/Vs and an amorphous phase, wherein the VI A element excludes oxygen. Thus, a driving characteristic of the thin film transistor may be improved.

Abstract: Thin film transistors (TFTs) and methods of manufacturing the same. A TFT may include a floating channel on a surface of a channel and spaced apart from a source and a drain, and an insulating layer formed on the floating channel and designed to determine a distance between the floating channel and the source or the drain.

Abstract: The present invention discloses a suspended nanochannel transistor structure and a method for fabricating the same. The transistor structure of the present invention comprises a substrate; a side gate formed on the substrate; a dielectric layer covering the substrate and the side gate; a suspended nanochannel formed beside the lateral of the side gate with an air gap existing between the suspended nanochannel and the dielectric layer; a source and a drain formed over the dielectric layer and respectively arranged at two ends of the suspended nanochannel. The electrostatic force of the side gate attracts or repels the suspended nanochannel and thus fast varies the equivalent thickness of the side-gate dielectric layer. Thereby, the on/off state of the element is rapidly switched, or the initial voltage of the channel is altered.

Abstract: In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.

Abstract: A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a first conductivity type is separated by trench isolation insulator islands. Within an isolated region designated for castellated-gate MOSFETs there exists a semiconductor body consisting of an upper portion with an upper surface, and a lower portion with a lower surface. Also within the castellated-gate MOSFET region, there exists a source region, a drain region, and a channel-forming region disposed between the source and drain regions, and are all formed within the semiconductor substrate body.

Abstract: A semiconductor apparatus includes a substrate having at least one terminal, a thin semiconductor film including at least one semiconductor device, the thin semiconductor film being disposed and bonded on the substrate; and an individual interconnecting line formed as a thin conductive film extending from the semiconductor device in the thin semiconductor film to the terminal in the substrate, electrically connecting the semiconductor device to the terminal. Compared with conventional semiconductor apparatus, the invented apparatus is smaller and has a reduced material cost.

Abstract: By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.

Abstract: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled.

Abstract: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled.

Abstract: A method for manufacturing a substrate of a liquid crystal display device is disclosed. The method includes forming a conductive line structure with low resistance to improve the difficulty of the resistance matching. The method can effectively reduce the resistance of the conductive line of the LCD panel to increase the transmission rate of the driving signal. Hence, the increasing yield of products can reduce the cost of manufacturing, and can meet the requirement of the large-size and high-definition thin film transistor liquid crystal display device.

Abstract: A thin film transistor structure is provided. The thin film transistor structure includes a source and a drain. The corresponding opposite surfaces of the source and the drain are at least partially complementary and continuous convex-concave surfaces so that the charging ability of the thin film transistor would be increased due to an extending length of the continuous convex-concave surfaces.

Abstract: Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

Abstract: A protective structure for a semiconductor sensor integrated in a semiconductor substrate for use in a state that is in direct contact with a measuring medium has a semiconducting layer that is applied to the semiconductor substrate, a metal layer and an insulating layer. The insulating layer is disposed between the semiconducting layer and the metal layer and electrically insulates same.

Abstract: A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a first conductivity type is separated by trench isolation insulator islands. Within an isolated region designated for castellated-gate MOSFETs there exists a semiconductor body consisting of an upper portion with an upper surface, and a lower portion with a lower surface. Also within the castellated-gate MOSFET region, there exists a source region, a drain region, and a channel-forming region disposed between the source and drain regions, and are all formed within the semiconductor substrate body.

Abstract: A semiconductor device with a TFT includes a substrate, an island-shaped semiconductor film serving as an active layer of the TFT on or over the substrate, a pair of source/drain regions formed in the semiconductor film, and a channel region formed between the pair of source/drain regions in the semiconductor film. The pair of source/drain regions is thinner than the remainder of the semiconductor film other than the source/drain regions. The thickness difference between the pair of source/drain regions and the remainder of the semiconductor film is in a range from 10 angstrom (?) to 100 angstrom. The total process steps are reduced and the operation characteristic and reliability of the device are improved.

Abstract: Transistors, semiconductor memory cells having a transistor and methods of forming the same are provided, the transistors may include a semiconductor substrate having a first semiconductor region. A gate pattern may be disposed on the first semiconductor region. Spacer patterns may each be disposed on a sidewall of the gate pattern. Second semiconductor regions and a third semiconductor regions may be disposed in the semiconductor substrate. The second semiconductor regions may be disposed under the spacer patterns. The third semiconductor regions may be disposed adjacent to the second semiconductor regions. The first semiconductor region may have a higher impurity ion concentration than the second semiconductor regions.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.

Abstract: A thin film transistor according to an embodiment of the present invention includes: a semiconductor layer formed on a substrate and having a first diffusion region, a channel region, and a second diffusion region; a gate electrode opposite to the semiconductor layer across a gate insulating film formed on the semiconductor layer; and a connecting conductive film formed on the semiconductor layer opposite to the gate insulating film and extending from the first diffusion region up to a predetermined position in the channel region to electrically connect between the first diffusion region and the channel region. The transistor further includes a laying conductive layer formed on the semiconductor layer opposite to the gate insulating film and electrically connected with the second diffusion region.

Abstract: A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure.

Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a channel and a gate electrode. The drain electrode is spaced from the source electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The channel includes a plurality of carbon nanotube wires, one end of each carbon nanotube wire is connected to the source electrode, and opposite end of each the carbon nanotube wire is connected to the drain electrode.

Abstract: The present invention relates to a thin film transistor substrate and a liquid crystal display panel for use in a liquid crystal display apparatus, and aims to provide a thin film transistor substrate and a liquid crystal display panel with good display quality. The thin film transistor substrate has a first sub-pixel electrode 16 and second sub-pixel electrode 17 arranged on the opposite sides of the gate bus line 12, a first thin film transistor 20a that establishes direct electrical connection with the first sub-pixel electrode 16, and a second thin film transistor 20b capacitively coupled to the second sub-pixel electrode 17. Since capacitance is formed where conventionally a source electrode and pixel electrode are connected via a contact hole, excessively opaque wiring is not required, which ensures sufficient effective area and transmittance of a pixel.