Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

Abstract: High voltage devices capable of preventing leakage current caused by inversion layer. In the high voltage device, a substrate comprises an active area formed therein, a source region and a drain region formed in the substrate, and a gate structure is formed on the active area to define a channel region in the substrate between the drain region and the source region, wherein the active area has at least one side extending along a direction perpendicular to the channel direction of the channel region, such that the gate structure without completely covering the extension.

Abstract: A bottom-contacted top gate thin film transistor (TFT) with enhanced off current suppression is provided, along with an associated fabrication method. The method provided a substrate. Source and drain regions are formed overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and drain, with contact regions immediately overlying the source/drain (S/D) interface top surfaces. A first dielectric layer is conformally deposited. Then, a second dielectric layer is formed overlying the S/D interface top surfaces, with an opening exposing a portion of the first dielectric overlying the channel. A gate is formed overlying the second dielectric layer and the exposed portion of the first dielectric layer.

Abstract: The present invention relates to semiconductor devices that each comprises at least one field effect transistor (FET) containing an intrinsically stressed phase change material layer. The intrinsically stressed phase change material layer is arranged and constructed for creating stress in the channel region of the FET. Preferably, the intrinsically stressed phase change material layer is deposited over the channel region of the FET. For an n-channel FET, the intrinsically stressed phase change material layer preferably contains intrinsic compressive stress that is created by phase change, for example, from a polycrystalline phase to an amorphous phase. Alternatively, for a p-channel FET, the intrinsically stressed phase change material layer preferably contains intrinsic tensile stress that is created by phase change, for example, from an amorphous phase to a polycrystalline phase.

Abstract: A semiconductor device can include a channel including an oxide comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table.

Abstract: Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

Abstract: A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.

Abstract: A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.

Abstract: A p channel field effect transistor in which the sensitivity of an enzyme can be enhanced by immobilizing the enzyme directly on an FET channel surface (diamond surface), as well as a sensor including the same, is provided. A diamond surface (22) having mixed hydrogen terminals, oxygen terminals, and amino terminals is treated under the action of glutaraldehyde OHC(CH2)3CHO (30), so that the glutaraldehyde (30) is immobilized on the diamond surface (22) having mixed hydrogen terminals, oxygen terminals, and amino terminals. Subsequently, urease (29) is further applied thereto, so that the amino group (31) of the urease (29) is bonded to the glutaraldehyde (30). That is, the urease (29) can be immobilized on the diamond surface (22) having mixed hydrogen terminals, oxygen terminals, and amino terminals. When the urea concentration is increased from 10?6 M to 10?2 M, the threshold voltage shifts by about 0.1 V in the positive direction, and the sensitivity to urea concentration of 30 mV/decade is exhibited.

Abstract: A thin film transistor substrate includes a thin film transistor of a first conductivity type, a semiconductor layer having a channel region of the first conductivity type placed between the source/drain regions, a gate electrode formed to an opposite face to the semiconductor layer with an gate insulating film interposed therebetween, an opening in the gate electrode corresponding to both edges in a channel width direction of the channel region. In the channel region corresponding to the opening, a highly concentrated impurity region having a higher impurity concentration of the first conductivity type than the channel corresponding to the gate electrode is formed.

Abstract: An exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more compounds of the formula AxBxOx, wherein each A is selected from the group of Cu, Ag, Sb, each B is selected from the group of Cu, Ag, Sb, Zn, Cd, Ga, In, Ge, Sn, and Pb, each O is atomic oxygen, each x is independently a non-zero integer, and each of A and B are different.

Abstract: A curled transistor comprises a coiled semiconductor substrate having a plurality of concentrically curled layers. Source and drain regions are configured on a portion of the coiled semiconductor substrate, and a gate dielectric is positioned between the source and drain regions. A first set of metallic contacts electrically couple to the source region on the coiled semiconductor substrate and a second set of metallic contacts electrically couple to the drain region on the coiled semiconductor substrate.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: Methods of forming thin film devices with different electrical characteristics on a substrate comprising a driver circuit region and a pixel region. A first and a second polysilicon pattern layers are formed on the driving circuit region and the pixel region of the substrate, respectively. A first ion implantation is performed on the second polysilicon pattern layer using a masking layer covering the first polysilicon pattern layer as an implant mask, such that the first polysilicon pattern layer has an impurity concentration different from the second polysilicon pattern layer. After removal of the masking layer, a gate dielectric layer and a gate are successively formed on each of the first and second polysilicon pattern layers and a source/drain region is subsequently formed in each of the first and second polysilicon pattern layers to define a channel region therein.

Abstract: A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a source region formed on the insulating layer adjacent a first end of the conductive fin and a drain region formed on the insulating layer adjacent a second end of the conductive fin. The semiconductor device may further include a metal gate formed on the insulating layer adjacent the conductive fin in a channel region of the semiconductor device.

Abstract: A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lower end surface. A source region, a drain region, and a channel-forming region between the source and drain regions are all formed in the semiconductor substrate body. trench isolation insulator islands surround the source and drain regions as well as the channel-forming region. The channel-forming region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is also provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements.

Abstract: A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction and activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.

Abstract: The TFT electric characteristic is ready to be influenced by the channel region in the neighborhood of an interface between a semiconductor and a gate insulating film. The present invention provides TFTs reduced in electric characteristic deviations and a method for manufacturing the same. The invention forms a region or layer containing an inactive element, or rear gas element, in the channel region. As shown in FIG. 1, a rear gas element is contained at least in an upper layer of the channel region.

Abstract: A multi-channel type thin film transistor includes a gate electrode over a substrate extending along a first direction, a plurality of active layers parallel to and spaced apart from each other extending along a second direction crossing the first direction, and source and drain electrodes spaced apart from each other with respect to the gate electrode and extending along the first direction, wherein each of the plurality of active layers includes a channel region overlapped with the gate electrode, a source region, a drain region, and lightly doped drain (LDD) regions, one between the channel region and the source region and another one between the channel region and the drain region, wherein the LDD regions of the adjacent active layers have different lengths from each other.