Charging By Injection Of Carriers Through Conductive Insulator (e.g., Poole-frankel Conduction) (epo) Patents (Class 257/E29.303)
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Patent number: 8659952Abstract: A method of operating a non-volatile memory having a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is greater than the fourth voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region.Type: GrantFiled: July 8, 2008Date of Patent: February 25, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Ming-Chang Kuo, Chao-I Wu
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Patent number: 8492794Abstract: A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.Type: GrantFiled: March 15, 2011Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Jin Cai, Kevin K. Chan, Wilfried E. Haensch, Tak H. Ning
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Patent number: 8378341Abstract: A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.Type: GrantFiled: December 14, 2009Date of Patent: February 19, 2013Assignee: Renesas Electronics CorporationInventors: Yoshihiro Hayashi, Naoya Inoue, Kishou Kaneko
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Patent number: 7777302Abstract: A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method includes forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.Type: GrantFiled: June 29, 2007Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Joseph R. Greco, Richard S. Kontra, Emily Lanning
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Patent number: 7671401Abstract: A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).Type: GrantFiled: October 28, 2005Date of Patent: March 2, 2010Assignee: Mosys, Inc.Inventors: Gang-feng Fang, Dennis Sinitsky, Wingyu Leung
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Patent number: 7442977Abstract: This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.Type: GrantFiled: October 19, 2005Date of Patent: October 28, 2008Assignee: Micron Technology, Inc.Inventors: Cem Basceri, H. Montgomery Manning, Gurtej S. Sandhu, Kunal R. Parekh
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Patent number: 7411836Abstract: A method of operating a non-volatile memory comprising a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is bigger than the fourth voltage, the third voltage is bigger than the second voltage, and the second voltage is bigger than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region.Type: GrantFiled: October 11, 2005Date of Patent: August 12, 2008Assignee: MACRONIX International Co., Ltd.Inventors: Ming-Chang Kuo, Chao-I Wu
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Patent number: 7247924Abstract: A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.Type: GrantFiled: October 28, 2003Date of Patent: July 24, 2007Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Joseph R. Greco, Richard S. Kontra, Emily Lanning