Comprising Only Group Iv-vi Or Ii-iv-vi Chalcogenide Compound (e.g., Pbsnte) (epo) Patents (Class 257/E31.029)
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Patent number: 7560722Abstract: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.Type: GrantFiled: June 10, 2008Date of Patent: July 14, 2009Assignee: Axon Technologies CorporationInventor: Michael N Kozicki
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Patent number: 7527985Abstract: A method for manufacturing a memory device comprises patterning a dielectric layer and a conductive layer to align near the center of the top surface of a first contact drain plug and near the center of the top surface of a second contact drain plug. A first electrode is formed on the right sidewalls of the patterned dielectric layer and the conductive layer. A sidewall insulating member has a first sidewall surface and a second sidewall surface where the first sidewall surface of the sidewall insulating member is in contact with a sidewall of the first electrode. A second electrode is formed by depositing an electrode layer overlying the top surface of the sidewall insulating member and the second sidewall of the insulating member and isotropically etching the electrode layer to form the second electrode.Type: GrantFiled: October 24, 2006Date of Patent: May 5, 2009Assignee: Macronix International Co., Ltd.Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh
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Patent number: 7528401Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.Type: GrantFiled: January 16, 2004Date of Patent: May 5, 2009Assignee: Micron Technology, Inc.Inventor: Jiutao Li
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Patent number: 7511297Abstract: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.Type: GrantFiled: September 14, 2007Date of Patent: March 31, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Jang, Ki-Nam Kim, Soon-Moon Jung
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Patent number: 7494849Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.Type: GrantFiled: November 3, 2005Date of Patent: February 24, 2009Assignee: Cswitch Inc.Inventors: Antonietta Oliva, Louis Charles Kordus, II, Narbeh Derharcobian, Vei-Han Chan, Thomas E. Stewart, Jr.
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Patent number: 7491573Abstract: A memory device utilizing a phase change material as the storage medium, the phase change material based on antimony as the solvent in a solid solution.Type: GrantFiled: March 13, 2008Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Alejandro G Schrott, Chung H Lam, Simone Raoux, Chieh-Fang Chen
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Patent number: 7470922Abstract: A phase change material is formed over a dielectric material. An impurity is introduced into the dielectric to improve the adherence of said dielectric to said phase change material.Type: GrantFiled: November 21, 2007Date of Patent: December 30, 2008Assignee: Ovonyx, Inc.Inventors: Paola Besana, Tina Marangon, Amos Galbiati
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Patent number: 7456420Abstract: An electrode for a memory material of a phase change memory device is disclosed. The electrode includes a first layer adhered to the memory material, the first layer including a nitride (ANx), where A is one of titanium (Ti) and tungsten (W) and x greater than zero, but is less than 1.0, and a second layer adhered to the first layer, the second layer including a nitride (ANy), where y is greater than or equal to 1.0. The multiple layer electrode allows the first layer to better adhere to chalcogenide based memory material, such as GST, than for example, stoichiometric TiN or WN, which prevents delamination. A phase change memory device and method are also disclosed.Type: GrantFiled: March 7, 2006Date of Patent: November 25, 2008Assignee: International Business Machines CorporationInventors: Donna R. Cote, Ronald W. Mauthe, Keith Kwong Hon Wong
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Patent number: 7449711Abstract: A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.Type: GrantFiled: January 11, 2006Date of Patent: November 11, 2008Assignee: Elpida Memory, Inc.Inventors: Isamu Asano, Tsuyoshi Kawagoe, Yukio Fuji, Kiyoshi Nakai, Kazuhiko Kajigaya
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Publication number: 20080224180Abstract: A radiation detecting system includes at least a carrier collective electrode layer, a radiation-sensitive semiconductor layer, at least one charge transfer layer, and a voltage applying electrode formed on an insulating substrate and wherein at least one of the charge transfer layers includes chalcogenide compounds containing therein chalcogenide elements larger than the stoichiometric value by not smaller than 3% of the stoichiometric value in a composition thereof.Type: ApplicationFiled: March 14, 2008Publication date: September 18, 2008Applicant: FUJIFILM CORPORATIONInventor: Fumito NARIYUKI
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Patent number: 7405420Abstract: Chalcogenide-based nanowire memories are implemented using a variety of methods and devices. According to an example embodiment of the present invention, a method of manufacturing a memory circuit is implemented. The method includes depositing nanoparticles at locations on a substrate. Chalcogenide-based nanowires are created at the locations on the substrate using a vapor-liquid-solid technique. Insulating material is deposited between the chalcogenide-based nanowires. Lines are created to connect at least some of the chalcogenide-based nanowires.Type: GrantFiled: September 29, 2006Date of Patent: July 29, 2008Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: H. S. Philip Wong, Stefan Meister, SangBum Kim, Hailin Peng, Yuan Zhang, Yi Cui
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Patent number: 7399655Abstract: A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element.Type: GrantFiled: August 4, 2003Date of Patent: July 15, 2008Assignee: Ovonyx, Inc.Inventor: Charles H. Dennison
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Patent number: 7394088Abstract: A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed contact surfaces. A phase change memory element is encased within the dielectric material layer, including a phase-change layer positioned between and in electrical contact with the electrodes, wherein the lateral extent of the phase change layer is less than the lateral extent of the electrodes. An isolation material is positioned between the phase change layer and the dielectric layer, wherein the thermal conductivity of the isolation material is lower than the thermal conductivity of the dielectric material.Type: GrantFiled: January 24, 2006Date of Patent: July 1, 2008Assignee: Macronix International Co., Ltd.Inventor: Hsiang-Lan Lung
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Patent number: 7393798Abstract: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.Type: GrantFiled: June 14, 2006Date of Patent: July 1, 2008Assignee: Micron Technology, Inc.Inventor: Kristy A. Campbell
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Patent number: 7391050Abstract: A memory device is described an active material configured to be placed in a more or less conductive state by means of appropriate switching processes. The active material is positioned between a material having low thermal conductivity or material layers having low thermal conductivity.Type: GrantFiled: July 22, 2005Date of Patent: June 24, 2008Assignee: Infineon Technologies AGInventor: Thomas Happ
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Patent number: 7385219Abstract: A microelectronic programmable structure suitable for storing information, and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.Type: GrantFiled: May 4, 2007Date of Patent: June 10, 2008Assignee: A{umlaut over (x)}on Technologies CorporationInventors: Michael N. Kozicki, Muralikrishnan Balakrishnan, Maria Mitkova
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Publication number: 20080124831Abstract: Methods and devices are provided for high-throughput printing of semiconductor precursor layer from microflake particles. In one embodiment, the method comprises of transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be microflakes that have a high aspect ratio. The resulting dense film formed from microflakes are particularly useful in forming photovoltaic devices.Type: ApplicationFiled: June 19, 2007Publication date: May 29, 2008Inventors: Matthew R. Robinson, Jeroen K. J. Van Duren, Craig Leidholm, Brian M. Sager
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Patent number: 7365354Abstract: A programmable resistance memory element using a conductive sidewall layer as the bottom electrode. The programmable resistance memory material deposited over the top edge of the bottom electrode, in a slot-like opening of a dielectric material. A method of making the opening.Type: GrantFiled: December 2, 2002Date of Patent: April 29, 2008Assignee: Ovonyx, Inc.Inventor: Jon Maimon
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Patent number: 7365411Abstract: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichiometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.Type: GrantFiled: August 12, 2004Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventor: Kristy A. Campbell
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Patent number: 7361929Abstract: A field-effect transistor includes source, drain, and gate electrodes; a crystalline or polycrystalline layer of inorganic semiconductor; and a dielectric layer. The layer of inorganic semiconductor has an active channel portion physically extending from the source electrode to the drain electrode. The inorganic semiconductor has a stack of 2-dimensional layers in which intra-layer bonding forces are covalent and/or ionic. Adjacent ones of the layers are bonded together by forces substantially weaker than covalent and ionic bonding forces. The dielectric layer is interposed between the gate electrode and the layer of inorganic semiconductor material. The gate electrode is configured to control a conductivity of an active channel part of the layer of inorganic semiconductor.Type: GrantFiled: April 4, 2007Date of Patent: April 22, 2008Assignees: Lucent Technologies Inc.Inventors: Ernst Bucher, Michael E. Gershenson, Christian Kloc, Vitaly Podzorov
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Patent number: 7361925Abstract: The present invention includes a memory cell device and method that includes a memory cell, a first electrode, a second electrode, phase-change material and an isolation material. The phase-change material is coupled adjacent the first electrode. The second electrode is coupled adjacent the phase-change material. The isolation material adjacent the phase-change material thermally isolates the phase-change material.Type: GrantFiled: February 10, 2005Date of Patent: April 22, 2008Assignee: Infineon Technologies AGInventors: Thomas Happ, Shoaib Zaidi
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Patent number: 7354793Abstract: A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method.Type: GrantFiled: August 12, 2004Date of Patent: April 8, 2008Assignee: Micron Technology, Inc.Inventor: Kristy A. Campbell
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Patent number: 7348209Abstract: Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least one chalcogenide glass layer. The invention also relates to methods of forming such a memory device.Type: GrantFiled: August 29, 2006Date of Patent: March 25, 2008Assignee: Micron Technology, Inc.Inventor: Kristy A. Campbell
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Patent number: 7348590Abstract: A memory cell device includes a first electrode, a heater adjacent the first electrode, phase-change material adjacent the heater, a second electrode adjacent the phase-change material, and isolation material adjacent the phase-change material for thermally isolating the phase-change material.Type: GrantFiled: April 8, 2005Date of Patent: March 25, 2008Assignee: Infineon Technologies AGInventor: Thomas Happ
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Patent number: 7338857Abstract: A phase change material is formed over a dielectric material. An impurity is introduced into the dielectric to improve the adherence of said dielectric to said phase change material.Type: GrantFiled: October 14, 2004Date of Patent: March 4, 2008Assignee: Ovonyx, Inc.Inventors: Paola Besana, Tina Marangon, Amos Galbiati
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Patent number: 7338851Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.Type: GrantFiled: July 14, 2004Date of Patent: March 4, 2008Assignee: Micron Technology, Inc.Inventor: Kristy A. Campbell
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Patent number: 7329579Abstract: A phase changeable memory cell is disclosed. According to embodiments of the invention, a phase changeable memory cell is formed that has a reduced contact area with one of the electrodes, compared to previously known phase changeable memory cells. This contact area can be a sidewall of one of the electrodes, or a perimeter edge of a contact opening through the electrode. Thus, when the thickness of the electrode is relatively thin, the contact area between the electrode and the phase changeable material pattern is relatively very small. As a result, it is possible to reduce power consumption of the phase changeable memory device and to form reliable and compact phase changeable memory cells.Type: GrantFiled: June 30, 2005Date of Patent: February 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Yongho Ha, Jihye Yi, Hyunjo Kim
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Patent number: 7323734Abstract: A phase changeable memory cell is disclosed. According to embodiments of the invention, a phase changeable memory cell is formed that has a reduced contact area with one of the electrodes, compared to previously known phase changeable memory cells. This contact area can be a sidewall of one of the electrodes, or a perimeter edge of a contact opening through the electrode. Thus, when the thickness of the electrode is relatively thin, the contact area between the electrode and the phase changeable material pattern is relatively very small. As a result, it is possible to reduce power consumption of the phase changeable memory device and to form reliable and compact phase changeable memory cells.Type: GrantFiled: February 25, 2003Date of Patent: January 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Yongho Ha, Jihye Yi, Hyunjo Kim
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Patent number: 7323356Abstract: Disclosed is a method of producing an LnCuOX single-crystal thin film (wherein Ln is at least one selected from the group consisting of lanthanide elements and yttrium, and X is at least one selected from the group consisting of S, Se and Te), which comprises the steps of growing a base thin film on a single-crystal substrate, depositing an amorphous or polycrystalline LnCuOX thin film on the base thin film to form a laminated film, and then annealing the laminated film at a high temperature of 500° C. or more.Type: GrantFiled: February 19, 2003Date of Patent: January 29, 2008Assignee: Japan Science and Technology AgencyInventors: Hideo Hosono, Masahiro Hirano, Hiromichi Ota, Masahiro Orita, Hidenori Hiramatsu, Kazushige Ueda
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Patent number: 7314776Abstract: Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting the top surface of the phase change material.Type: GrantFiled: December 13, 2002Date of Patent: January 1, 2008Assignee: Ovonyx, Inc.Inventors: Brian G. Johnson, Charles H. Dennison
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Patent number: 7307908Abstract: A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory refresh operations in a conventional volatile memory device, such as a DRAM. A processor can perform periodic memory refresh operations by executing a set of memory refresh instructions implemented in software, rather than in hardware. Accordingly, the memory device can advantageously be simplified, because the need for memory refresh circuitry and for a unique refresh control signal are advantageously eliminated. Moreover, the processor executing the memory refresh instructions can typically perform more sophisticated algorithms, as compared to memory refresh circuitry implemented in hardware, for determining when to perform a memory refresh operation.Type: GrantFiled: November 28, 2005Date of Patent: December 11, 2007Assignee: Micron Technology, Inc.Inventor: Terry L. Gilton
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Patent number: 7303939Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.Type: GrantFiled: October 9, 2003Date of Patent: December 4, 2007Assignee: Micron Technology, Inc.Inventor: Rita J. Klein
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Patent number: 7282387Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.Type: GrantFiled: November 2, 2005Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventor: Rita J. Klein
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Patent number: 7282783Abstract: Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least one chalcogenide glass layer. The invention also relates to methods of forming such a memory device.Type: GrantFiled: February 1, 2007Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventor: Kristy A. Campbell
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Patent number: 7259023Abstract: A phase change memory may be formed to have a dimension that is sub-lithographic in one embodiment by forming a surface feature over the phase change material, and coating the surface feature with a mask of sub-lithographic dimensions. The horizontal portions of the mask and the surface feature may then be removed and the remaining portions of the mask may be used to define a dimension of said phase change material. Another dimension of the phase change material may be defined using an upper electrode extending over said phase change material as a mask to etch the phase change material.Type: GrantFiled: September 10, 2004Date of Patent: August 21, 2007Assignee: Intel CorporationInventors: Charles C. Kuo, Ilya Karpov, Yudong Kim, Greg Atwood
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Publication number: 20070158631Abstract: A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is between the first and second electrodes. A second layer including a metal-chalcogenide material is also between the first and second electrodes and is one of a phase change material and a conductive material. An insulating layer is between the first and second layers. There is at least one opening in the insulating layer providing contact between the first and second layers.Type: ApplicationFiled: December 16, 2005Publication date: July 12, 2007Inventors: Jon Daley, Kristy Campbell
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Patent number: 7232703Abstract: A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34). This non-volatile memory achieves high integration at low cost.Type: GrantFiled: November 4, 2004Date of Patent: June 19, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoyuki Morita, Noboru Yamada, Akihito Miyamoto, Takashi Ohtsuka, Hideyuki Tanaka
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Patent number: 7227171Abstract: A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction transverse to said first direction; the first and second thin portions being in direct electrical contact and defining a contact area having a sublithographic extension. The thin portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer; the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic opening that is used to etch a mold opening in a mold layer and filling the mold opening.Type: GrantFiled: December 5, 2002Date of Patent: June 5, 2007Assignees: STMicroelectronics S.r.l., Ovonyx, Inc.Inventors: Roberto Bez, Fabio Pellizzer, Caterina Riva, Romina Zonca
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Patent number: 7214958Abstract: A memory cell device includes a first electrode, phase-change material adjacent the first electrode, a second electrode adjacent the phase-change material, a diffusion barrier adjacent the phase-change material, and isolation material adjacent the diffusion barrier for thermally isolating the phase-change material. The diffusion barrier prevents diffusion of the phase-change material into the isolation material.Type: GrantFiled: April 8, 2005Date of Patent: May 8, 2007Assignee: Infineon Technologies AGInventor: Thomas Happ
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Patent number: 7202493Abstract: A chalcogenide phase change memory cell has a substrate with a conductor line. The conductor line has a contact end. An insulating layer is located over the substrate and conductor line. An aperture is located in the insulating layer. The aperture extends to the substrate. A memory material is conformally located within the aperture. The memory material is in electrical contact with the contact end. A conductive layer is located over the memory material in the aperture.Type: GrantFiled: November 30, 2004Date of Patent: April 10, 2007Assignee: Macronix International Co., Inc.Inventor: Hsiang-Lan Lung
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Patent number: 7190048Abstract: Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least one chalcogenide glass layer. The invention also relates to methods of forming such a memory device.Type: GrantFiled: July 19, 2004Date of Patent: March 13, 2007Assignee: Micron Technology, Inc.Inventor: Kristy A. Campbell
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Patent number: 7186999Abstract: An error reduction circuit for use in arrays of chalcogenide memory and computing devices. The error reduction circuit reduces the error associated with the output response of chalcogenide devices. In a preferred embodiment, the output response is resistance and the error reduction circuit reduces errors or fluctuations in the resistance. The error reduction circuit includes a network of chalcogenide devices, each of which is nominally equivalent and each of which is programmed into the same state having the same nominal resistance. The inclusion of multiple devices in the network of the instant error reduction circuit provides for a reduction in the contributions of both dynamic fluctuations and manufacturing fluctuations to the error in the output response.Type: GrantFiled: February 24, 2005Date of Patent: March 6, 2007Assignee: Energy Conversion Devices, Inc.Inventors: Stanford R. Ovshinsky, Morrel H. Cohen
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Patent number: 7135727Abstract: Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the contact structure dimensions employ conventional semiconductor deposit and etch processing steps that are capable of creating readily reproducible results.Type: GrantFiled: November 10, 2004Date of Patent: November 14, 2006Assignee: Macronix International Co., Ltd.Inventors: Ming Hsiu Lee, Ruichen Liu
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Patent number: 7129560Abstract: A memory cell includes a storage medium having a programmable thermal impedance, and a heater in thermal communication with the storage medium for programming the thermal impedance. In another aspect, a memory cell includes a storage medium having a programmable electrical impedance, and a heater in thermal communication with the storage medium for programming the electrical impedance. In a third aspect, a memory device includes a plurality of the memory cells in accordance with the first and/or second aspect of the present invention.Type: GrantFiled: March 31, 2003Date of Patent: October 31, 2006Assignee: International Business Machines CorporationInventors: Hendrik F. Hamann, Martin Patrick O'Boyle, H. Kumar Wickramasinghe
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Patent number: 7126152Abstract: A storage device includes a first electrode, a second electrode facing the first electrode, an inter-electrode material layer provided between the first electrode and the second electrode, and a voltage application unit applying a predetermined voltage to the first and the second electrodes. Furthermore, an oxidation-reduction active material changeable into an electrode reaction inhibition layer by applying voltages to the first and the second electrodes is contained in a region that is covered by an electric field, the electric field being generated when the voltage is applied, and the electrode reaction inhibition layer is either formed along an interface region between the second electrode and the inter-electrode material layer, or changes an area thereof, or disappears depending on an application condition of the voltage to the first and the second.Type: GrantFiled: November 29, 2004Date of Patent: October 24, 2006Assignee: Sony CorporationInventors: Minoru Ishida, Katsuhisa Aratani, Akira Kouchiyama, Tomohito Tsushima
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Patent number: 7112836Abstract: A horizontal electrode having a small cross-section makes electrical contact with a chalcogenide memory element. The dimensions of the cross-section are controlled by conventional deposit/etch semiconductor processing steps. The resulting memory element can be driven by a CMOS steering element.Type: GrantFiled: March 17, 2004Date of Patent: September 26, 2006Assignee: Macronix International Co., Ltd.Inventor: Yi Chou Chen
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Patent number: 7109056Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.Type: GrantFiled: September 20, 2001Date of Patent: September 19, 2006Assignee: Micron Technology, Inc.Inventor: Rita J. Klein