Abstract: An integrated image sensor includes a pixel array; an analog circuit configured to control the pixel array and read out image data based on an output signal of the pixel array; a processor configured to generate a control signal for controlling the analog circuit based on the image data and to feed back the control signal to the analog circuit; and a memory storing the image data.

Abstract: A solid state imaging device that includes a substrate having oppositely facing first and second surfaces and a photoelectric conversion unit layer having a light incident side facing away from the substrate. The substrate includes a first photoelectric conversion unit and a second photoelectric conversion and the photoelectric conversion layer includes a third photoelectric conversion unit.

Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.

Abstract: Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region.

Abstract: An organic optoelectronic component includes a substrate embodied in a light-transmissive fashion, an organic light-emitting element having an organic light-emitting layer between two electrodes, and an organic light-detecting element having an organic light-detecting layer. The organic light-emitting element and the organic light-detecting element are arranged on the substrate. Part of the light generated by the organic light-emitting element during operation enters into the substrate, emerges from the substrate and is detected by the organic light-detecting element.

Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.

Abstract: A quad photoreceiver includes a low capacitance quad InGaAs p-i-n photodiode structure formed on an InP (100) substrate. The photodiode includes a substrate providing a buffer layer having a metal contact on its bottom portion serving as a common cathode for receiving a bias voltage, and successive layers deposited on its top portion, the first layer being drift layer, the second being an absorption layer, the third being a cap layer divided into four quarter pie shaped sections spaced apart, with metal contacts being deposited on outermost top portions of each section to provide output terminals, the top portions being active regions for detecting light. Four transimpedance amplifiers have input terminals electrically connected to individual output terminals of each p-i-n photodiode.

Abstract: The photovoltaic cell comprises, deposited on a transparent substrate in the following order: a first conductive oxide layer; a first p-i-n junction; a second p-i-n junction; a second conductive oxide layer, wherein said first conductive oxide layer is substantially transparent and comprises a low-pressure chemical vapor deposited ZnO layer; and said second conductive oxide layer comprises an at least partially transparent low-pressure chemical vapor deposited ZnO layer; and wherein said first p-i-n junction comprises in the following order: a layer of p-doped a-Si:H deposited using PECVD and having at its end region facing toward said second p-i-n junction a higher band gap than at its end region facing toward said first conductive oxide layer; a buffer layer of a-Si:H deposited using PECVD without voluntary addition of a dopant; a layer of substantially intrinsic a-Si:H deposited using PECVD; a first layer of n-doped a-Si:H deposited using PECVD; and a layer of n-doped ?c-Si:H deposited using PECVD; and whe

Abstract: To provide a stacked photoelectric conversion device capable of inhibiting extreme decrease of the output in the morning and evening. A stacked photoelectric conversion device of the present invention comprises a first photoelectric conversion layer, a second photoelectric conversion layer and a third photoelectric conversion layer stacked in this order from a light entrance side, each photoelectric conversion layer having a p-i-n junction and formed of a silicon based semiconductor, wherein a short-circuit photocurrent of the first photoelectric conversion layer is larger than a short-circuit photocurrent of the second photoelectric conversion layer or a short-circuit photocurrent of the third photoelectric conversion layer under a condition of light source: xenon lamp, irradiance: 100 mW/cm2, AM: 1.5, and temperature: 25° C.

Abstract: Provided are a solar cell and a method for manufacturing the same. A solar cell according to an exemplary embodiment of the present invention includes: a substrate; a first electrode disposed on the substrate and including a first groove; a first semiconductor layer disposed on the first electrode; a second semiconductor layer disposed on the first semiconductor layer; and a second electrode disposed on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer have a second groove extending therethrough, the second electrode extends into the second groove, and a third groove is formed in the second electrode and positioned within the second groove.

Abstract: To provide a photoelectric conversion device with improved photoelectric conversion characteristics and cost competitiveness. A photoelectric conversion device including a semiconductor junction has a semiconductor layer in which a needle-like crystal is made to grow over an impurity semiconductor layer. The impurity semiconductor layer is formed of a microcrystalline semiconductor and includes an impurity imparting one conductivity type. An amorphous semiconductor layer is deposited on a microcrystalline semiconductor layer by setting the flow rate of a dilution gas (typically silane) to 1 time to 6 times the flow rate of a semiconductor source gas (typically hydrogen) at the time of deposition. Thus, a crystal with a three-dimensional shape tapered in a direction of the deposition of a film, i.e., in a direction from the microcrystalline semiconductor layer to the amorphous semiconductor layer is made to grow.

Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.

Abstract: Provided is an image sensor and a method for manufacturing the same. The image sensor includes a substrate on which a circuitry including a first lower metal line and a second lower metal line is formed. A lower electrode is formed on the first lower metal line. A separation metal pattern surrounds the lower electrode and connected to the second lower metal line. An intrinsic layer is formed on the lower electrode. A second conductive type conduction layer is formed on the intrinsic layer. An upper electrode is formed on the second conductive type conductive layer. A bias can be applied to the second lower metal line such that the separation metal pattern can provide a Schottky Barrier, directing electrons to the lower electrode and inhibiting crosstalk between pixels.

Abstract: A solid-state imaging device of the present invention includes: a semiconductor substrate including a first region of a first conductivity type; a signal accumulation region of a second conductivity type formed within the first region; a gate electrode formed above the first region; a drain region of a second conductivity type formed on the first region; an isolation region having insulation properties, which is formed to surround a region where the signal accumulation region, the gate electrode, and the drain region are formed; a first conductivity type dopant doping region formed in contact with a side face and a bottom face of the isolation region, the first conductivity type dopant doping region having a higher dopant concentration than the first region; and a second conductivity type dopant doping region formed in the first region, under an end of the gate electrode in a gate width direction.

Abstract: To provide a stacked photoelectric conversion device capable of inhibiting extreme decrease of the output in the morning and evening. A stacked photoelectric conversion device of the present invention comprises a first photoelectric conversion layer, a second photoelectric conversion layer and a third photoelectric conversion layer stacked in this order from a light entrance side, each photoelectric conversion layer having a p-i-n junction and formed of a silicon based semiconductor, wherein a short-circuit photocurrent of the first photoelectric conversion layer is larger than a short-circuit photocurrent of the second photoelectric conversion layer or a short-circuit photocurrent of the third photoelectric conversion layer under a condition of light source: xenon lamp, irradiance: 100 mW/cm2, AM: 1.5, and temperature: 25° C.

Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.

Abstract: A photodiode that can separately detect the intensities of the three wavelength ranges of ultraviolet light of 400 nm or below includes an insulating layer; and a plurality of silicon semiconductor layers having different thicknesses formed on the insulating layer, wherein each of the plurality of silicon semiconductor layers has a low-concentration diffusion layer formed by diffusing one of a P-type impurity or an N-type impurity therein with a low concentration; a P-type high-concentration diffusion layer formed by diffusing a P-type impurity therein with a high concentration; and an N-type high-concentration diffusion layer formed by diffusing an N-type impurity therein with a high concentration, and wherein the P-type high-concentration diffusion layer and the N-type high-concentration diffusion layer formed in a respective one of the plurality of silicon semiconductor layers are arranged to face each other with the low-concentration diffusion layer interposed there between.

Abstract: An image sensor may include a device isolating layer and a photodiode on a substrate; a first dielectric layer on the photodiode; a first micro lens on the first dielectric layer; a second dielectric layer on the first micro lens; a color filter on the second dielectric layer; and a second micro lens on the color filter.

Abstract: Provided is an image sensor and a method for manufacturing the same. The image sensor includes a substrate on which a circuitry including a first lower metal line and a second lower metal line is formed. A lower electrode is formed on the first lower metal line. A separation metal pattern surrounds the lower electrode and connected to the second lower metal line. An intrinsic layer is formed on the lower electrode. A second conductive type conduction layer is formed on the intrinsic layer. An upper electrode is formed on the second conductive type conduction layer. A bias can be applied to the second lower metal line such that the separation metal pattern can provide a Schottky Barrier, directing electrons to the lower electrode and inhibiting crosstalk between pixels.

Abstract: A microelectromechanical system switch may include a relatively stiff cantilevered beam coupled, on its free end, to a more compliant or flexible extension. A contact may be positioned at the free end of the cantilevered beam. The extension reduces the actuation voltage that is needed and compensates for the relative stiffness of the cantilevered beam in closing the switch. In opening the switch, the stiffness of the cantilevered beam may advantageously enable quicker operation which may be desirable in higher frequency situations.

Abstract: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.

Abstract: A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction. Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.

Abstract: A scanning head for an optical position-measuring system includes a receiver grating, formed of photosensitive areas, for the scanning of locally intensity-modulated light of differing wavelengths. The receiver grating is formed from a semiconductor layer stack of a doped p-layer, an intrinsic i-layer and a doped n-layer. The individual photosensitive areas have a first doped layer and at least a part of the intrinsic layer in common and are electrically separated from one another by interruptions in the second doped layer.

Abstract: Shorting bars are provided for electrostatic discharge protection as a portion of trace deposition in a photodiode array. During normal processing for etching of the metal layers, the shorting bars are removed without additional processing requirements. Additional shorting elements are provided by employing FET silicon layers having traces in contact with the array traces to provide extended ESD protection until removal of those shorting elements during normal processing for opening vias for photodiode bottom contact.

Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.