Electrode (epo) Patents (Class 257/E31.124)
-
Patent number: 11901390Abstract: A semiconductor device includes a substrate, a dielectric layer, a plurality of dielectric patterns and a conductive pad. The substrate includes a first surface and a second surface opposite to the first surface. The dielectric layer is disposed at the first surface of the substrate, and the substrate is disposed between the dielectric layer and the second surface of the substrate. The dielectric patterns are disposed on the dielectric layer and between the first surface and the second surface of the substrate. The conductive pad is inserted between the plurality of dielectric patterns and extended into the dielectric layer.Type: GrantFiled: November 15, 2021Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
-
Patent number: 11855116Abstract: A first conductive portion includes a first pad surrounded by a first insulator film in a plane perpendicular to a first direction, and a first via connected to the first pad so that the first via is positioned between the first pad and a first semiconductor layer in the first direction. A second conductive portion includes a second pad surrounded by a second insulator film in a plane perpendicular to the first direction, and a second via connected to the second pad so that the second via is positioned between the second pad and a second semiconductor layer in the first direction. The first and the second conductive portions are different in dimension.Type: GrantFiled: November 5, 2021Date of Patent: December 26, 2023Assignee: Canon Kabushiki KaishaInventors: Tsutomu Tange, Takumi Ogino, Hiroaki Kobayashi
-
Patent number: 11832461Abstract: A photoelectric conversion module includes photoelectric conversion elements electrically coupled. The photoelectric conversion elements each sequentially include first electrode, photoelectric conversion layer, and second electrode. The photoelectric conversion module includes first photoelectric conversion element, second photoelectric conversion element, coupling portion to couple the first and second photoelectric conversion elements in series, first partition portion, and second partition portion. The first electrode or the second electrode forming the first photoelectric conversion element includes a contact region in contact with the coupling portion. A value of X/(Y?X) is 0.3 or greater, where X denotes a length of the contact region and Y denotes a predetermined length in the coupling direction around the contact region.Type: GrantFiled: November 23, 2021Date of Patent: November 28, 2023Assignee: RICOH COMPANY, LTD.Inventors: Takaya Ito, Ryota Arai, Tomoya Hirano
-
Patent number: 11810994Abstract: The invention relates to an infrared-transmitting high-sensitivity visible light detector and its preparation method. The detector is composed of passivation layer (14), upper electrode (13), heterojunction (15), lower electrode (3), and intrinsic monocrystalline silicon substrate (2). The upper electrode (13) is the material that is electrically conductive and transparent to visible light and infrared light. The heterojunction (15) is divided into heterojunction upper layer (5) and heterojunction lower layer (4), wherein the upper heterojunction layer (5) is a nano film sensitive to visible light and capable of transmitting infrared ray, and the lower heterojunction layer (4) is intrinsic monocrystalline silicon.Type: GrantFiled: November 23, 2019Date of Patent: November 7, 2023Inventors: Huan Liu, Yan An, Weiguo Liu, Jun Han, Changlong Cai, Minyu Bai, Zhuoman Wang
-
Patent number: 11804564Abstract: Provided is a solar cell, including: an N-type semiconductor substrate having a front surface and a rear surface opposite to the front surface; a boron diffusion layer arranged on the front surface of the N-type semiconductor substrate, a first passivation layer is provided on a surface of the boron diffusion layer, and a first electrode is provided passing through the first passivation layer to form an electrical connection with the N-type semiconductor substrate; and a phosphorus-doped polysilicon layer arranged on the rear surface of the N-type semiconductor substrate. A silicon oxide layer containing nitrogen and phosphorus is provided between the rear surface of the N-type semiconductor substrate and the phosphorus-doped polysilicon layer, a second passivation layer is provided on a surface of the phosphorus-doped polysilicon layer, and a second electrode is provided passing through the second passivation layer to form an electrical connection with the phosphorus-doped polysilicon layer.Type: GrantFiled: May 5, 2022Date of Patent: October 31, 2023Assignee: Jinko Solar Co., Ltd.Inventors: Jiahua Qu, Jingsheng Jin, Linan Zhang
-
Patent number: 11791354Abstract: Disclosed is a CMOS image sensor with global shutters and a method for fabricating the CMOS image sensor. In one embodiment, a semiconductor device, includes: a light-sensing region; a charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact.Type: GrantFiled: May 8, 2020Date of Patent: October 17, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Yu Tseng, Ming-Hsien Chen
-
Patent number: 11784264Abstract: A method for fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a first metal layer on the dielectric region. The method can also include forming a second metal layer on the first metal layer and locally heating a particular region of the second metal layer, where heating includes forming a metal bond between the first and second metal layer and forming a contact between the first metal layer and the solar cell structure. The method can include forming an adhesive layer on the first metal layer and forming a second metal layer on the adhesive layer, where the adhesive layer mechanically couples the second metal layer to the first metal layer and allows for an electrical connection between the second metal layer to the first metal layer.Type: GrantFiled: July 29, 2021Date of Patent: October 10, 2023Assignee: Maxeon Solar Pte. Ltd.Inventors: Matthieu Moors, Taeseok Kim
-
Patent number: 11767219Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer, wherein the formation of the plurality of scribe lines includes removing portions of the second wafer from the second surface towards the first surface to form a third surface between the first surface and the second surface, and the plurality of scribe lines protrudes from the third surface of the second wafer.Type: GrantFiled: July 17, 2020Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Cheng Shen, Yi-Hsien Chang, Yi-Heng Tsai, Chun-Ren Cheng
-
Patent number: 11769810Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer, a gate electrode, and the gate electrode, a first electrode electrically connected to the oxide semiconductor layer, a second electrode electrically connected to the oxide semiconductor layer, a first conductive layer provided at at least one position between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode, the first conductive layer containing a first metal element, a first element different from the first metal element, and one of oxygen (O) or nitrogen (N), and a second conductive layer between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing oxygen (O) and a second element different from both of the first metal element and the first element. The gate electrode is between the first electrode and the second electrode in the first direction.Type: GrantFiled: March 11, 2021Date of Patent: September 26, 2023Assignee: Kioxia CorporationInventors: Junji Kataoka, Tomomasa Ueda, Shushu Zheng, Nobuyoshi Saito, Keiji Ikeda
-
Patent number: 11682522Abstract: Provided is a conductive paste composition for an external electrode of a multilayer ceramic capacitor that includes a conductive base material, an organic solvent, a binder resin, and a dispersing agent. The conductive base material includes a flake-shaped conductive powder, a spherical conductive powder, and first and second glass frits. The flake-shaped conductive powder has a larger size D50 than the spherical conductive powder. The first glass frit includes SiO2, SrCO3, BaCO3, Li2SO4, K2SO4, V2O5, ZnO, Al2O3, and Y2O3, and the second glass frit includes SiO2, SrCO3, BaCO3, CaF, ZnO, Al2O3, Y2O3, and L2O3.Type: GrantFiled: August 20, 2021Date of Patent: June 20, 2023Assignee: SAMHWA CAPACITOR CO., LTD.Inventors: Young Joo Oh, Jung Rag Yoon, In Hee Cho
-
Patent number: 11658251Abstract: An object of the present invention is to provide, at a low cost, a system and a method for manufacturing a solar cell having high conversion efficiency. A solar cell according to the present invention is characterized by including a passivation film that protects a semiconductor substrate, a first finger electrode connected to the semiconductor substrate on a main surface of the semiconductor substrate, a first bus bar electrode that intersects the first finger electrode, and an intermediate layer provided in an intersecting position of the first finger electrode and the first bus bar electrode. The solar cell is characterized in that the first finger electrode and the first bus bar electrode are electrically connected to each other via the intermediate layer.Type: GrantFiled: July 14, 2022Date of Patent: May 23, 2023Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Ryo Mitta, Takenori Watabe, Hiroyuki Ohtsuka
-
Patent number: 11613803Abstract: Use of a laser-activatable component in a composition and/or use of a composition that includes the laser-activatable component, during laser transfer printing, characterized in that the laser-activatable component is activated by laser irradiation during use in such a way that the viscosity and/or the elasticity and/or the tack of the composition increase(s) due to an increase in temperature of the composition, wherein the laser-activatable component is a polymer made up of the groups comprising polyethylene glycol, polyvinylpyrrolidone, polyvinyl acetate, polyvinyl alcohol, polyacrylate, polyester, or copolymers of these polymers or blends.Type: GrantFiled: November 9, 2020Date of Patent: March 28, 2023Assignee: LPKF Laser & Electronics AGInventors: Robin Alexander Krüger, Malte Schulz-Ruhtenberg, Marc Hüske
-
Patent number: 11508863Abstract: A a semiconductor component (1a, 1b) having a front side and an opposite rear side and also side surfaces, and also at least one emitter (2a, 2b) and at least one base (3a, 3b), wherein a pn junction (4a, 4b) is formed between emitter (2a, 2b) and base (3a, 3b) and the emitter (2a, 2b) extends parallel to the front and/or rear side. At least one side surface is a passivated separating surface (T), at which a separating surface passivation layer (6a, 6b) is arranged, which has stationary charges having a surface charge density at the separating surface (T) with a magnitude of greater than or equal to 1012 cm-2. A method for singulating a semiconductor component (1a, 1b) having a pn junction is also provided.Type: GrantFiled: September 24, 2019Date of Patent: November 22, 2022Assignee: Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V.Inventors: Elmar Lohmüller, Ralf Preu, Puzant Baliozian, Tobias Fellmeth, Nico Wöhrle, Pierre Saint-Cast, Florian Clement, Andreas Brand
-
Patent number: 11424378Abstract: A photovoltaic device is provided that comprises a photovoltaic active zone being formed of a stack of thin films comprising a first electrode, an absorber film and a metallic electrode. A collection gate is arranged in contact with the first electrode to reduce its electrical resistance and avoid direct physical or electrical contact with the metallic electrode. The photovoltaic active zone includes a plurality of channels, made in the metallic electrode and the absorber film. The collection gate is separated from the metallic electrode and from the absorber film by a dielectric material.Type: GrantFiled: July 10, 2020Date of Patent: August 23, 2022Inventors: Philippe Gilbert Frederic Cardi, Sylvain De Vecchi
-
Patent number: 10002985Abstract: A solar cell module and a method for manufacturing the same are disclosed. The solar cell module includes solar cells each including a semiconductor substrate, and first electrodes and second electrodes extending in a first direction on a surface of the semiconductor substrate, conductive lines extended in a second direction crossing the first direction on the surface of the semiconductor substrate and connected to the first electrodes or the second electrodes through a conductive adhesive, and an insulating adhesive portion extending in the first direction on at least a portion of the surface of the semiconductor substrate, on which the conductive lines are disposed, and fixing the conductive lines to the semiconductor substrate and the first and second electrodes. The insulating adhesive portion is attached up to an upper part and a side of at least a portion of each conductive line.Type: GrantFiled: September 9, 2016Date of Patent: June 19, 2018Assignee: LG ELECTRONICS INC.Inventors: Joonhan Kwon, Hyeyoung Yang, Bojoong Kim
-
Patent number: 9893241Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.Type: GrantFiled: November 14, 2016Date of Patent: February 13, 2018Assignee: EPISTAR CORPORATIONInventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
-
Patent number: 9537031Abstract: A method for fabricating a solar cell using a nozzle assembly that includes a base portion, a scriber coupled to the base portion, and a nozzle coupled to the base portion such that the nozzle is positioned a predefined distance from a tip of the scriber is provided. The method generally comprises positioning a substructure that includes a buffer layer and an absorber layer proximate to the base portion. A P2 line is scribed through the buffer and absorber layers of the substructure using the scriber tip. A nanoparticle solution is sprayed, using the nozzle, onto at least one portion of the buffer layer at a predefined pressure when the P2 line is being scribed through the buffer and absorber layers such that a transparent conductive oxide (TCO) layer is inhibited from forming over the portion of the buffer layer that is being sprayed with the nanoparticle solution.Type: GrantFiled: June 28, 2013Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shih-Wei Chen
-
Patent number: 9024397Abstract: A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to ?40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.Type: GrantFiled: January 7, 2012Date of Patent: May 5, 2015Assignee: Texas Instruments IncorporatedInventors: Peter J. Hopper, William French, Paul Mawson, Steven Hunt, Roozbeh Parsa, Martin Fallon, Ann Gabrys, Andrei Papou
-
Patent number: 9024179Abstract: The invention is directed to a polymer thick film conductive composition comprising (a) a conductive silver-coated copper powder; and (b) an organic medium comprising two different resins and organic solvent, wherein the ratio of the weight of the conductive silver-coated copper powder to the total weight of the two different resins is between 5:1 and 45:1. The invention is further directed to a method of electrode grid and/or bus bar formation on thin-film photovoltaic cells using the composition and to cells formed from the method and the composition.Type: GrantFiled: April 9, 2014Date of Patent: May 5, 2015Assignee: E I du Pont de Nemours and CompanyInventor: Jay Robert Dorfman
-
Patent number: 8994132Abstract: A photoelectric conversion element includes an insulating film, a first electrode, a light receiving layer, and a second electrode. The first electrode is formed on the insulating film and is made of titanium oxynitride. The light receiving layer is formed on the first electrode and includes an organic material. A composition of the first electrode just before forming the light receiving layer meets (1) a requirement that an amount of oxygen contained in the whole of the first electrode is 75 atm % or more of an amount of titanium, or (2) a requirement that in a range of from the substrate side of the first electrode to 10 nm or a range of from the substrate side of the first electrode to ? of the thickness of the first electrode, an amount of oxygen is 40 atm % or more of an amount of titanium.Type: GrantFiled: September 26, 2011Date of Patent: March 31, 2015Assignee: FUJIFILM CorporationInventors: Tetsuro Mitsui, Yuki Kuramoto
-
Patent number: 8987042Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° C. or less and having a contact resistance of less than 5×10?4 ohms-cm2.Type: GrantFiled: May 22, 2014Date of Patent: March 24, 2015Assignee: SolAero Technologies Corp.Inventors: Tansen Varghese, Arthur Cornfeld
-
Patent number: 8987035Abstract: A method for producing an infrared light detector (1) has the steps of: providing a plurality of connection pins (11, 12), which are kept parallel to one another and arranged with one of the longitudinal ends (17, 18) thereof in a horizontal plane, and a printed circuit board (6) with a planar underside (8), in which a recess (15, 16) of the same form in each case is provided for each of the connection pins (11, 12); filling the recesses (15, 16) with a solder paste, so that in each of the recesses (15, 16) there is a solder paste body (21) with the same amount of solder paste; positioning the printed circuit board (6) over the connection pins (11, 12), so that each of the connection pins (11, 12) extends with its longitudinal end (17, 18) in the recess (15, 16) assigned to it and dips in the solder paste body (21) located in the respective recess (15, 16); liquefying the solder paste bodies (21), so that electrically conducting connections are formed between the connection pins (11, 12) and the solder pasteType: GrantFiled: December 21, 2010Date of Patent: March 24, 2015Assignee: Pyreos, Ltd.Inventors: Ron Laird, Scott Freeborn, Archie Shaw Stewart
-
Patent number: 8975715Abstract: A photodetector includes a substrate and an insulating arrangement formed in the substrate. The insulating arrangement electrically insulates a confined region of the substrate. The confined region is configured to generate free charge carriers in response to an irradiation. The photodetector further includes a read-out electrode arrangement configured to provide a photocurrent formed by at least a portion of the free charge carriers that are generated in response to the irradiation. The photodetector also includes a biasing electrode arrangement that is electrically insulated against the confined region by means of the insulating arrangement. The biasing electrode arrangement is configured to cause an influence on a spatial charge carrier distribution within the confined region so that fewer of the free charge carriers recombine at boundaries of the confined region compared to an unbiased state.Type: GrantFiled: June 29, 2012Date of Patent: March 10, 2015Assignee: Infineon Technologies AGInventor: Thoralf Kautzsch
-
Patent number: 8969194Abstract: Disclosed is a backside illuminated image sensor including a light receiving element formed in a first substrate, an interlayer insulation layer formed on the first substrate including the light receiving element, a via hole formed through the interlayer insulation layer and the first substrate while being spaced apart from the light receiving element, a spacer formed on an inner sidewall of the via hole, an alignment key to fill the via hole, interconnection layers formed on the interlayer insulation layer in a multilayer structure in which a backside of a lowermost layer of the interconnection layers is connected to the alignment key, a passivation layer covering the interconnection layers, a pad locally formed on a backside of the first substrate and connected to a backside of the alignment key, and a color filter and a microlens formed on the backside of the first substrate corresponding to the light receiving element.Type: GrantFiled: October 15, 2013Date of Patent: March 3, 2015Assignee: Intellectual Ventures II LLCInventor: Sung-Gyu Pyo
-
Patent number: 8969122Abstract: Processes for fabricating photovoltaic devices in which the front side contact metal semiconductor alloy metallization patterns have a uniform thickness at edge portions as well as a central portion of each metallization pattern are provided.Type: GrantFiled: June 14, 2011Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Kathryn C. Fisher, Qiang Huang, Satyavolu S. Papa Rao, David L. Rath
-
Patent number: 8962984Abstract: Disclosed is a solar cell apparatus and manufacturing method thereof. A solar cell apparatus includes: a support substrate; a first back electrode disposed on the support substrate; a light absorber part disposed on the first back electrode; a buffer disposed on the light absorber part; and a barrier film disposed on a side surface of the light absorber part and extending from the buffer.Type: GrantFiled: March 24, 2011Date of Patent: February 24, 2015Assignee: LG Innotek Co., Ltd.Inventor: Suk Jae Jee
-
Patent number: 8962380Abstract: Back contact back junction solar cell and methods for manufacturing are provided. The back contact back junction solar cell comprises a substrate having a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer and patterned reflective layer on the emitter form a light trapping backside mirror. An interdigitated metallization pattern is positioned on the backside of the solar cell and a permanent reinforcement provides support to the cell.Type: GrantFiled: December 9, 2010Date of Patent: February 24, 2015Assignee: Solexel, Inc.Inventors: Mehrdad M Moslehi, Pawan Kapur, Karl-Josef Kramer, David Xuan-Qi Wang, Sean Seutter, Virenda V Rana, Anthony Calcaterra, Emmanuel Van Kerschaver
-
Patent number: 8927314Abstract: A method of manufacturing a solar cell includes the steps of: providing a substrate having a front side, a back side and a doped region; forming a conductor layer on the front side; firing the conductor layer at a temperature such that the conductor layer is formed with a first portion embedded into the doped region and a second portion other than the first portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the conductor layer so that the second portion of the conductor layer is disposed in the ARC layer; and removing the ARC layer on the conductor layer so that the conductor layer has an exposed surface exposed out of the ARC layer, wherein the exposed surface of the conductor layer is substantially flush with a first exposed surface of the ARC layer.Type: GrantFiled: July 16, 2012Date of Patent: January 6, 2015Assignee: Big Sun Energy Technology Inc.Inventors: Sheng Yung Liu, Chin-Tien Yang, Chun-Hung Lin
-
Patent number: 8921967Abstract: An integrated circuit (IC) combination of a target integrated circuit (TIC) and a plurality of thin film photovoltaic cells (PV) connected thereto. The IC comprises a target integrated circuit (TIC) having a top surface and a bottom surface; a plurality of thin film photovoltaic (PV) cells formed over at least one of the top surface and the bottom surface of the TIC, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output.Type: GrantFiled: December 19, 2011Date of Patent: December 30, 2014Assignee: Sol Chip Ltd.Inventors: Shani Keysar, Reuven Holzer, Ofer Navon, Ram Friedlander
-
Patent number: 8890767Abstract: Provided are an active metamaterial device operating at a high speed and a manufacturing method thereof. The active metamaterial device includes a first dielectric layer, a lower electrode disposed on the first dielectric layer, a second dielectric layer disposed on the lower electrode, metamaterial patterns disposed on the second dielectric layer, a couple layer disposed on the metamaterial patterns and the second dielectric layer, a third dielectric layer disposed on the couple layer, and an upper electrode disposed on the third dielectric layer.Type: GrantFiled: March 27, 2012Date of Patent: November 18, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Choon Gi Choi, Muhan Choi, Sung-Yool Choi
-
Patent number: 8889471Abstract: For solar cell fabrication, the addition of precursors to printable media to assist etching through silicon nitride or silicon oxide layer thus affording contact with the substance underneath the nitride or oxide layer. The etching mechanism may be by molten ceramics formed in situ, fluoride-based etching, as well as a combination of the two.Type: GrantFiled: May 7, 2012Date of Patent: November 18, 2014Assignee: Sichuan Yinhe Chemical Co., Ltd.Inventors: Ovadia Abed, Yunjun Li, James P. Novak, Samuel Kim, Patrick Ferguson
-
Patent number: 8878325Abstract: A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.Type: GrantFiled: November 7, 2012Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Hsun Wan, Yi-Shin Chu, Szu-Ying Chen, Pao-Tung Chen, Jen-Cheng Liu, Dun-Nian Yaung
-
Patent number: 8859423Abstract: Embodiments of methods for fabricating polymer nanostructures and nanostructured electrodes are disclosed. Material layers are deposited onto polymer nanostructures to form nanostructured electrodes and devices including the nanostructured electrodes, such as photovoltaic cells, light-emitting diodes, and field-effect transistors. Embodiments of the disclosed methods are suitable for commercial-scale production of large-area nanostructured polymer scaffolds and large-area nanostructured electrodes.Type: GrantFiled: August 11, 2011Date of Patent: October 14, 2014Assignee: The Arizona Board of Regents on behalf of the University of ArizonaInventors: Jayan Thomas, Nasser N. Peyghambarian, Robert A. Norwood, Palash Gangopadhyay, Akram A. Khosroabadi
-
Patent number: 8859322Abstract: The present invention relates to cost effective production methods of high efficiency silicon based back-contacted back-junction solar panels and solar panels thereof having a multiplicity of alternating rectangular emitter- and base regions on the back-side of each cell, each with rectangular metallic electric finger conductor above and running in parallel with the corresponding emitter- and base region, a first insulation layer in-between the wafer and finger conductors, and a second insulation layer in between the finger conductors and cell interconnections.Type: GrantFiled: September 28, 2012Date of Patent: October 14, 2014Assignee: Rec Solar Pte. Ltd.Inventors: Richard Hamilton Sewell, Andreas Bentzen
-
Patent number: 8852989Abstract: Methods for increasing the power output of a TFPV solar panel using thin absorber layers comprise techniques for roughening and/or texturing the back contact layer. The techniques comprise roughening the substrate prior to the back contact deposition, embedding particles in sol-gel films formed on the substrate, and forming multicomponent, polycrystalline films that result in a roughened surface after a wet etch step, etc.Type: GrantFiled: October 27, 2011Date of Patent: October 7, 2014Assignee: Intermolecular, Inc.Inventors: Jeroen Van Duren, Haifan Liang
-
Patent number: 8853732Abstract: The invention relates to an optoelectronic component, having —a carrier (1) comprising a first main surface (Ia), —at least one optoelectronic semiconductor chip (2) having no substrate, and —a contact metallization (3a, 3b), wherein —the carrier (1) is electrically insulating, —the at least one optoelectronic semiconductor chip (2) is fastened to the first main surface (Ia) of the carrier (1) by means of a bonding material (4), particularly a solder material, —the contact metallization (3a, 3b) covers at least one area of the first main surface (Ia) free of the optoelectronic semiconductor chip (2), and —the contact metallization (3a, 3b) is electrically conductively connected to the optoelectronic semiconductor chip (2).Type: GrantFiled: August 31, 2010Date of Patent: October 7, 2014Assignee: OSRAM Opto Semiconductors GmbHInventors: Klaus Müller, Günter Spath, Siegfried Herrmann, Ewald Karl Michael Günther, Herbert Brunner
-
Patent number: 8841157Abstract: A thin film photovoltaic device includes a substrate and a first conductive layer coupled to the substrate. The first conductive layer includes at least one first groove extending through a first portion of the first conductive layer to a portion of the substrate. The device also includes at least one semiconductor layer coupled to a remaining portion of the first conductive layer and the portion of the substrate. The at least one semiconductor layer includes a plurality of non-overlapping vias, each via extending through a portion of the at least one semiconductor layer to a portion of the first conductive layer. The device further includes a second conductive layer coupled to a remaining portion of the at least one semiconductor layer and portions of the first conductive layer. The second conductive layer includes at least one second groove extending through a portion of the second conductive layer to a portion of the at least one semiconductor layer.Type: GrantFiled: January 4, 2012Date of Patent: September 23, 2014Assignee: Esi-Pyrophotonics Lasers IncInventor: Matthew Rekow
-
Patent number: 8828789Abstract: It is the gist of the present invention to provide a photovoltaic device in which a single crystal semiconductor layer provided over a substrate having an insulating surface or an insulating substrate is used as a photoelectric conversion layer, and the single crystal semiconductor layer is provided with a so-called SOI structure where the single crystal semiconductor layer is bonded to the substrate with an insulating layer interposed therebetween. As the single crystal semiconductor layer having a function as a photoelectric conversion layer, a single crystal semiconductor layer obtained by separation and transfer of an outer layer portion of a single crystal semiconductor substrate is used.Type: GrantFiled: February 3, 2011Date of Patent: September 9, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuyuki Arai
-
Patent number: 8803271Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the dielectric layer is over a back surface of the semiconductor substrate. A metal shield is over the dielectric layer and overlapping the photo-sensitive device. A metal plug penetrates through the dielectric layer, wherein the metal plug electrically couples the metal shield to the semiconductor substrate.Type: GrantFiled: March 23, 2012Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhe-Ju Liu, Chih-Cherng Jeng, Kuo-Cheng Lee, Szu-Hung Yang, Po-Zen Chen, Chi-Chin Hsu
-
Patent number: 8796804Abstract: An integrated circuit structure includes a substrate and a metallization layer over the substrate. The metallization layer includes a dielectric layer and metal lines in the dielectric layer. The integrated circuit structure further includes a sensing element over the metallization layer. The sensing element may be formed in passivation layers.Type: GrantFiled: April 22, 2008Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke Chun Liu, Kuan-Chieh Huang, Chin-Min Lin, Ken Wen-Chien Fu, Mingo Lin
-
Patent number: 8779280Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a first doped region of a first conductive type formed on a semiconductor substrate of the first conductive type, a second doped region of a second conductive type opposite the first conductive type formed on the semiconductor substrate at a location adjacent to the first doped region, a passivation layer exposing a portion of each of the first and second doped regions, a first electrode formed on the exposed portion of the first doped region, and a second electrode formed on the exposed portion of the second doped region. The first electrode includes a metal seed layer directly contacting the first doped region, and the second electrode includes a metal seed layer directly contacting the second doped region.Type: GrantFiled: August 17, 2010Date of Patent: July 15, 2014Assignee: LG Electronics Inc.Inventors: Sungeun Lee, Youngho Choe
-
Patent number: 8778720Abstract: Discussed is a fabrication method of a solar cell according to an embodiment of the invention, which includes forming an electrode material on a semiconductor substrate for the solar cell; and forming an electrode by heat treating the electrode material by laser irradiation, wherein the electrode material comprises at least one of an electrode paste, electrode ink and aerosol for the electrode.Type: GrantFiled: November 9, 2011Date of Patent: July 15, 2014Assignee: LG Electronics Inc.Inventors: Jong Hwan Kim, Hwa Nyeon Kim, Ju Hwan Yun
-
Patent number: 8766389Abstract: A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.Type: GrantFiled: December 27, 2011Date of Patent: July 1, 2014Assignee: Sony CorporationInventor: Naoyuki Sato
-
Patent number: 8759668Abstract: Formulations and methods of making solar cells are disclosed. In general, the invention provides a solar cell comprising a contact made from a mixture wherein, prior to firing, the mixture comprises at least one aluminum source, at least one boron source, and about 0.1 to about 10 wt % of a glass component. Within the mixture, the overall content of aluminum is about 50 wt % to about 85 wt % of the mixture, and the overall content of boron is about 0.05 to about 20 wt % of the mixture.Type: GrantFiled: October 24, 2011Date of Patent: June 24, 2014Assignee: Heraeus Precious Metals North America Conshohocken LLCInventors: Jalal Salami, Srinivasan Sridharan, Steve S. Kim, Aziz S. Shaikh
-
Patent number: 8753918Abstract: A method of forming a solar cell including: providing a semiconductor body including at least one photoactive junction; forming a semiconductor contact layer composed of GaAs deposited over the semiconductor body; and depositing a metal contact layer including a germanium layer and a palladium layer over the semiconductor contact layer so that the specific contact resistance is less than 5×10?4 ohms-cm2.Type: GrantFiled: September 4, 2012Date of Patent: June 17, 2014Assignee: Emcore Solar Power, Inc.Inventors: Tansen Varghese, Arthur Cornfeld
-
Patent number: 8748218Abstract: A solar cell and a method for manufacturing the same are discussed. The solar cell includes a substrate of a first conductive type, an emitter layer of a second conductive type opposite the first conductive type, a plurality of first electrodes each including a first electrode layer connected to the emitter layer and a second electrode layer positioned on the first electrode layer, at least one first current collector connected to the plurality of first electrodes, and a second electrode connected to the substrate. The emitter layer forms a p-n junction along with the substrate. The first electrode layer has a first width and the second electrode layer has a second width less than the first width of the first electrode layer.Type: GrantFiled: April 7, 2011Date of Patent: June 10, 2014Assignee: LG Electronics Inc.Inventors: Sungjin Kim, Youngsung Yang, Taeyoung Kwon, Seongeun Lee
-
Patent number: 8728857Abstract: A photovoltaic solar cell for generating electricity from sunlight is disclosed. The photovoltaic solar cell comprises a plurality of spaced-apart point contact junctions formed in a semiconductor body to receive the sunlight and generate the electricity therefrom, the plurality of spaced-apart point contact junctions having a first plurality of regions having a first doping type and a second plurality of regions having a second doping type. In addition, the photovoltaic solar cell comprises a first electrical contact electrically connected to each of the first plurality of regions and a second electrical contact electrically connected to each of the second plurality of regions, as well as a passivation layer covering major surfaces and sidewalls of the photovoltaic solar cell.Type: GrantFiled: November 25, 2013Date of Patent: May 20, 2014Assignee: Sandia CorporationInventors: Gregory N. Nielson, Jose Luis Cruz-Campa, Murat Okandan, Paul J. Resnick
-
Patent number: 8728848Abstract: A method for forming, on an organic semiconductor layer, an electrical contact layer comprising a metal, is disclosed. In one aspect, the method includes providing a charge collecting barrier layer on the organic semiconductor layer, providing a liquid composition comprising a precursor for the metal on the charge collecting barrier layer, and performing a sintering process. The charge collecting barrier layer is substantially impermeable to the components of the liquid composition.Type: GrantFiled: May 12, 2011Date of Patent: May 20, 2014Assignees: IMEC, Katholieke Universiteit Leuven R&DInventor: Claudio Girotto
-
Patent number: 8722448Abstract: A photo detector and related fabricating method are disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer. The patterned conductive layer is disposed on the dielectric layer. The inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region.Type: GrantFiled: October 30, 2013Date of Patent: May 13, 2014Assignee: AU Optronics Corp.Inventors: Yu-Min Lin, Hsin-Li Chen, Feng-Yuan Gan
-
Publication number: 20140127853Abstract: A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer.Type: ApplicationFiled: November 5, 2012Publication date: May 8, 2014Applicants: Bay Zu Precision Co., Ltd., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shun-Ming Chen, Chien-Chih Huang, Joel P. Desouza, Augustin J. Hong, Jeehwan Kim, Chien-Yeh Ku, Devendra K. Sadana, Chuan-Wen Wang