Abstract: A magnetic recording array includes a plurality of spin elements, and a shared transistor connected to a first spin element and a second spin element adjacent to each other, in which each of the plurality of spin elements includes a wiring and a laminate including a first ferromagnetic layer laminated on the wiring, the shared transistor includes a first gate, a second gate, a first region, a second region, and a third region, in a plan view in a laminating direction of the laminate, the first region is sandwiched between the first gate and the second gate, the second region together with the first region sandwiches the first gate, and the third region together with the first region sandwiches the second gate, and one of the second region and the third region is connected to the first spin element, and the other is connected to the second spin element.

Abstract: A lithium boron coating and a method of producing the same. Atomic layer deposition deposits lithium and boron to form a lithium borate layer. The lithium borate maybe deposited as a solid electrolyte.

Abstract: A semiconductor memory includes a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and a first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein portions of the third line located in the cell region and over the contact plug contact the second line, and part of a remainder of the third line is spaced apart from the second line.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

Abstract: A storage device includes a resistance change memory element including a first electrode, a second electrode, a resistance change layer between the first and second electrodes, including at least two elements selected from a group consisting of germanium (Ge), antimony (Sb), and tellurium (Te), and having a crystal structure with a c-axis oriented in a first direction from the first electrode toward the second electrode, and a first layer between the first electrode and the resistance change layer and including nitrogen (N) and at least one of silicon (Si) or germanium (Ge).

Abstract: A semiconductor device may include first row lines each extending in a first direction, column lines each extending in a second direction crossing the first direction, second row lines each extending in the first direction, a plurality of first memory cells respectively coupled between the first row lines and the column lines, each of the plurality of first memory cells including a first variable resistance layer and a first dielectric layer positioned between the first variable resistance layer and a corresponding one of the first row lines, and a plurality of second memory cells respectively coupled between the second row lines and the column lines, each of the plurality of second memory cells including a second variable resistance layer and a second dielectric layer positioned between the second variable resistance layer and a corresponding one of the second row lines.

Abstract: A capacitor structure and a manufacturing method thereof are disclosed in this invention. The capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric stacked layer. The capacitor dielectric stacked layer is disposed between the first electrode and the second electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. A manufacturing method of a capacitor structure includes the following steps. A capacitor dielectric stacked layer is formed on a first electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. Subsequently, a second electrode is formed on the capacitor dielectric stacked layer, and the capacitor dielectric stacked layer is located between the first electrode and the second electrode.

Abstract: A method includes etching a first and a second semiconductor fin to form a first and a second recesses, epitaxially growing an n-type source/drain region comprising a first portion and a second portion from the first and the second recesses, and a first middle portion in between and having a concave top surface. A first contact opening is formed extending into the n-type source/drain region and having a first V-shaped bottom. The method further includes etching a third and a fourth semiconductor fin to form a third and a fourth recesses, and forming a p-type source/drain region including a third portion and a third portion grown from the third and the fourth recesses, and a second middle portion in between and having a convex top surface. A second contact opening is formed and has a second V-shaped bottom, with a tip of the second V-shaped bottom being downwardly pointing.

Abstract: A semiconductor memory device and associated methods, the device including first and second lower conductive lines extending in a first direction; a first middle conductive line on the first and second lower conductive lines and extending in a second direction; first and second memory cells between the first and second lower conductive lines and the first middle conductive line; an air gap support layer between the first and second memory cells; and a first air gap between the first and second memory cells and under the air gap support layer, wherein an upper surface of the air gap support layer lies in a same plane as the first and second memory cells, the first and second memory cells include first and second OTS layers and first and second phase-change layers, and the first air gap overlaps the first and second phase-change layers.

Abstract: A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.

Abstract: A resistance access memory device includes a first electrode, a resistance change layer, formed on the first electrode, comprising a thin film containing BiX13 and and Bi2X2(3-x), and a second electrode formed on the resistance change layer, where X1 is a halogen element selected from the group consisting of F, Cl, Br, I, and combinations thereof, X2 is a chalcogen element selected from the group consisting of S, Se, Te, and combinations thereof, and x is a real number of 0 or more and less than 3.

Abstract: Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.

Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode, a dielectric cap above the first electrode, a second electrode laterally adjacent to the first electrode, in which an upper surface of the second electrode is substantially coplanar with an upper surface of the dielectric cap, and a resistive layer between the first electrode and the second electrode. An edge of the first electrode is electrically coupled to an edge of the second electrode by at least the resistive layer.

Abstract: A resistive memory including a substrate, a first electrode, a second electrode, a resistance changeable layer and an oxygen reservoir layer is provided. The first electrode is located on the substrate. The second electrode is located between the first electrode and the substrate. The resistance changeable layer is located between the first electrode and the second electrode. The oxygen reservoir layer is located between the first electrode and the resistance changeable layer. The oxygen reservoir layer includes a first portion, a second portion and a third portion. The second portion is connected to one side of the first portion. The third portion is connected to the other side of the first portion. A thickness of the first portion is greater than a thickness of the second portion and a thickness of the third portion. The first portion of the oxygen reservoir layer protrudes toward the first electrode.

Abstract: One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening.

Abstract: A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; a variable resistance element formed over the substrate and exhibiting different resistance values representing different digital information, the variable resistance element including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; and a blocking layer disposed on at least sidewalls of the variable resistance element, wherein the blocking layer may include a layer that is substantially free of nitrogen, oxygen or a combination thereof.

Abstract: A device and a method of forming same are provided. The device includes a substrate, a first dielectric layer over the substrate, a bottom electrode extending through the first dielectric layer, a phase-change layer over the bottom electrode, and a top electrode over the phase-change layer. The phase-change layer includes a first portion extending into the bottom electrode and a second portion over the first portion and the first dielectric layer. A width of the first portion decreases as the first portion extends toward the substrate. The second portion has a first width. The top electrode has the first width.

Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

Abstract: A semiconductor memory device including a device isolation layer in a substrate to define first and second active portions, a first contact on the substrate, first and second memory cells spaced apart from the first contact in a first direction by first and second distances, respectively, first and second conductive lines connected to the first and second memory cells, respectively, and extending in a second direction, and first and second selection transistors respectively connected to the first and second conductive lines. A length of a bottom surface of a first gate electrode of the first selection transistor overlapping the first active portion in a third direction may be different from a length of a bottom surface of a second gate electrode of the second selection transistor overlapping the second active portion in the third direction.

Abstract: An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

Abstract: Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line, a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line.

Abstract: A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed over the substrate, a gate insulation layer disposed on the resistance change layer, a gate electrode layer disposed on the gate insulation layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed respectively over the substrate and disposed to contact a different portion of the resistance change layer.

Abstract: A switch device according to an embodiment of the present disclosure includes a first electrode; a second electrode opposed to the first electrode; and a switch layer including selenium (Se), at least one kind of germanium (Ge) or silicon (Si), boron (B), carbon (C), (Ga), and arsenic (As), and provided between the first electrode and the second electrode.

Abstract: A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.

Abstract: Disclosed herein are selector devices and related devices and techniques. For example, in some embodiments, a selector device may include a first electrode, a second electrode, and a selector material stack between the first electrode and the second electrode. The selector material stack may include a dielectric material layer between a first conductive material layer and a second conductive material layer. A first material layer may be present between the first electrode and the first conductive material layer, and a second material layer may be present between the first conductive material layer and the dielectric layer. The first material layer and the second material layer may be diffusion barriers, and the second material layer may be a weaker diffusion barrier than the first material layer.

Abstract: Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria.

Abstract: A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.

Abstract: The memory cell includes a memory area which is formed in a phase-change material pattern based on chalcogenide. An electric p/n-type junction is series-connected between electrodes. The p/n junction is formed in a crystalline area by the interface between first and second doped areas of the phase-change material pattern. The memory area is formed in one of the two doped areas, at a distance from the junction.

Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

Abstract: Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof.

Abstract: A memory device includes a substrate and a memory array on the substrate. The memory array includes memory cells including stressed phase change materials in a layer of encapsulation materials. The memory cells may include memory cell structures such as mushroom-type memory cell structures, bridge-type memory cell structures, active-in-via type memory cell structures, and pore-type memory cell structures. The stressed phase change materials may comprise GST (GexSbxTex) materials in general and Ge2Sb2Te5 in particular. To manufacture the memory device, a substrate is first fabricated. Memory cells including phase change materials in a layer of encapsulation materials are formed on a front side of the substrate. A tensile or compressive stress is induced into the phase change materials on the front side of the substrate.

Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.

Abstract: A structure for a variable-resistance element using an electrochemical reaction. The structure limits a position at which metal cross-linking breaks to a position most preferred for cross-linking break: namely, a part of an ion conduction layer closest to a first electrode. Also provided is a method for manufacturing the variable-resistance element, which has a first electrode serving as a source for a metal ion(s), a second electrode which is less ionizable (i.e. has a higher redox potential) than the first electrode, and an ion conduction layer which is interposed between the first and second electrodes and can conduct the metal ion(s). There is a first region in the ion conduction layer, adjacent to the first electrode, having a diffusion coefficient that increases continuously towards the first electrode right upto contacting the first electrode.

Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

Abstract: A Zinc Oxide (ZnO) layer deposited using Atomic Layer Deposition (ALD) over a phase-change material forms a self-selected storage device. The diode formed at the ZnO/GST interface shows both rectification and storage capabilities within the PCM architecture.

Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line with a spacer of electrically insulating material surrounding the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact.

Abstract: The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract: Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion.

Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.