Semiconductor Or Barrier Layer Device (e.g., Integrated Circuit, Transistor, Etc.) Patents (Class 264/272.17)
  • Patent number: 7355278
    Abstract: A technology is provided that can seal the opening in a wiring board using a transfer mold insulating resin from the opening. A mold die is used which includes a first die having a recess in a predetermined form and a second flat die. The first die is disposed on a surface of a wiring board which has a plurality of openings and on which a semiconductor chip is mounted via an elastic material. The second die is disposed on a back surface of the wiring board opposite the surface on which the semiconductor chip is mounted. The mold is used for sealing with an insulating resin the periphery of the semiconductor chip and at least one of the openings of the wiring board, wherein the above-described second die has a protrusion around an area overlapping the opening to be sealed with the insulating resin.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: April 8, 2008
    Assignee: Hitachi Cable, Ltd.
    Inventors: Akiji Shibata, Akihiro Okamoto, Yosuke Shimazaki, Kazumoto Komiya
  • Publication number: 20080029930
    Abstract: A resin molding mold 20 with a cavity 21 has a resin injection port 29a from which a molding resin 25 is injected toward the cavity 21, and an air release port 30a from which air from the cavity 21 is released during resin injection. Not only the resin injection port 29a but also the air release port 30a is formed in a top surface portion 21a of the cavity 21. Thus, even if a resin burr remains in the resin injection port 29a or the air release port 30a, it can be prevented from adhering to an external terminal 4A provided on a front surface portion 2a of the substrate 2.
    Type: Application
    Filed: June 5, 2007
    Publication date: February 7, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuo Ito, Takayuki Yoshida, Toshiyuki Fukuda, Takao Ochi
  • Publication number: 20070243667
    Abstract: The objective of the invention is to prevent electrostatic destruction of semiconductor chips during resin molding. With the semiconductor device manufacturing method, a substrate 400 that includes on the surface multiple semiconductor chips 410 and liquid resin 434 supplied to multiple semiconductor devices is supported by an electrically insulated lower die 200. An upper die 110 in which multiple shape-forming parts (cavities) 112 are formed is pressed against lower die 200 through the medium of a polymer release film 300, and liquid resin 434 on the substrate is molded.
    Type: Application
    Filed: April 16, 2007
    Publication date: October 18, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kiyoharu Takano, Makoto Yoshino, Yoshimi Takahashi
  • Patent number: 7267791
    Abstract: Disclosed is a method for producing light-guiding LED bodies in a mold, using a material that is flowable before becoming definitively solid. Each LED body comprises at least one light-emitting chip and at least two electrical connections that are connected to the chip. At least one flowable material is fed into the mold in chronologically separate steps via at least one of at least two locations. In a first step, the flowable material is fed into the mold so as to flow around the chip and the connections in that area. In further steps, one or several flowable materials are fed into areas other than the one in which the chip and connections are located. The inventive method for producing light-guiding LED bodies allows virtually all produced luminescent diodes to have the same optical characteristics and prevents the individual LED electronics from being spoiled through damage.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: September 11, 2007
    Assignee: G.L.I. Global Light Industries GmbH
    Inventors: Thorsten Ricking, Cem Olkay, Christine Weber
  • Patent number: 7265453
    Abstract: A semiconductor component includes a leadframe, a die, upper and lower body segments encapsulating the die, and dummy segments on the leadframe. The dummy segments are configured to vent trapped air in a molding compound during molding of the body segments, such that corners of the body segments do not include the trapped air.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: September 4, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Steven L. James, Lori Tandy, legal representative, William D. Tandy, deceased
  • Patent number: 7255610
    Abstract: An integrally multiple-molded part for electronic devices is provided capable of absorbing and relieving the internal stresses of a multiple-molded part, preventing the occurrence of clearances between the bonding side face of each electrical connection terminal and a resin, obtaining stable frictional force at the contact region between the bonding surface of the electrical connection terminal and an aluminum wire, obtaining the energy required for bonding, and achieving high bondability. The surface of the molded electrical connection terminal section formed as a primary-molded article becomes exposed after secondary molding, and a stress-absorbing structure is formed in the primary molding resin section of the primary-molded article that serves as a transmission path for stresses associated with the resin shrinkage occurring when the secondary molding resin is cured.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: August 14, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Katsuhide Oohashi, Shigeo Amagi, Osamu Miyo
  • Patent number: 7250687
    Abstract: A system for degating a packaged semiconductor device that includes a tape substrate includes a first element and a second element. The first element of the system is positionable adjacent to a first major surface of the packaged semiconductor device and includes a receptacle for receiving a portion of a gate of the packaged semiconductor device. A second element of the degating system is positionable adjacent to a second major surface of the packaged semiconductor device and includes a degating element alignable with the gate. The degating element is extendable through the gate to force a portion of the gate and a sprue therein into the receptacle of the first element.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: July 31, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Teck Kheng Lee, M Vijendran
  • Patent number: 7247267
    Abstract: A mold for molding semiconductor devices mounted on a package substrate is provided. The mold comprises a top mold and a bottom mold. The top mold has a top runner, at least a first dummy runner and a plurality of mold cavities. The first dummy runner connects with the top runner and the top runner extends into a space between the mold cavities. The mold cavities for accommodating the semiconductor devices are connected to the top runner. The bottom mold has a bottom runner and at least a second dummy runner. The second dummy runner connects with the bottom runner. The second dummy runner is above but separated from the first dummy runner by the package substrate.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: July 24, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jen-Chieh Kao, Kuo-Chung Yee
  • Patent number: 7241414
    Abstract: A method and apparatus is provided for molding a semiconductor device in a mold including two mold halves. One mold half includes a compressible sealing mechanism constructed and configured to exert a sealing pressure between a surface of the mold half and a surface of a semiconductor device located in the mold. A compliant tape is positionable onto the mold half comprising the sealing mechanism between the semiconductor device and the sealing mechanism for molding of the semiconductor device.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: July 10, 2007
    Assignee: ASM Technology Singapore Pte Ltd.
    Inventors: Shu C Ho, Teng H Kuah, Zhi P Zhang, Shuai G Lee, Chun Y Li, Yi Lin
  • Patent number: 7239933
    Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: July 3, 2007
    Assignee: Micron Technology, Inc.
    Inventors: William M. Hiatt, Warren M. Farnworth, David R. Hembree, Peter A. Benson
  • Patent number: 7205170
    Abstract: The invention relates to a method for producing light-conducting LED bodies by injection molding into a mold of a material that is fusible prior to final solidification. Each LED body comprises at least one light-emitting chip and at least two wire-shaped electrodes that are electrically connected to the chip. The injection mold is evacuated via at least one opening per LED after positioning the electronic parts and closing. The evacuation opening is disposed in the proximity of the electrodes in the bottom area of the LED. The fusible material is injected between the bottom area and the chip or the reflector trough at least approximately parallel to the chip surface and at least approximately normal to a surface embodied by two electrodes, with the center line of the injection stream running between two electrodes. The inventive method for producing light-conducting LED bodies prevents the LED electronics from being damaged during normal performance of the injection molding process.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: April 17, 2007
    Assignee: G.L.I. Global Light Industries GmbH
    Inventors: Thorsten Ricking, Cem Olkay, Jörg Lehmann, Thomas Manth
  • Patent number: 7195955
    Abstract: This disclosure describes a clear overmolding cap for protecting the photonic devices in optoelectronic packages from damage due to handling, module assembly, board assembly, and environmental exposure in field applications. The overmolding of the devices with a clear mold cap or similar material also provides a standoff for optical fibers positioned next to the active facets. The photonic devices are attached to a substrate, which may be flexible that has electronic traces that allow the photonic devices to be connected to an external device such as a semiconductor device. A technique for manufacturing the overmolding cap using a mold die system in combination with a rigid carrier is also disclosed. The rigid carrier is used to maintain the shape of the substrate during the molding process. The proposed method applies to photonic devices used in optoelectronic packages that can serve as transceivers, transmitters, or receivers.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: March 27, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Luu Thanh Nguyen, Ken Pham, Peter Deane, William Paul Mazotti, Bruce Carlton Roberts
  • Patent number: 7178235
    Abstract: A method for providing an encapsulated optoelectronic chip is provided. The optoelectronic chip is secured on a substrate. A translucent coating substance is then applied on said optoelectronic chip and the translucent coating substance is then polished away to enable an optical coupling.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: February 20, 2007
    Assignee: Reflex Photonics Inc.
    Inventors: David Robert Cameron Rolston, Tomasz Maj
  • Patent number: 7169345
    Abstract: According to one embodiment of the invention, a system for packaging integrated circuits includes a mold tool for packaging integrated circuits. The mold tool includes a first mold plate that includes a first non-planar surface and a second mold plate that includes a second non-planar surface. The first and second non-planar surfaces form upper and lower surfaces of a mold cavity when the first and second mold plates are engaged. The mold tool also includes a distribution system coupled to the mold cavity. The distribution system transfers a mold compound into the mold cavity to substantially encapsulate an integrated circuit. The distribution system includes a gate runner coupled to the mold cavity. The gate runner funnels the mold compound into the mold cavity. The distribution system also includes a bridge insert that decreases wear on the gate runner as the mold compound is transferred through the gate runner.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: January 30, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Selvarajan Murugan
  • Patent number: 7170158
    Abstract: A multi-chip package comprises a double-sided circuit board having first and second surfaces. Each surface has a package area and a peripheral area. Each package area has a chip mounting area on which a chip is attached, and a bonding area with which the chip is electrically connected. The peripheral area of the first surface has a runner area on which molding compound flows, and the peripheral area of the second surface has external connection pattern with which the bonding areas are electrically connected. In particular, the circuit board has gate holes, which are co-located on each surface to result in a common hole.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: January 30, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee Kook Choi, Cheol Joon Yoo
  • Patent number: 7153462
    Abstract: An injection casting system for encapsulating semiconductor products and method of use includes a mold unit having a cavity, a substrate material placed against the cavity, the cavity being filled by a liquid dispenser in contact with the bottom of the cavity and a running channel at the bottom of the cavity to receive the liquid dispenser for even dispersion of epoxy in the cavity from the bottom of the cavity upward to the top of the cavity.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: December 26, 2006
    Assignee: Vishay Infrared Components, Inc.
    Inventor: Haryanto Chandra
  • Patent number: 7144538
    Abstract: A method for forming a direct chip attach device (1) includes attaching an electronic chip (3) to a lead frame structure (2), which includes a flag (18). Next, conductive studs (22) are attached to bond pads (13) on electronic chip (3) and flag (18) to form a sub-assembly (24). Sub-assembly (24) is then placed in a molding apparatus (27,47), which includes a first plate (29,49) and second plate (31,51). Second plate (31,51) includes a cavity (32,52) for receiving electronic chip (3) and flag (18), and pins (36,56). During a molding step, pins (36,56) contact conductive studs (22) to prevent encapsulating material (4) from covering studs (22). This forms openings (6) to receive solder balls (9) during a subsequent processing step.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: December 5, 2006
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yeu Wen Lee, Chuan Kiak Ng, Guan Keng Quah
  • Patent number: 7070659
    Abstract: Explosive forces are used to fill interconnect material into trenches, via holes and other openings in semiconductor products. The interconnect material may be formed of metal. The metal may be heated prior to the force filling step. The explosive forces may be generated, for example, by igniting mixtures of gases such as hydrogen and oxygen, or liquids such as alcohol and hydrogen peroxide. To control or buffer the explosive force, a baffle may be interposed between the explosions and the products being processed. The baffle may be formed of a porous material to transmit waves to the semiconductor products while protecting the products from contaminants. Various operating parameters, including the flow rate of the fuel and the oxidizing materials, may be positively controlled. In another embodiment of the invention, a piston is used to transmit the explosive force. If desired, an annular space at the periphery of the piston may be maintained at atmospheric pressure to protect against wafer contamination.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: July 4, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Moore
  • Patent number: 7060216
    Abstract: The elements of a tire pressure monitoring and transmitting system are encapsulated into a single package. A pressure sensitive device is covered with a flexible gel coat and then inserted into a molding tool cavity. A removable pin is incorporated into the molding tool and in its normal position is in contact with the gel. A molding compound is injected into the cavity so as to encapsulate the device and gel coat. When the pin is extracted and the device ejected from the molding cavity, an airway is left defined by the removable pin. The airway exposes the flexible gel covering the pressure sensitive device to the local air pressure, whereby the gel, being flexible, transfers the pressure to the pressure sensitive device.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: June 13, 2006
    Assignee: Melexis, NV
    Inventor: Johan Schuurmans
  • Patent number: 7005101
    Abstract: The mold for a thin package uses a gate which has a high aspect ratio, about 30 degrees or greater throughout the length of the gate. Additionally, the depth of the gate goes to zero at a point outside of the area of the finished package, but within the dam bars, so that the leadframe space acts as a virtual gate. This reduces the need for trimming and lowers stress on the finished package.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: February 28, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Selvarajan Murugan
  • Patent number: 6989122
    Abstract: Techniques for forming packaged semiconductor devices having top surfaces with flash-free electrical contact surfaces are described. According to one aspect, a molding cavity is provided which has a molding surface that is sufficiently smooth such that when placed in contact with an electrically conductive contact, gaps between the conductive contact and the mold cavity surface do not form.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: January 24, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Ken Pham, Luu Thanh Nquyen, William Paul Mazotti
  • Patent number: 6989121
    Abstract: The upper and lower mold plates of a transfer molding machine are configured for one-side encapsulation of a pair of substrate mounted electronic devices having an opposite conductor-grid-array and/or bare heat sink/dissipater. A buffer member, optionally with cut-outs or apertures, may be placed between the two back-to-back substrates for protecting the grid-arrays and enabling encapsulation of devices with varying thicknesses without adjustment of the molding machine. Alternately, the upper and lower plates are configured for one-side encasement using covers of a pair of substrate mounted electronic devices having an opposite conductor-grid-array and/or bare heat sink/dissipater.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: January 24, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Steven G. Thummel
  • Patent number: 6977055
    Abstract: An elongated electrical cable or flexible circuit board includes an electrically conductive path and an insulating body encompassing and electrically isolating the conductive path, the insulating body including an exposed surface having an array of fastener elements extending therefrom, the fastener elements arranged and constructed to engage mating fastener elements associated with a supporting surface to selectively secure the cable or flexible circuit board to the supporting surface. The fastener elements can be loop-engageable fasteners and/or loops.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: December 20, 2005
    Assignee: Velcro Industries B.V.
    Inventors: Christopher M. Gallant, Michel Labrecque, Mark A. Clarner, John DeMain
  • Patent number: 6971863
    Abstract: A molding apparatus for molding semiconductor devices using a molding compound in which a mold is automatically treated with a mold releasing agent is provided. A lead frame strip in-magazine part and a tablet loading part are designed so that dummy lead frame strips and releasing tablets used in a mold releasing agent treatment process are automatically supplied to the molding apparatus in a mold releasing agent treatment mode or a mold cleaning mode. After the mold releasing agent treatment mode or mold cleaning mode is complete, the molding apparatus is switched back to a normal molding process and normal lead frame strips and molding compound tablets are to the mold part. In addition, a pick-up part and a stack magazine part are designed to distinguish by-products generated during the mold releasing agent treatment process from normally molded products by switching from a normal molding process to either a mold releasing agent treatment process or a mold cleaning process.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: December 6, 2005
    Assignee: Samsung Electronics Co., LTD
    Inventors: Kyung-soo Park, Tae-hyuk Kim, Hoon Chang, Sung-soo Lee
  • Patent number: 6969918
    Abstract: A system for fabricating semiconductor components includes mating mold cavity plates having mold cavities configured to mold body segments of the semiconductor components on either side of a leadframe. The mold cavity plates also include runners configured to direct molding compound between the mold cavities and into the corners of the mold cavities. The runners prevent trapped air from accumulating in the corners of the mold cavities, and eliminate the need for air vents in the corners. The mold cavity plates also include dummy mold cavities configured to form dummy segments on the leadframe, and air vents in flow communication with the dummy segments. The dummy mold cavities are configured to collect trapped air, and to direct the trapped air through the air vents to atmosphere. Each dummy mold cavity has only a single associated air vent, such that cleaning is facilitated, and flash particles from the air vents are reduced.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: November 29, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Steven L. James, Lori Tandy, legal representative, William D. Tandy, deceased
  • Patent number: 6956098
    Abstract: The substrates of the present invention comprise a polyimide base polymer derived at least in part from collinear monomers together with crankshaft monomers. The resulting polyimide material has been found to provide advantageous properties, particularly for electronics type applications.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: October 18, 2005
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: John Donald Summers, Richard Frederich Sutton, Jr., Brian Carl Auman
  • Patent number: 6949296
    Abstract: The substrates of the present invention comprise a polyimide base polymer derived at least in part from non-rigid rod monomers together with optionally rigid rod monomers where the substrates are cured under low tension. The resulting polyimide materials have been found to provide advantageous properties (e.g. balanced molecular orientation, good dimensional stability, and flatness) particularly useful for electronics type applications.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: September 27, 2005
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Meredith L. Dunbar, James R. Edman
  • Patent number: 6939501
    Abstract: A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: September 6, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Ford B. Grigg, James M. Ocker, Rick A. Leininger
  • Patent number: 6933176
    Abstract: A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one of a heat spreader, the semiconductor die and the substrate. The heat spreader is fixed to the at least one of the first surface of the substrate and the semiconductor die such that he at least one collapsible spacer is disposed therebetween. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: August 23, 2005
    Assignee: Asat Ltd.
    Inventors: Mohan Kirloskar, Chun Ho Fan, Neil McLellan
  • Patent number: 6913950
    Abstract: A semiconductor device includes an insulating substrate, a cutout formed in side surfaces of the substrate, a conductive pad formed on the obverse surface of the substrate, an electrode formed on the reverse surface of the substrate, a semiconductor chip mounted on the substrate, and a connector which connects the pad to the electrode. The connector is arranged in the cutout.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: July 5, 2005
    Assignee: Rohm Co., Ltd.
    Inventor: Masahiko Kobayakawa
  • Patent number: 6896837
    Abstract: An apparatus and method for controlling the surface level of a liquid residing within a relatively vertically stationary workpiece support platform disposed within a reservoir for use in stereolithographic processes wherein a layered object or structure is formed by selectively curing portions of the liquid to at least a semisolid state in multiple, at least partially superimposed layers. Providing precise control of liquid depth over the vertically stationary platform as well as focusing of a laser beam for curing the liquid at the varying surface levels thereof relative to the vertically stationary platform is effected using a laser range finder system controlled by a computer used to control the stereolithographic process in a closed loop fashion.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: May 24, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Patent number: 6893903
    Abstract: A semiconductor device (21) can include, e.g., a recessed portion (25) on the reverse surface (224) of an insulating resin (22) which is the mounting surface of the semiconductor device (21). Additionally, on the outer peripheral surface of the recessed portion (25), the exposed region of leads (26) and the reverse surface (224) of the insulating resin (22) form generally the same plane. This allows, e.g., a QFN semiconductor device (21) according to preferred embodiments herein to place dust particles in the recessed portion (25) even in the presence of dust particles such as crushed burr particles of the leads (26) or plastic burrs, thereby avoiding mounting deficiencies when mounting the semiconductor device.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: May 17, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Isao Ochiai, Toshiyuki Take, Tetsuya Fukushima
  • Patent number: 6890459
    Abstract: A method for manufacturing a semiconductor laser package in accordance with a preferred embodiment of the present invention includes the following steps: providing a housing (20) with a top portion (21), the top portion defining an optical cavity (23) composed of a window (231) and a sprue (232); disposing the housing in a cavity of a mold (not shown); closing the mold and injecting a melted transparent plastic resin into the sprue to fill the sprue and the window, thereby forming an integrated optical element; and taking the package out of the mold after curing of the injected plastic resin. The optical element is integrated with the housing, permitting light to pass therethrough. The package has a strong structure and is not as easily damaged when subjected to impacts. The optical element is made of a plastic material which is comparatively inexpensive. Therefore, the manufacturing cost is further reduced.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: May 10, 2005
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventor: Nan Tsung Huang
  • Patent number: 6890460
    Abstract: Disclosed is a method for manufacturing a lens cap (20) for an optical module. The lens cap includes a housing (21) and an optical lens (22). The housing includes a sidewall (23) and a top wall (24) connecting with the sidewall. The top wall has an inclined portion (241) defining a through-hole (243) therein, and the through-hole includes a window (244) and an injection void (245) connecting with the window. The optical lens is made of optical plastic and is formed in the through-hole using insert-molding. The optical lens transmits and reflects light.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: May 10, 2005
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventor: Nan Tsung Huang
  • Patent number: 6881611
    Abstract: A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: April 19, 2005
    Assignee: Fujitsu Limited
    Inventors: Norio Fukasawa, Toshimi Kawahara, Muneharu Morioka, Mitsunada Osawa, Yasuhiro Shinma, Hirohisa Matsuki, Masanori Onodera, Junichi Kasai, Shigeyuki Maruyama, Masao Sakuma, Yoshimi Suzuki, Masashi Takenaka
  • Patent number: 6869556
    Abstract: The present invention provides a molding system as well as a method for encapsulating semiconductor packages, wherein a cavity plate is kept at a desired temperature during molding. The system includes a mold comprising a first mold piece and a second mold piece adapted to define a mold cavity for enclosing one or more semiconductor devices for molding, and a cavity plate adapted for mounting in the cavity to introduce encapsulation material to the semiconductor device(s). The system also includes retaining means adapted selectively to hold the cavity plate against the first mold piece or the second mold piece whereby to maintain the cavity plate at the desired temperature.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: March 22, 2005
    Assignee: ASM Technology Singapore Pte Ltd.
    Inventors: Shu Chuen Ho, Teng Hock Kuah, Jian Wu, Si Liang Lu
  • Patent number: 6869811
    Abstract: A semiconductor device includes a heat sink adjacent to a die. A dam is positioned at the peripheral edges of the heat sink. During a transfer molding process, the dam serves two purposes. First, the dam prevents damage to the mold. Second, the dam prevents encapsulant packaging compound material from flowing onto the heat sink. The dam may be a gasket. The dam may also be a burr created by, for example, stamping the bottom of the heat sink. The dam may include copper, polyamides, and leadlock tape. The dam may be permanently connected to the heat sink or removed following packaging. The dam may be removed mechanically, through the use of heat, or during an electrolytic deflash cycle.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: March 22, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Richard W. Wensel
  • Patent number: 6863516
    Abstract: A method and apparatus for reducing or eliminating the formation of air pockets or voids in a flowable material provided in contact with at least one substrate. The flowable material is provided in a non-horizontal direction and flows from a lower portion to an upper portion. As a result, the flowable material is provided uniformly with a single, uniform flow front due to gravity acting thereon and gravity thereby substantially preventing voids and air pockets from forming in the flowable material. In one embodiment, the at least one substrate is provided in the cavity of a transfer mold in which the cavity is filled from a gate at a lower portion of the cavity to a vent at an upper portion of the cavity. In another embodiment, a bumped semiconductor device is attached to a substrate having a gap therebetween, in which the gap is oriented longitudinally perpendicular to a horizontal plane so that the flowable material may fill the gap in a vertical direction.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: March 8, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Vernon M. Williams
  • Patent number: 6858910
    Abstract: A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process characterized by lining the cavity surfaces of the top and bottom mold halves with a protective plastic film, which also protects the surfaces of the components during the molding phase, selectively encapsulating the bonding pads and coupling members of the chip while leaving empty space above the components, and attaching a lid over the components. A molding method as well as a molding apparatus are provided compatible with the sensitivity of the micromechanical devices, yet flexible with regard to the technique used to assemble the chip and the substrate. Furthermore, the method disclosed is flexible with regard to the material and the properties of the substrate.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: February 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Anthony L. Coyle, George A. Bednarz
  • Patent number: 6840751
    Abstract: A die mold machine for molding a plurality of semiconductor assemblies on multiple substrate/leadframes includes a plurality of die mold layers stacked vertically one above the other to form a plurality of die mold sections. The top die mold layer has at least one aperture or die hall in the top most die layer and apertures or die halls in the in-between layers for passing molding compound which flows through the die hall in the top layer down through the die halls or apertures between the die mold layers into the die mold sections for molding semiconductor assemblies on said substrate/leadframes between said die mold layers.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: January 11, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Akira Matsunami
  • Patent number: 6838184
    Abstract: An aromatic polyimide film for producing an electro-conductive sealing element of a packaged semi-conductor device, has a thickness of 20 to 60 ?m, a moisture vapor transmission coefficient of 0.05 to 0.8 g/mm/m2·24 hrs, a water absorption ratio of 2.0% or less, and an elastic modulus in tension of 5,000 MPa or more, in which a surface of the polyimide film has been treated with reduced-pressure plasma discharge.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: January 4, 2005
    Assignee: Ube Industries, Ltd.
    Inventors: Takuji Takahashi, Toshihiko Anno, Kohji Narui, Shozo Katsuki
  • Publication number: 20040262811
    Abstract: A method for forming a direct chip attach device (1) includes attaching an electronic chip (3) to a lead frame structure (2), which includes a flag (18). Next, conductive studs (22) are attached to bond pads (13) on electronic chip (3) and flag (18) to form a sub-assembly (24). Sub-assembly (24) is then placed in a molding apparatus (27,47), which includes a first plate (29,49) and second plate (31,51). Second plate (31,51) includes a cavity (32,52) for receiving electronic chip (3) and flag (18), and pins (36,56). During a molding step, pins (36,56) contact conductive studs (22) to prevent encapsulating material (4) from covering studs (22). This forms openings (6) to receive solder balls (9) during a subsequent processing step.
    Type: Application
    Filed: June 26, 2003
    Publication date: December 30, 2004
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Yeu Wen Lee, Chuan Kiak Ng, Guan Keng Quah
  • Patent number: 6835596
    Abstract: An improvement of the yield of semiconductor devices is achieved in the manufacture of a semiconductor device. The method includes forming a resin enclosure for block-molding a plurality of a semiconductor chips by placing a plurality of semiconductor chips inside a cavity of a molding die along with a substrate, and then injecting a resin from a first side to a second side of a main surface of the substrate. The plurality of semiconductor chips are mounted on the main surface of the substrate from the first side to the second side of the main surface with a predetermined spacing, the second side facing the first side. The method is characterized by the application of cleaning treatment to the main surface of the substrate before forming the resin enclosure.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: December 28, 2004
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Masakatsu Gotou, Norihiko Kasai
  • Patent number: 6830719
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Publication number: 20040245674
    Abstract: The present invention provides methods for packaging small size memory cards wherein the methods comprise molding over a populated printed circuit board, thereby an encapsulated memory card is obtained with desirable external dimensions and features. In one aspect of the invention, methods are provided for preventing mold bleed underneath of the contact pads of memory cards. In one embodiment, the mold bleeding is prevented by using slidable holding pins that exert pressure directly upon the contact pins during the molding process. In another embodiments, the mold bleeding is prevented by covering the contact pads with temporary substrate coverage during the molding process. In yet another embodiment, the mold bleeding is prevented by using pressing edges that exert pressure directly upon the area of contact pads during the molding process. In still another embodiment, the mold bleeding is prevented by using vacuum pressure to secure the populated PCB onto the bottom of a molding apparatus.
    Type: Application
    Filed: April 8, 2004
    Publication date: December 9, 2004
    Inventors: Chee Kiang Yew, Piau Fong, Keng Siew Matthew Chua
  • Publication number: 20040239449
    Abstract: An encapsulation method for sensitive composition is provided in which a film, in particular a plastic film, is laminated over the entire surface of an arrangement having a component mounted on a carrier in a flip chip construction. For additional sealing and mechanical stabilization, a plastic compound in liquid form is subsequently applied and hardened so as to surround the chip. Optionally, before the application of the plastic compound, the film can be removed in the area of structuring lines in such a way that the plastic compound can come into contact both with the carrier and with the chip surface.
    Type: Application
    Filed: March 29, 2004
    Publication date: December 2, 2004
    Inventors: Alois Stelzl, Hans Kruger, Gregor Feiertag
  • Patent number: 6818169
    Abstract: A molding device and method utilizes a cavity including fast and second parts for molding an article having one or more convex portions and a gate for injecting mold resin into the cavity. The gate in turn includes one or more gate sides for injecting resin into a concave portion of one part and a gate base for injecting resin into a second of the parts in which no concave portions are located, both resin injections occurring simultaneously and substantially encapsulating a semiconductor element to form a molded article having a convex lens.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: November 16, 2004
    Assignee: International Business Machines Corporation
    Inventor: Kazuhiro Umemoto
  • Patent number: 6811738
    Abstract: A method is for forming a plastic protective package for an electronic device integrated on a semiconductor and comprising an electronic circuit to be encapsulated in the protective package. The electronic device may be at least partially activated from outside of the protective package. The method may include providing a mold having a half-mold with an insert abutting towards the inside of the mold and an end having an element that can be elastically deformed to abut in pressing contact against at least one portion of the integrated circuit. The method may also include injecting a resin into the mold so that the protective package has a hole by the at least one portion of the electronic circuit.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: November 2, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Pierangelo Magni, Andrea Cigada
  • Patent number: 6808661
    Abstract: A system is proposed for encapsulating in plastics material leadframe items comprising an IC wired to a leadframe. Dust of the plastics material is removed from the encapsulation system, and in particular from those items where dust principally accumulates, such as the surfaces of the molds. To reduce the level of dust which enters the molding region, the path along which the leadframe items are conveyed to the molding region is closed at times when the leadframe items are not being transported there. Additionally, the leadframe items are conveyed to the molding region under a cover including a vacuum source, so that the dust is continually sucked away from them.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: October 26, 2004
    Assignee: ASM Technology Singapore PTE Ltd.
    Inventors: See Yap Ong, Kock Hien Wee, Shu Chuen Ho, Teng Hock Kuah, Jian Wu
  • Patent number: 6805829
    Abstract: The invention relates to a method for production of three-dimensionally arranged conducting and connecting structures for volumetric and energy flows. Various light-setting materials are used for the production of the layers. Upon exchanging the materials, those layer regions in which no setting occurred during the preceding setting process, are also filled with new material, such that, in the subsequent setting process, not only is the upper layer linked to the one lying directly beneath it, but also material of the upper layer is connected to the material of a layer lying below the penultimate layer. It is thus possible, within the layer sequence, to connect a structure with varying properties from layer to layer.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: October 19, 2004
    Inventor: Reiner Götzen