Abstract: A method of manufacturing a capacitor-embedded PCB is disclosed. The method may include fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

Abstract: A method for producing an ink-jet head includes forming a buffer layer on an upper surface of a vibration plate, and forming a piezoelectric precursor layer on an entire upper surface of a surface layer, the piezoelectric precursor layer being converted into a piezoelectric sheet. The buffer layer is formed of a material with which mutual diffusion between the piezoelectric precursor layer and the buffer layer is hardly caused as compared with mutual diffusion between the piezoelectric precursor layer and the vibration plate with which no buffer layer is provided. A stack, in which the buffer layer and the piezoelectric precursor layer are formed, is heated at a predetermined temperature, and the piezoelectric precursor layer is calcinated to form the piezoelectric sheet. It is possible to suppress the deterioration of the performance of the piezoelectric member.

Abstract: The capacitor forming method utilizes a plurality of metal sheet manipulating rollers and a glass supply, which, in combination, make a metal-glass laminate and glass or devitrifying glass dielectric to form a capacitor. Several embodiments of the method manufacture ferroelectric crystal dielectrics by utilizing heat-treatment and annealing to form and devitrify glass while the glass is in a metal-glass spool or flat form.

Abstract: There is disclosed a thin film capacitor and the like capable of suppressing fluctuations of a capacity, increasing a VBD, and accordingly improving a device. characteristic and reliability of a product. In electronic components 1 to 4, a capacitor 11 is formed on a flat substrate 51 as a base material including a planarization layer 52 formed on the surface thereof. The capacitor 11 has a structure in which a lower conductor 21 constituted of an underlayer conductor 21a and a conductor 21b, a dielectric film 31 made of alumina or the like, a resin layer J1 mainly formed of a novolak resin or the like, a resin layer J2 mainly formed of a polyimide resin or the like, and an upper conductor 25 constituted of an underlayer conductor 25a and a conductor 25b are formed on the planarization layer 52 of the substrate 51. The resin layer J1 has an opening K1 above the lower conductor 21, and the resin layer J2 is provided with an opening K2 opened more widely than the opening K1.

Abstract: Disclosed are embodiments of a method of forming a capacitor with inter-digitated vertical plates such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.

Abstract: New designs for multilayer ceramic capacitors are described with high voltage capability without the need of coating the part to resist surface arc-over. One design combines a high overlap area for higher capacitance whilst retaining a high voltage capability. A variation of this design has increased voltage capability over this design as well as another described in the prior art although overlap area and subsequently capacitance is lowered in this case. These designs are compared to the prior art in examples below.

Abstract: The invention concerns multilayered constructions useful in forming capacitors and resistors, which may be used in the manufacture of printed circuit boards and microelectronic devices. A thermosetting polymer layer or layers are attached directly onto a heat resistant film layer, specifically on the side(s) of the heat resistant film to be attached to an electrically conductive layer having an electrical resistance material layer thereon. Attaching the adhesive to the heat resistant film rather than the electrically conductive layer streamlines the manufacturing process, particularly in the formation of the electrical resistance material layer onto the electrically conductive layer. This also results in better precision and uniformity of the multilayered construction.

Abstract: A method of manufacturing a printed wiring board including preparing a high-dielectric capacitor sheet including a ceramic high-dielectric layer sandwiched by upper and lower electrode sheets, attaching the high-dielectric capacitor sheet to a first insulating layer, forming through holes for the upper and lower electrode sheets such that the through holes penetrate through the ceramic high-dielectric layer and upper and lower electrode sheets, forming a second insulating layer which fills the through holes and covers an upper surface of the high-dielectric capacitor sheet, forming an upper electrode connecting first hole, an upper electrode connecting second hole and a lower electrode connecting hole, filling the upper holes with conductive material such that the upper electrode connecting first hole and the upper electrode connecting second hole are connected to form an upper electrode connection portion, and filling the lower electrode connecting hole with conductive material to form a lower electrode conn

Abstract: [Problem to be Solved] To provide a helical capacitor for controlling a high-frequency power which flows in power lines, and a manufacturing method of the helical capacitor. [Solution] A helical capacitor is constituted by helically spiraling a belt shape capacitor line 1001 which includes an internal metal body to be a helically spiraled belt-shape internal electrical conductor, a dielectric film covering the internal electrical conductor, and an electrically conductive layer covering the dielectric film. The capacitor line of belt shape 1001 can be wrapped around the internal support body 1200. Internal metal body lead terminals 1311, 1321 are respectively formed at both ends of the internal metal body, and electrically conductive layer lead terminals 1312, 1322 can be respectively formed at both ends of the electrically conductive layer.

Abstract: Provided herein are devices comprising a printed wiring board that comprise, singulated capacitors fabricated from known good, thin-film, fired-on-foil capacitors. Provided are methods of incorporating the singulated capacitors into the build-up layers of a printed wiring board to minimize impedance. The singulated capacitors have a pitch that allows each power and ground terminal of an IC to be directly connected to a power and ground electrode, respectively, of its own singulated capacitor. Using a feedstock of known good, fired-on-foil capacitors allows for improved PWB yield.

Abstract: The present invention relates to tunable capacitors, devices including tunable capacitors, and methods of making and using tunable capacitors and devices. One or more secondary tunable capacitors can be connected to a primary capacitor by printing a connector conducting layer or feature to obtain a desired net capacitance. Digitally printing the connector conducting layer allows the number of secondary capacitors connected into the circuit to be determined during the integrated circuit fabrication process, without the need for individual masks connecting the appropriate number of secondary capacitors. This provides an in-process or post-process trimming method to obtain the desired precision and accuracy for capacitors. Various sizes and combinations of secondary capacitors can be connected to obtain high precision capacitors and/or improved matching of capacitance values.

Abstract: A capacitor capable of being incorporated into a packaging substrate, which capacitor includes a high-dielectric-constant layer, and an upper electrode layer and a lower electrode layer sandwiching the high-dielectric-constant layer from the upper side and the lower side. A packaging substrate containing the capacitor, and a method for producing the same are also provided.

Abstract: A seal design provides positive compression to produce a hermetic seal around a feedthrough pin in a hermetically sealed device, including an implantable medical device. One embodiment of the seal design uses a plurality of “micro-flanges” placed along the length of a feedthrough pin, which micro-flanges grabs and compresses the insulator material to form a hermetic seal. Because the seal design produces positive compression of the insulator, the seal is relatively insensitive to changes in temperature and to differences in thermal expansion coefficients (“TCEs”) between the metal feedthrough and the insulator. It is therefore possible to use a wider variety of materials for the insulator and the feedthrough with the described sealing design, while achieving a superior hermetic seal.

Abstract: A capacitor device includes a capacitor Q constituted by a lower electrode (12) formed on a substrate (10), a dielectric film (14), and an upper electrode (16); an insulating film (18) covering the capacitor Q; a first contact hole (18a) formed in the insulating film (18) on a connection portion (16a) of the upper electrode (16); an electrode pad (20) for preventing a diffusion of solder, formed in the first contact hole (18a); and a solder bump (22) electrically connected to the electrode pad (20), and the upper electrode (16) has a protrusion portion (16a) protruding from the dielectric film (14), and is connected to the first contact hole (18a) on the protrusion portion (16a).

Abstract: A capacitor assembly for use in, and a method of assembling, a filtered feedthrough. The capacitor includes an insulative member fixedly attached to its bottom portion to inhibit high voltage arcing. The termination material present on the inner and outer diameters of the capacitor is absent from a portion of the capacitor proximate the bottom portion, e.g., at the insulative member.

Abstract: The present invention relates to a ceramic laminated device including a dielectric ceramic and an Ag electrode. In a dielectric ceramic that can be sintered at low temperatures and has a high dielectric constant and Q value, reactivity between the ceramic and Ag during sintering is suppressed low and segregation of specific elements in the proximity of the electrode is controlled. Thus, a filter having a high Q value and low loss is produced stably. For this purpose, in a ceramic laminated body including at least a ceramic and a Si-containing glass, a ratio of A/B, i.e. a ratio of a Si element concentration (A) within a range at a distance of 5 ?m or smaller from the Ag electrode to a Si element concentration (B) within a range at a distance larger than 5 ?m from the Ag electrode, is set equal to or smaller than 2.

Abstract: A method of manufacturing a metal-insulator-metal (MIM) capacitor that includes at least one of the following steps: Sequentially forming a bottom metal film, an insulating film, and a top metal film over a wafer. Forming a first pattern for etching the top metal film and the insulating film. Etching the top metal film and the insulating film, using the formed first pattern, and then stripping the first pattern. Conducting a heat treatment and a cooling split for the wafer. Forming a metal pattern for etching the bottom metal film. Etching the bottom metal film, using the formed metal pattern, and then stripping the metal pattern.

Abstract: Object The invention provides a method for manufacturing a solid electrolytic capacitor, capable of joining a bolster member interposed between an anode lead and an anode lead frame to the anode lead frame with good adhesion property and high positional accuracy. Solution A bolster member is obtained from a ladder-shaped frame. A width of the bolster member in a direction perpendicular to a lead-out direction of an anode lead is larger than a width of an anode lead frame. The bolster member is aligned with the anode lead frame while being chucked, and then is joined to the anode lead frame.

Abstract: An ionic polymer metal composite (IPMC) capacitor is disclosed which includes a thin single layer non-hydrated ionic polymer substrate with conductive film electrodes applied to at least a portion of each side of the non-hydrated ionic polymer substrate. The disclosed capacitor is suited for providing thin capacitance structures made to substantially any desired dimensions and shape and may be particularly suited for short term power storage in low power electronics, sensors, micro-electronics, MEMs and high temperature applications. A method of manufacturing an IPMC capacitor is also disclosed including providing a thin single layer non-hydrated ionic polymer substrate, applying a conductive film electrode to both sides of the substrate, and attaching electrical connections to the electrodes. The disclosed method of manufacture may optionally also include heat curing the capacitor and coating the capacitor with at least one moisture-resistant protective coating layer.

Abstract: A multi-layer ceramic capacitor has a temperature characteristic satisfying an X8R property and has a high specific resistance under a high temperature circumstance, in which the dielectric ceramic composition forming the dielectric ceramics is expressed by a formula: BaTiO3+aMgO +bMOx+cReO3/2+dSiO2, wherein MgO represents MgO conversion, MOx represents oxide conversion for 1 atom in 1 molecule of at least one metal selected from V, Cr, and Mn, ReO3/2 represents oxide conversion for 1 atom in 1 molecule of at least one rare earth metal selected from Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Y, and SiO2 represents SiO2 conversion, and wherein 0.4?a?3.0 mol, 0.05?b?0.4 mol, 6.0?c?16.5 mol, 3.0?d?5.0 mol, 2.0?c/d?3.3, based on 100 mol of BaTiO3.

Abstract: Methods of making thin film capacitors formed on foil by forming onto a thin film dielectric in a single deposition event an integrally complete top electrode having a minimum thickness of at least 1 micron.

Abstract: A multilayer ceramic capacitor 1 having dielectric layers 2 and internal electrode layers 3 formed using a conductor paste, wherein the conductor paste contains a conductive material, the conductive material is comprised of a first ingredient and second ingredient, the first ingredient includes metal elements having Ni as a main ingredient, and the second ingredient includes a metal element dissolving in the first ingredient and having a melting point of 1490° C. or more.

Abstract: High-temperature, multiple-layer polymer (MLP) capacitors with a stacked electrode arrangement are disclosed. The capacitor electrodes are separated by a polymer dielectric that is stable at high temperatures. In some embodiments, the polymer dielectric also has a high permittivity and is filled with high-permittivity nanoparticles, which enables the capacitor to achieve a very high capacitance density.

Abstract: A method for manufacturing a resonator is presented in the present application. The method includes providing a handle substrate, providing a host substrate, providing a quartz substrate comprising a first surface opposite a second surface, applying interposer film to the first surface of the quartz substrate, bonding the quartz substrate to the handle substrate wherein the interposer film is disposed between the quartz substrate and the handle substrate, thinning the second surface of the quartz substrate, removing a portion of the bonded quartz substrate to expose a portion of the interposer film, bonding the quartz substrate to the host substrate, and removing the handle substrate and the interposer film, thereby releasing the quartz substrate.

Abstract: A multilayer chip capacitor includes: a capacitor main body; a plurality of first and second inner electrodes; and m (m?3) number of first and second outer electrodes. The plurality of first and second inner electrodes are connected with two outer electrodes positioned on both opposing surfaces and having the same polarity as that of the first and second inner electrodes, and classified into a plurality of groups depending on the locations of the outer electrodes connected to the first and second inner electrodes. At least one of two outer electrodes connected with inner electrodes of each group is different from an outer electrode connected with inner electrodes of a different group having the same polarity, and inner electrodes of one group are connected to outer electrodes connected with at least another one group so that all the inner electrodes belonging to the same polarity can be electrically connected.

Abstract: Apparatus and method for providing high density component assemblies, such as electromechanical or electro-optical assemblies.

Abstract: A trimmer capacitor is provided which includes a conductive bushing having a first terminal of the capacitor formed integrally therewith, a rotor threadably engageable with the bushing, and a dielectric portion attached at one end to the bushing and having a metallized stator surrounding the dielectric portion near the opposite end thereof. The metallized stator forms the second terminal of the capacitor, and is positioned above the bottom edge of the dielectric portion. The rotor includes transverse slots which bias the rotor in position against the bushing, to prevent undesired rotation of the rotor.

Abstract: A manufacturing method includes forming a dielectric part by oxidizing an entire first surface of a valve metal sheet; forming a through hole in the valve metal sheet in which the dielectric part is formed; applying an adhesive conductive material to a surface of a substrate; attaching the valve metal sheet in which the through hole is formed, to the substrate so that the first surface contacts the conductive material on the substrate surface; forming a conductive layer by curing the conductive material; forming a protection layer which covers a second surface of the valve metal sheet which is opposite to the first surface of the valve metal sheet; forming openings in the protection layer, so that the conductive layer in the through hole and the second surface of the valve metal sheet are partially exposed from the openings; and filling up the openings in the protection layer with another conductive material to form electrode terminals.

Abstract: A dielectric ceramic represented by a general formula: 100BamTiO3+aROn+bMOv+cXOw (where R represents a rare earth element, M represents a predetermined metal element, and n, v, and w represent independently a positive number determined in accordance with the valences of the elements R and M and a sintering aid component X, respectively), and the solid solution regions of the secondary components in the main phase grains are 10% or less (including 0%) on average in terms of a cross-sectional area ratio. The sintering aid component X contains at least Si, and m, a, b, and c satisfy 0.995?m?1.030, 0.1?a?2.0, 0.1?b?3.0, and 0.1?c?5.0. In a monolithic ceramic capacitor, dielectric layers are formed from the above-described dielectric ceramic.

Abstract: In a capacitor structure and a method of manufacturing the capacitor structure, first and second conductive patterns are formed on a substrate. The first and second conductive patterns extend in a first direction. The first and second conductive patterns are alternately arranged to be spaced apart from one another in a second direction substantially perpendicular to the first direction. An insulating interlayer is formed on the substrate to cover the first and second conductive patterns. Third and fourth conductive patterns extending in a third direction lying at an angle of between about 0° and about 90° relative to the first direction are formed on the insulating interlayer. The third and fourth conductive patterns are alternately arranged to be spaced apart from one another in a fourth direction substantially perpendicular to the third direction.

Abstract: One capacitor fabrication process including metal layer forming a metal layer on one surface of a substrate, dielectric layer forming a dielectric layer on the metal layer, metal foil forming a metal foil on the dielectric layer, separating the noble metal layer from the dielectric layer, and electrode layer forming an electrode layer on the second surface of the dielectric layer, wherein the second surface faces away from the first surface of the dielectric layer with the metal foil. Another capacitor fabrication process includes separation layer forming a separation layer on one surface of a substrate, dielectric layer forming a dielectric layer on the separation layer, metal foil forming a metal foil the dielectric layer, separating the substrate from the separation layer, and an electrode layer forming an electrode layer on the second surface of the dielectric layer, wherein the second surface faces away from the first surface of said dielectric layer with the metal foil.

Abstract: A method of producing a piezoelectric actuator includes the steps of: forming a first electrode layer on a substrate by jetting an aerosol containing particles of a conductive material and ceramic particles onto the substrate to make the particles adhere to the substrate; forming a piezoelectric layer on the first electrode layer by jetting an aerosol containing particles of a piezoelectric material onto the first electrode layer to make the particles adhere to the electrode; performing an annealing treatment for the piezoelectric layer; and forming, on the piezoelectric layer, a second electrode layer paring with the first electrode layer. Accordingly, the adherence between the substrate and the first electrode layer and between the first electrode layer and the piezoelectric layer are improved, thereby hardly causing exfoliation of the layers due to differences in coefficients of thermal expansion between the layers.

Abstract: A piezoelectric thin film device includes an amorphous metal film disposed on a substrate and a piezoelectric film disposed on the amorphous metal. One of crystal axis of the piezoelectric film is aligned in a direction perpendicular to a surface of the amorphous metal.

Abstract: In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.

Abstract: An embodiment mitigates one or more of the limiting factors of fabricating polymer ferroelectric memory devices. For example, an embodiment reduces the degradation of the ferroelectric polymer due to the polymer's reaction with, and migration or diffusion of, adjacent metal electrode material. Further, the ferroelectric polymer is exposed to fewer potentially high temperature or high energy processes that may damage the polymer. An embodiment further incorporates an immobilized catalyst to improve the adhesion between adjacent layers, and particularly between the electrolessly plated electrodes and the ferroelectric polymer.

Abstract: In a method of manufacturing ceramic capacitor according to the present invention, a pair of interdigitated internal electrodes are arranged perpendicularly to the surface of the substrate, subsequent to which the respective end faces of this pair of internal electrodes are exposed, and a pair of external electrodes are formed at these exposed end faces. In this method of manufacturing ceramic capacitor, formation of the external electrodes on the end faces of the respective internal electrodes, with these internal electrodes being interdigitately integrally-formed and the end faces thereof being exposed, it possible to reliably and easily form the external electrodes.

Abstract: Devices for storing energy at a high density are described. The devices include carbon-containing extensions which increase the surface area between a dielectric material and one or both of the electrodes. The dielectric material may have a high dielectric constant (high permittivity) and a high breakdown voltage, allowing a high voltage difference between paired electrodes to effect a high stored energy density.

Abstract: A method for manufacturing a ceramic electronic component having excellent solderability is provided. In this method, the elution of barium from the ceramic electronic component and the adhesion of ceramic electronic components in tin plating are reduced. The method for manufacturing a ceramic electronic component includes the steps of providing an electronic component of barium-containing ceramic and forming an electrode on the outer surface of the electronic component, the electrode being electroplated with tin. In this method, a plating bath used in the tin plating has a tin ion concentration A in the range of 0.03 to 0.51 mol/L, a sulfate ion concentration B in the range of 0.005 to 0.31 mol/L, a molar ratio B/A of less than one, and a pH in the range of 6.1 to 10.5.

Abstract: A method of manufacturing a multilayered piezoelectric element having a multilayered structure by which an internal electrode and a side electrode are strongly connected. The method includes the steps of: forming first and second side surfaces by dicing the multilayered structure to protrude end portions of first and second electrode layers to an outer side than adjacent piezoelectric material layers and secure insulating regions between each electrode layer and respective one side surface; and forming a first side electrode on the first side surface and a second side electrode on the second side surface.

Abstract: A method for producing a dielectric film, comprising: a coating step of coating a colloidal solution containing an organometallic compound containing a metal constituting a dielectric film containing at least a lead component to form a dielectric precursor film; a drying step of drying the dielectric precursor film; a degreasing step of degreasing the dielectric precursor film; and a firing step of firing the dielectric precursor film to form a dielectric film, and wherein the drying step includes a first drying step of heating the dielectric precursor film to a temperature lower than the boiling point of a solvent, which is a main solvent of the material, and holding the dielectric precursor film at the temperature for a certain period of time to dry the dielectric precursor film, and a second drying step of drying the dielectric precursor film at a temperature in the range of 140° C., to 170° C., the degreasing step is performed at a degreasing temperature of 350° C. to 450° C.

Abstract: A capacitor is disclosed having a plurality of drawn fibers. Each of the drawn fibers has an electrically conductive fiber core and an electrically insulating cladding. The drawn fibers are arranged in a matrix bundle pattern of a first and second set of fiber cores with each fiber core of the first set being disposed adjacent to and aligned with at least one fiber core of the second set to create a capacitance between the first and second set of fiber cores. A first electrode contacts the first set of fiber cores and a second electrode contacts the second set of fiber cores so that an electric capacitance is established between the first and second sets of fiber cores and between the first and second electrodes.

Abstract: A multilayer ceramic capacitor having external electrodes. Each of the external electrodes has a lower layer resistance electrode and an upper layer conductive electrode. A glass contained in the upper layer conductive electrode has a softening point higher than that of a glass contained in the lower layer resistance electrode by 20° C. or more.

Abstract: A filtered feedthrough assembly having at least one terminal pin therethrough is provided. The feedthrough assembly comprises a ferrule having a cavity therethrough for receiving the terminal pin, and insulating structure having an upper surface. The insulating structure is disposed within the cavity and around the terminal pin for electrically isolating the pin from the ferrule. A capacitor is disposed around the pin and electrically coupled thereto. The capacitor has a lower surface that is disposed proximate the upper surface, and at least one washer is disposed between the upper surface and the lower surface. To attach the capacitor to the insulating structure, a body of epoxy is substantially confined between the upper surface and the lower surface by the ferrule, the insulating structure, the capacitor, and the at least one washer.

Abstract: A capacitor and method of fabricating a capacitor. A method of fabricating a capacitor may include forming a device isolation film on and/or over a semiconductor substrate, forming a polysilicon pattern on and/or over a device isolation film, forming a silicide on and/or over an upper portion of a polysilicon pattern, forming a capacitor insulating film covering a silicide, forming a pre-metal-dielectric (PMD) on and/or over a semiconductor substrate having a capacitor insulating film, and/or forming an upper metal electrode on and/or over a hole on and/or over a PMD, which may expose an insulating film opposite a region of a silicide.

Abstract: A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.

Abstract: A plurality of thin film capacitor parts are provided in respective regions each surrounded by a plurality of gate metal lines (12) and a plurality of data signal lines (11) intersecting perpendicularly to each other on a glass substrate (1), and each of the thin film capacitor parts has a lower electrode (3), a gate insulating film, and an upper electrode (5), which are provided in this order. Adjacent upper electrodes (5) are electrically connected to each other via a corresponding first wire (8), which is positioned above the adjacent upper electrodes (5) and intersects with one of the data signal lines (11). This makes it possible to provide a thin film capacitor, which includes the lower electrodes (3) each having the same thickness in a center portion and an edge portion, and the upper electrodes (5) that are connected to each other by using a corresponding connecting wire with low possibility of disconnection.

Abstract: A method for manufacturing a capacitor embedded in a PCB includes: preparing a copper clad lamination (CCL) substrate having a reinforcement member and copper foils formed on both surfaces of the reinforcement member; planarizing surfaces of the copper foils of the CCL substrate; forming a dielectric layer on the planarized surface of the copper foils; and forming a top electrode on the dielectric layer.

Abstract: A method for forming a capacitor dielectric includes depositing a zirconium oxide layer, performing a post-treatment on the zirconium oxide layer such that the zirconium oxide layer has a tetragonal phase, and depositing a tantalum oxide layer over the zirconium oxide layer such that the tantalum oxide layer has a tetragonal phase.

Abstract: A method of manufacturing a component-embedded printed circuit board is disclosed. The method includes: forming a blind hole in the first metal layer such that the first insulation layer is exposed, for a metal-clad laminate that includes a first metal layer stacked over a first insulation layer, securing a component to the first insulation layer by embedding the component in the blind hole, stacking a second insulation layer and a second metal layer on either side of the metal-clad laminate, and forming circuit patterns by removing portions of the metal layers.

Abstract: A discoidal feedthrough capacitor has its active electrode plates disposed within a dielectric body so that an edge of the active electrode plates is exposed at a surface of a through-hole for a conductive lead. The conductive lead is conductively coupled to the exposed edge of the electrode plates without an intervening conductive termination surface. Similarly, a ground electrode plate set of the feedthrough capacitor may have an edge exposed at the outer periphery of the capacitor for conductively coupling the exposed edge of the ground electrode plate to a conductive ferrule without an intervening conductive termination surface.