Abstract: The use of electrical energy storage unit (EESU) technology can provide power averaging for utility grids. Such EESUs can also be used to construct a system capable of storing electrical energy over specified periods (e.g., 24 hours) to provide peak power to homes, commercial sites, and industrial sites. By charging these power averaging units during non-peak times and then delivering the energy during peak-demands times, more efficient utilization of the present utility-grid power-generating plants and the already existing power transmission lines will be accomplished. These systems also have the capability of isolating users from utility-grid power failures, transients, and AC noise.

Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.

Abstract: A capacitive ultrasonic transducer includes a flexible layer, a first conductive layer on the flexible layer, a support frame on the first conductive layer, the support frame including a flexible material, a membrane over the support frame being spaced apart from the first conductive layer by the support frame, the membrane including the flexible material, a cavity defined by the first conductive layer, the support frame and the membrane, and a second conductive layer on the membrane.

Abstract: The present invention relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.

Abstract: A method for manufacturing a laminated electronic component is performed such that a water-repellent agent is applied to end surfaces at which ends of internal electrodes are exposed so as to be filled in spaces along interfaces between insulating layers and the internal electrodes. Subsequently, an abrading step is performed such that the internal electrodes are sufficiently exposed at the end surfaces and an excess water-repellent agent is removed therefrom to enable plating films to be directly formed on the end surfaces.

Abstract: A method for manufacturing a piezoelectric element includes the steps of forming a first electrode above a substrate, forming above the first electrode a piezoelectric layer composed of a piezoelectric material having a perovskite structure, and forming a second electrode above the piezoelectric layer, wherein the step of forming the first electrode includes forming a lanthanum nickelate layer that is oriented to a cubic (100) by a sputter method, and a ratio of nickel to lanthanum (Ni/La) in a target used for the sputter method is greater than 1 but smaller than 1.5.

Abstract: The invention provides a multilayer ceramic capacitor comprising a capacitor body composed by alternately layering dielectric layers and inner electrode layers. Accordingly, the multilayer ceramic capacitor has high relative permittivity and is high the temperature property and highly accelerated life test property.

Abstract: A method of manufacturing a capacitor-embedded low temperature co-fired ceramic substrate. A capacitor part is manufactured by firing a deposition including at least one high dielectric ceramic sheet to form a capacitor part. A plurality of low temperature co-fired green sheets are provided. Each of the low temperature co-fired green sheet has at least one of a conductive pattern and a conductive via hole thereon. A low temperature co-fired ceramic deposition is formed by depositing the low temperature co-fired green sheets to embed the capacitor part in the low temperature co-fired ceramic deposition. The embedded capacitor part is connected either to the conductive pattern or the conductive via hole of an adjacent green sheet. Then the low temperature co-fired ceramic deposition having the capacitor part embedded therein is fired.

Abstract: A method of producing a multilayer capacitor has a step of preparing a plurality of first ceramic green sheets, a step of preparing a plurality of second ceramic green sheets, a step of laminating the plurality of first and second ceramic green sheets, and a step of cutting a ceramic green sheet laminate body along predetermined intended cutting lines to obtain laminate chips of individual multilayer capacitor units. In the step of preparing the first ceramic green sheets, first and second internal electrode patterns are formed so that the first and second internal electrode patterns are alternately arranged in a predetermined direction and in a direction perpendicular to the predetermined direction and so that portions corresponding to lead portions of first and second internal electrodes in the first and second internal electrode patterns are continuous across the predetermined intended cutting line.

Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.

Abstract: A method is used to manufacture a multilayer electronic component including a multilayer composite including internal electrodes having ends that are exposed at a predetermined surface of the multilayer composite. In the method, the exposed ends of the internal electrodes are coated with a metal film primarily composed of at least one metal selected from the group consisting of Pd, Au, Pt and Ag and having a thickness of at least about 0.1 ?m by immersing the multilayer composite in a liquid containing a metal ion or a metal complex. Then, a continuous plating layer is formed by depositing a plating metal on the ends of the internal electrodes exposed at the predetermined surface of the multilayer composite, and subsequently growing the deposits of the plating metal so as to be connected to each other. Thus, exposed ends of the internal electrodes are electrically connected to each other.

Abstract: A mirror for a piezoelectric resonator consisting of alternately arranged layers of high and low acoustic impedance is manufactured by at first producing a first layer on which a second layer is produced, so that the second layer partially covers the first layer. Then, a planarization layer is applied on the first layer and on the second layer. Subsequently, a portion of the second layer is exposed by structuring the planarization layer, wherein the portion is associated with an active region of the piezoelectric resonator. Finally, the resulting structure is planarized by removing the portions of the planarization layer remaining outside the portion.

Abstract: To provide a method for manufacturing a quartz piece which can suppress the deterioration of the CI and the temperature characteristic failure by forming the end surface of the quartz piece perpendicularly. A method for manufacturing a quartz piece that has a shape having two sides facing each other from a quartz substrate, includes the steps of: forming an etching mask provided with an opening area for forming the outside shape along one side out of the two sides which face each other, and provided with no opening area on the other side out of the two sides facing each other, on one surface side of the quartz substrate; and forming an etching mask provided with an opening area for forming an outside shape along the other side out of the two sides which face each other, and provided with no opening area on the one side, on the other surface side of the quartz substrate.

Abstract: A method of manufacturing a chip capacitor according to an aspect of the invention may include: preparing a capacitor lamination including a dielectric sheet formed of a composite having ceramic powder and a polymer mixed with each other, and first and second internal electrodes formed on both surfaces of the dielectric sheet at predetermined intervals; forming covering layers formed of an insulating material on both surfaces of the capacitor lamination; forming at least one first opening and at least one second opening in the capacitor lamination having the covering layers formed thereon to expose the first and second internal electrodes, respectively; forming plating layers in the first and second openings, the plating layers connected to the first and second internal electrodes; and dicing the result into chips on the basis of the first and second openings so that the plating layers formed in the first and second openings are provided as first and second external terminals.

Abstract: Methods of making metal/dielectric/metal structures include casting copper slurry onto a fugitive substrate to form the first electrode and subsequently casting dielectric and copper slurries onto the first electrode, removing the fugitive substrate and co-firing the structure, wherein the dielectric comprises glass in an amount that is less than 20% by weight of the total inorganic composition and the dielectric achieves substantially complete densification. Alternatively, a metal tape and a dielectric tape, comprising glass in the above amount, may be formed and laminated together to form a metal/dielectric/metal green tape structure, which is co-fired, such that the structure achieves substantially complete densification.

Abstract: A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.

Abstract: Disclosed are methods of making a dielectric on a metal foil, and a method of making a large area capacitor that includes a dielectric on a metal foil. A first dielectric layer is formed over the metal foil by physical vapor deposition, and a dielectric precursor layer is formed over the first dielectric layer by chemical solution deposition. The metal foil, first dielectric layer and dielectric precursor layer are prefired at a prefiring temperature in the range of 350 to 650° C. The prefired dielectric precursor layer, the first dielectric layer and the base metal foil are subsequently fired at a firing temperature in the range of 700 to 1200° C.

Abstract: A ceramic electronic component that is hardly influenced by a stress generated when an external electrode containing a metal sintered compact is formed at the end of the ceramic component body, and a method for manufacturing the same are provided. A laminated ceramic capacitor includes a ceramic component body and first electrodes to be connected to internal electrodes that are led to the end surfaces are formed. The first external electrodes are arranged so that the ends are spaced apart from the side surfaces of the ceramic component body. Second external electrodes containing a conductive resin are arranged so as to entirely cover the first electrodes and first and second metal layers and are formed thereon. The first external electrodes are formed by supplying a conductive paste containing conductive metal powder and glass frit having a softening point higher than the sintering starting temperature of the conductive metal powder, and heating the same.

Abstract: In an exemplary embodiment, a method for a magnetic sensor includes forming a first conductive layer over a substrate containing circuitry, forming a dielectric layer over the first conductive layer, forming a second conductive layer over the dielectric layer such that the first conductive layer, the dielectric layer, and the second conductive layer form a first capacitor, and providing first and second terminals, wherein the first terminal is coupled to the first conductive layer and the second terminal is coupled to the second conductive layer.

Abstract: A method of manufacturing a printed circuit board including embedded capacitors, composed of a polymer condenser laminate including a plurality of polymer condenser layers, each of which has a polymer sheet and a conductor pattern formed on the polymer sheet, and a via hole for interlayer connection therethrough, and a circuit layer formed on either surface or both surfaces of the polymer condenser laminate and having a circuit pattern and a via hole for interlayer connection therethrough. The printed circuit board manufactured by the method of the current invention has higher capacitance density per unit area than conventional embedded capacitor printed circuit boards, whereby capacitors having various capacitance values, such as multilayered ceramic capacitors having high capacitance, can be embedded in the printed circuit board, instead of being mounted thereon.

Abstract: A method of fabricating a polymer-based capacitive ultrasonic transducer, which comprises the steps of: (a) providing a substrate; (b) forming a first conductor on the substrate; (c) coating a sacrificial layer on the substrate while covering the first conductor by the same; (d) etching the sacrificial layer for forming an island while maintaining the island to contact with the first conductor; (e) coating a first polymer-based material on the substrate while covering the island by the same; (f) forming a second conductor on the first polymer-based material; (g) forming a via hole on the first polymer-based material while enabling the via hole to be channeled to the island; and (h) utilizing the via hole to etch and remove the island for forming a cavity.

Abstract: A semiconductor device and a method of fabricating the same include an electrode having a nickel layer with impurities. The electrode having a nickel layer with impurities can be a gate electrode or a capacitor electrode. The electrode having a nickel layer with impurities may include a combination of a pure nickel layer and a nickel layer with impurities.

Abstract: A method for forming a decouple capacitor of an integrated circuit, the integrated circuit including a core circuit and a plurality of I/O circuits coupled to the core circuit, includes cutting part of a plurality of lines in at least one specific circuit of the I/O circuits to form decouple capacitors of the integrated circuit.

Abstract: Provided is a method of manufacturing a multi-frequency surface acoustic wave (SAW) device on a common piezoelectric substrate. The method features varying the resonant frequency of waveguide elements of the SAW device using a single etch step. The etch step removes a sub-portion of multiple layers of conductive film disposed on the substrate.

Abstract: Disclosed are apparatus and methodology for inexpensive realization of one or more secondary capacitors within a monolithic body that already includes a first, larger capacitor to provide ultra wideband structures. Alternating layers of electrodes are provided with arm portions that embrace portions of adjacent electrode layers so as to create additional coupling effects within the capacitor structure thereby producing multiple additional equivalent capacitor structures within the device.

Abstract: A multilayer ceramic capacitor component includes a ceramic capacitor body having opposite ends and comprised of a plurality of electrode layers and dielectric layers, first and second external terminals attached to the ceramic capacitor body. The plurality of electrode layers include a plurality of alternating layers of active electrodes extending inwardly from alternating ends of the ceramic capacitor body. The capacitor may include a plurality of side shields disposed within the plurality of alternating layers of active electrodes to provide shielding with the alternating layers of active electrodes having a pattern to increase overlap area to provide higher capacitance without decreasing separation between the alternative layers of active electrodes. The capacitor may have a voltage breakdown of 3500 volts DC or more in air. The capacitor may have a coating. The capacitor provides improved resistance to arc-over, high voltage breakdown in air, and allows for small case size.

Abstract: The present invention relates to a process for the manufacture of capacitors on metal foil using chemical solution deposition of a barium/titanium precursor formulation. The metal foil substrate is annealed and subsequently polished prior to the precursor formulation deposition in order to obtain a desirable process yield of capacitors without short circuits across the dielectric.

Abstract: Disclosed is a method for manufacturing a solid electrolytic capacitor in which a capacitor element has conductive polymer solid electrolyte on a dielectric oxide film layer. The method includes the following processes: forming a manganese oxide layer on the dielectric oxide film layer; and chemically polymerizing a reaction solution containing a monomer, aromatic sulfonic acid, and a solvent using the manganese oxide layer as an oxidizing agent. Here, polyhydric alcohol capable of being coordinated to manganese ions released from the manganese oxide layer is made to coexist with the chemical polymerization reaction.

Abstract: A production method of a multilayer electronic device, comprising the steps of forming an electrode layer 12a on a first support sheet 20; forming a green sheet 10a on a surface of the electrode layer 12a to obtain a green sheet 10a having an electrode layer 12a; stacking the green sheets 10a, each having the electrode layer 12a, to form a green chip; and firing the green chip: wherein before stacking the green sheet 10a having the electrode layer 12a, an adhesive layer 28 is formed on a surface on the opposite side of the electrode layer side of the green sheet 10a having the electrode layer 12a; and the green sheet 10a having the electrode layer 12a formed thereon is stacked via the adhesive layer 28.

Abstract: An exemplary embodiment providing one or more improvements includes a capacitor with a segmented end electrode and methods for segmenting an end electrode of a capacitor for reducing or eliminating instances of thermally induced damage of the capacitor.

Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, and cause a short-circuit. The inner conductor is printed in such a manner that the center of each of the via conductors is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability that the inner conductor contact the via conductor and cause a short-circuit is minimized.

Abstract: A method for producing a multilayer ceramic electronic component includes a plating step including depositing a plating material on the ends of internal electrodes exposed at a predetermined surface of a laminate to form plating deposits primarily composed of a specific metal and growing the plating deposits so as to connect the plating deposits to each other to form a continuous plated layer. The specific metal primarily defining the plated layer is different from a metal defining the internal electrodes. The same or substantially the same metal as the metal defining the internal electrodes is present throughout the plated layer.

Abstract: A capacitance arrangement comprising at least one parallel-plate capacitor comprising a first electrode means, a dielectric layer and a second electrode means partly overlapping each other. A misalignment limit is given. Said first electrode means comprises a first and a second electrode arranged symmetrically with respect to a longitudinal axis, said first and second electrodes have a respective first edge, which face each other, are linear and parallel such that a gap is defined there between. Said second electrode means comprises a third electrode with a first section and a second section disposed on opposite sides of said gap interconnected by means of an intermediate section, which is delimited by a function depending on a first parameter and a second parameter. One of said two parameters is adapted to be selected hence allowing calculation of the other parameter to determine the shape and size of the second electrode means.

Abstract: A lower electrode 3 including a low-temperature melting layer 3A and a high-temperature melting layer 3B having mutually different melting-start temperatures is provided between a vibration plate 2 and a piezoelectric layer 4. In a calcination step of calcinating the lower electrode 3, the calcination is performed at a low temperature at which only the low-temperature melting layer 3A melts, and in an annealing-process step of the piezoelectric layer 4, the annealing process is performed at a high temperature at which the high-temperature melting layer 3B melts. At this time, in the calcination step, the melting of platinum nano-particles occurs in the low-temperature melting layer 3A, rendering the adhesion and diffusion-preventive effect. Further, in the annealing step, in the high-temperature melting layer 3B, platinum particles are melted, rendering the adhesion and diffusion-preventive effect.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first and second inner electrodes are laminated alternately, and first and second terminal electrodes arranged on the multilayer body. The first terminal electrode is electrically connected to the first inner electrodes. The first terminal electrode includes one or a plurality of resistance layers having a resistivity greater than that of the first inner electrode. The one or a plurality of resistance layers cover end portions of lead portions of the first inner electrodes exposed at the side face. Each resistance layer has a width wider than the lead portion of the first inner electrode but narrower than the width of the side face formed with the first terminal electrode.

Abstract: A method for manufacturing a multilayer chip capacitor includes: forming screen patterns on mother green sheets such that a widthwise margin is not formed on the mother green sheets, the screen patterns are spaced apart from each other in the width direction and the longitudinal direction, and a width of each screen pattern is greater than a spacing between the adjacent screen patterns; forming internal electrode patterns on the mother green sheets; forming a stack of the mother green sheets; forming a capacitor body having internal electrodes by cutting the stack of the mother green sheets along cutting lines arranged in the width direction and the longitudinal direction; forming chip-protecting side members on both sides of the capacitor body such that the chip-protecting side members contact both sides of the internal electrodes, respectively; and forming a pair of terminal electrodes on the outer surface of the capacitor body.

Abstract: Method for producing parts for passive electronic components according to which: a laminated strip (1) is produced which is constituted by at least one stack of a thin metal strip and a layer of adhesive material, and at least one part (6) is cut from the laminated strip (1), the cutting operation being carried out using a method which comprises at least one step for etching by means of sandblasting. Parts produced.

Abstract: A single layer capacitive device including a portion of pre-fired ceramic material and one or more terminations is formed with manufacturing steps that are easily modified to customize size and other aspects of such devices. The single layer devices may be utilized by themselves or selectively combined with MLCs to form integrated capacitor assemblies yielding many desirable performance characteristics in a monolithic assembly. An exemplary integrated capacitor assembly advantageously provides customized frequency response and capacitance in limited real estate. Predictable and generally constant or “flat” impedance versus frequency is afforded mainly by the properties of the single layer device, while higher capacitance is provided mainly from features of one or more associated MLCs. High structural integrity of exemplary integrated capacitor assemblies is achieved due to the disclosed attachment methods.

Abstract: The present invention provides an electronic device with improved characteristics and a method of making the electronic device. In a method of making an electronic device (piezoelectric device) 74 according to the present invention, an outer edge R1 of a piezoelectric film 52A formed on an electrode film 46A of a laminate 60 is located inside an outer edge R2 of the electrode film 46A. For this reason, in removal of a monocrystalline Si substrate 14 from a multilayer board 61, where an etching solution permeates between polyimide 72 and laminate 60, the etching solution circumvents the electrode film 46A before it reaches the piezoelectric film 52A. Namely, a route A of the etching solution to the piezoelectric film 52A is significantly extended by the electrode film 46A. In the method of making the electronic device 74, therefore, the etching solution is less likely to reach the piezoelectric film 52A.

Abstract: A multilayer ceramic electronic component includes a ceramic body including a plurality of ceramic layers, the ceramic body having a first main surface and a second main surface and a plurality of side surfaces that connect the first main surface to the second main surface, an internal conductor including nickel, the internal conductor being disposed in the ceramic body and having an exposed portion exposed at least one of the side surfaces, and an external terminal electrode disposed on at least one of the side surfaces of the ceramic body, the external terminal electrode being electrically connected to the internal conductor. The external terminal electrode includes a first conductive layer including a Sn—Cu—Ni intermetallic compound, the first conductive layer covering the exposed portion of the internal conductor at least one of the side surfaces of the ceramic body.

Abstract: A multilayer electronic component includes a ceramic body including ceramic layers that are laminated to one another and internal conductors having exposed portions at side surfaces of the ceramic body. Substantially linear connection portions extend in the lamination direction of the ceramic layers so as to connect the exposed portions to one another. External terminal electrodes cover the exposed portions of the internal conductors and the connection portions and include base plating films directly disposed on the side surfaces by plating. The connection portions are formed by polishing the side surfaces in which the internal conductors are exposed using, for example, a brush so as to elongate the exposed portions of the internal conductors.

Abstract: A multilayer ceramic electronic component includes external terminal electrodes that are formed by direct plating on the first and second side surfaces of a ceramic body including stacked ceramic layers and inner conductors. The external terminal electrodes include base plating films formed so as to cover the exposed portions of inner conductors. Voids are provided that are open to the side surfaces of the ceramic body so as to be adjacent to the ends in the width direction of the exposed portions of the inner conductors. A plating metal defining the base plating films enters the voids and is electrically connected to the inner conductors in the ceramic body.

Abstract: A monolithic ceramic electronic component includes a laminate including a plurality of stacked ceramic layers and a plurality of internal electrodes extending between the ceramic layers and also includes external electrodes disposed on the laminate. The internal electrodes are partly exposed at surfaces of the laminate and are electrically connected to each other with the external electrodes. The external electrodes include first plating layers and second plating layers. The first plating layers are in direct contact with the internal electrodes. The second plating layers are located outside the first plating layers and contain glass particles dispersed therein.

Abstract: A ceramic electronic component includes a ceramic body and a plurality of external electrodes disposed at a surface of the ceramic body. The external electrodes include a plating layer containing glass particles each coated with a metal film. The plating layer is formed by co-deposition of a plating metal and the metal-coated glass particles.

Abstract: An inertial sensor includes a mesoscaled disc resonator comprised of micro-machined substantially thermally non-conductive wafer with low coefficient of thermal expansion for sensing substantially in-plane vibration, a rigid support coupled to the resonator at a central mounting point of the resonator, at least one excitation electrode within an interior of the resonator to excite internal in-plane vibration of the resonator, and at least one sensing electrode within the interior of the resonator for sensing the internal in-plane vibration of the resonator. The inertial sensor is fabricated by etching a baseplate, bonding the substantially thermally non-conductive wafer to the etched baseplate, through-etching the wafer using deep reactive ion etching to form the resonator, depositing a thin conductive film on the through-etched wafer.

Abstract: The mica capacitor and fabrication method there for, resulting in parallely stacking basic laminates in which an electrode sheet is arranged between parallely stacked mica sheets to protrude in a zigzag manner, arranging an insulation plate in which the basic laminates are parallely stacked where the insulation plate protruding in a zigzag manner is formed between the basic laminates, and filling a conductor between insulation protrusions, whereby a parallel connection is implemented on the basic laminates themselves while a serial connection is implemented between the basic laminates, thereby enabling a provision of mica capacitor having a high voltage property.

Abstract: A multilayer ceramic capacitor having external electrodes. Each of the external electrodes has a lower layer resistance electrode and an upper layer conductive electrode. A glass contained in the upper layer conductive electrode has a softening point higher than that of a glass contained in the lower layer resistance electrode by 20° C. or more.

Abstract: A method of manufacturing a sensor for in vivo applications includes the steps of providing two wafers of an electrically insulating material. A recess is formed in the first wafer, and a capacitor plate is formed in the recess of the first wafer. A second capacitor plate is formed in a corresponding region of the second wafer, and the two wafers are affixed to one another such that the first and second capacitor plates are arranged in parallel, spaced-apart relation.

Abstract: A collective component has a first region that intersects a conductive paste film for external terminal electrodes in a break line in which break leading holes are arranged and a second region that does not intersect a conductive paste film for external terminal electrodes in the break line. The first break leading holes are formed in the first region so as not to reach the second region. The second break leading holes are formed only in the second region or from the second region to a portion of the first region. The pitch of the first break leading holes is wider than the pitch of the second break leading holes.

Abstract: A digital variable capacitor package is provided as having a ground plane disposed on predetermined portion of the top surface of a substrate. An elongated signal electrode may also be disposed on the substrate and including a first end defining an input and a second end extending to a substantially central region of the top surface of the substrate. This elongated signal electrode is disposed to be electrically isolated from the ground plane. A number of elongated cantilevers are disposed on the substrate and each include first ends coupled to the second end of the signal electrode and each further include second ends suspended over different predetermined portions of the ground plane. In operation, one or more of the cantilevers may be actuated to move portion thereof into close proximity to the ground plane for providing one or more discrete capacitance values.