Assembling Formed Circuit To Base Patents (Class 29/831)
  • Patent number: 8997346
    Abstract: In order to avoid cost for accommodating a shield wire in a housing while bending, and smoothly and readily accommodate within the housing while the shield electric wire is insulated, a conductive housing 1 including a rear wall 4 continuing to an annular wall 3, and a tube wall 5 continuing to down the rear wall 4, a method comprising the steps of: passing through a shield electric wire 2 from a lower opening 5a of the tube wall of the conductive housing to a front opening 3a of the annular wall while bending the shield electric wire; putting a shield terminal 9 movably around the shield electric wire from top of the shield electric wire; exposing a core wire 2b and a braid 2a of the shield electric wire by stripping a tip thereof; connecting an L-shaped terminal 11 to the core wire; mounting an L-shaped insulation inner housing 12 outside the L-shaped terminal; connecting the shield terminal to the braid; and accommodating a vertical part 14 of the inner housing within the conductive housing by pulling in t
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: April 7, 2015
    Assignee: Yazaki Corporation
    Inventors: Takashi Omae, Kazuki Zaitsu
  • Publication number: 20150092378
    Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.
    Type: Application
    Filed: September 28, 2013
    Publication date: April 2, 2015
    Inventors: Mihir K. ROY, Mathew J. MANUSHAROW
  • Patent number: 8991040
    Abstract: A reusable electronic circuit assembling system facilitates assembly and testing of electronic circuits. The system has at least one baseboard and one or more assembling blocks magnetically or mechanically attached to the baseboard. Each assembling block has at least two electrically connected conductive clips located separately in the opening holes of the assembly block. Discrete electronic components are connected by selectively inserting the electrodes of the to-be-connected electronic components into the clips of the assembling blocks. A complete circuit is constructed by attaching the above block-component assemblies on the baseboard and connecting them in accordance with the desired circuit diagram.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: March 31, 2015
    Assignee: 5eTek, LLC
    Inventor: Erli Chen
  • Patent number: 8984748
    Abstract: A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: March 24, 2015
    Assignee: Hsio Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 8978244
    Abstract: A method for manufacturing a printed circuit board with cavity includes following steps. First, a first substrate is provided. The first substrate includes a first electrically conductive layer defining an exposed portion and a laminating portion. Second, a second substrate is provided. The second substrate includes an unwanted portion corresponding to the exposed portion and a preserving portion. Third, a first annular bump surrounding the exposed portion is formed. Fourth, a second annular bump surrounding the unwanted portion is formed. Fifth, a first adhesive layer defining an opening is provided. Sixth, the first and second substrates are laminated to the first adhesive layer, the exposed portion and the unwanted portion are exposed in the opening, and the second annular bump is in contact with the first annular bump. Seventh, the unwanted portion is removed and a cavity is defined, the exposed portion is exposed in the cavity.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 17, 2015
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventors: Xue-Jun Cai, Zhi-Yong Li, Chao Liu
  • Patent number: 8978217
    Abstract: A package manufacturing method where a base substrate and a lid substrate, at least one having a through-hole, are anodically bonded to each other using a jig having a communication-hole and arranged in a vacuum chamber to laminate the lid substrate to the base substrate and thereby form a bonded body having a plurality of cavities, each of which includes an electronic part sealed therein. The through-hole and the communication-hole are aligned with each other inside the vacuum chamber, such that gas within the cavities can escape through the through-hole and the communication-hole during bonding. A plurality of packages are formed by cutting the bonded body for every one of the plurality of cavities.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 17, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Takeshi Sugiyama
  • Patent number: 8973258
    Abstract: A manufacturing method of substrate structure is provided. A base material having a core layer, a first patterned copper layer, a second patterned copper layer and at least one conductive via is provided. The first and second patterned copper layers are respectively located on a first surface and a second surface of the core layer. The conductive via passes through the core layer and connects the first and second patterned copper layers. A first and a second solder mask layers are respectively formed on the first and second surfaces. Portions of the first and second patterned copper layers are exposed by the first and second solder mask layers, respectively. A first gold layer is formed on the first and second patterned copper layers exposed by the first and second solder mask layers. A nickel layer and a second gold layer are successively formed on the first gold layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 10, 2015
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Ching-Sheng Chen
  • Patent number: 8973261
    Abstract: A manufacturing method of an object having a conductive line includes the following steps. A hardening layer and a conductive line layer are formed in an in-mold roller (IMR) material in sequence. The conductive line layer is formed on a non-conductive substrate by an IMR process. A carrier sheet is then separated to expose the hardening layer. A connecting piece is formed on the hardening layer. The connecting piece runs through the hardening layer by a connection process, and the connecting piece is electrically connected to the conductive line layer. Therefore, an object structure having the conductive line is formed.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: March 10, 2015
    Assignee: Getac Technology Corporation
    Inventor: Cheng-Hung Chiang
  • Publication number: 20150060127
    Abstract: A combined printed wiring board includes a multilayer printed wiring board, and a wiring film fixed to a surface of the multilayer printed wiring board and including a first wiring structure formed to connect multiple semiconductor elements and a second wiring structure formed to connect the multilayer printed wiring board and each of the semiconductor elements.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Makoto Terui, Takashi Kariya, Yoshinori Shizuno, Masatoshi Kunieda
  • Publication number: 20150060124
    Abstract: A combined printed wiring board includes a multilayer printed wiring board having an outermost insulation layer, and a wiring film fixed to a portion of the outermost insulation layer of the multilayer printed wiring board. The wiring film includes dense-pitch pads formed on a semiconductor-mounting surface of the wiring film, the multilayer printed wiring board has sparse-pitch pads formed on a semiconductor-mounting surface of the multilayer printed wiring board, the dense-pitch pads are formed to facilitate electrical connection between a first semiconductor element and a second semiconductor element, and the sparse-pitch pads are formed to facilitate electrical connection between the multilayer printed wiring board and the first semiconductor element and/or the second semiconductor element.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Makoto TERUI, Takashi KARIYA, Yoshinori SHIZUNO, Masatoshi KUNIEDA
  • Publication number: 20150062832
    Abstract: A method and apparatus provides an Intelligent Electronic Device (IED) with new hardware modules. Hardware modules are provided that are configured for electrically connecting with connections of a first IED housing that has a first form factor. A second IED housing is provided having a second form factor that is different from the first form factor. The hardware modules are mounted in the second housing. Adaptor structure is employed to electrically connect the hardware modules with connections of the second housing. The second housing is mounted into an existing wiring and second form factor environment.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: ABB Technology AG
    Inventors: Shamsi Ismayilov, Yaser A. Khalifa, Frantisek Koudelka, Arkady Oksengorn, Siu Lau, Hardik Patel, In Y. Choi
  • Publication number: 20150062836
    Abstract: The present disclosure relates to a stacked package of a voltage regulator and a method for fabricating the same.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 5, 2015
    Inventor: Wei Chen
  • Patent number: 8966748
    Abstract: The invention relates to a method for manufacturing an arrangement with a component on a carrier substrate, wherein the method encompasses the following steps: Manufacturing spacer elements on the rear side of a cover substrate, arranging a component on a cover surface of a carrier substrate, and arranging the spacer elements formed on the carrier substrate so as to situate the component in the at least one hollow space and close the latter. In addition, the invention relates to an arrangement, a method for manufacturing a semi-finished product for a component arrangement, as well as a semi-finished product for a component arrangement.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 3, 2015
    Assignee: MSG Lithoglas AG
    Inventors: Jürgen Leib, Simon Maus, Ulli Hansen
  • Patent number: 8966731
    Abstract: A method for manufacturing a switching element which has enough resistance to repeat switching operations and which can be miniaturized and have low power consumption, and a display device including the switching element are provided. The switching element includes a first electrode to which a constant potential is applied, a second electrode adjacent to the first electrode, and a third electrode over the first electrode with a spacer layer formed of a piezoelectric material interposed therebetween and provided across the second electrode such that there is a gap between the second electrode and the third electrode. A potential which is different from or approximately the same as a potential of the first electrode is applied to the third electrode to expand and contract the spacer layer, so that a contact state or a noncontact state between the second electrode and the third electrode can be selected.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Honda
  • Patent number: 8959760
    Abstract: A method for manufacturing a printed wiring board, including providing a support board having a metal foil secured to the support board, forming a resin insulation layer on the metal foil, forming openings in the resin insulation layer, forming a conductive circuit on the resin insulation layer, forming in the openings via conductors to electrically connect the conductive circuit and the metal foil, separating the support board and the metal foil, and forming from the metal foil external terminals to electrically connect to another substrate or electronic component.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: February 24, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Ayao Niki, Kazuhisa Kitajima
  • Patent number: 8959756
    Abstract: A method of manufacturing a core substrate having an electronic component, including providing a core substrate having a first surface and a second surface on an opposite side of the first surface, forming a through hole extending from the first surface to the second surface in the core substrate, attaching an adhesive tape to the second surface of the core substrate such that the through hole formed in the core substrate is closed on the second surface, attaching an electronic component to the adhesive tape inside the through hole, filling the through hole with a filler, and removing the adhesive tape from the second surface of the core substrate.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: February 24, 2015
    Assignee: IBIDEN Co., Ltd.
    Inventors: Hajime Sakamoto, Dongdong Wang
  • Patent number: 8959734
    Abstract: An interactive card or the like employs a piezoelectric charge generator (piezo-strip) for temporarily driving an indicator. The piezo-strip may be displaced (bent) in order to generate charge to drive the indicator. Printed electronic processes are utilized to produce the indicator and/or the piezoelectric charge generator. An indicator is formed on a substrate by way of a printed electronics process. A displaceable region of piezoelectric material associated with the said substrate is formed by way of a printed electronics process. Electrical interconnections are formed on said substrate by way of a printed electronics process. The electrical interconnections connecting said indicator and said first region of piezoelectric material such that displacement of said first region of piezoelectric material generates a voltage therein that is provided to said indicator in order to actuate said indicator and thereby indicate the displacement of said first region of piezoelectric material.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 24, 2015
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jurgen H. Daniel, Tse Nga Ng
  • Publication number: 20150048154
    Abstract: A device includes a device casing and a water-soluble circuit located within the device casing. An identification code is encoded on the circuit. The identification code is associated with the device.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Travis R. Hebig, Joseph Kuczynski, Steven R. Nickel
  • Patent number: 8955219
    Abstract: The invention relates to a method for fabricating a bond by providing a body including a metallic surface provided with an inorganic, dielectric protective layer. The protective layer covers at least one surface zone of the metallic surface in which the metallic surface is to be electrically conductive bonded to a contact conductor. To fabricate the bond, a portion of a provided contact conductor above the surface zone is pressed on to the protective layer and the body so that the protective layer is destroyed above the surface zone in achieving an electrically conductive bond between the metallic surface and the contact conductor.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies AG
    Inventors: Roman Roth, Dirk Siepe
  • Patent number: 8951379
    Abstract: In the tape attaching method of cutting a tape member into conductive tape pieces and attaching the conductive tape pieces onto a plurality of attachment regions which are formed at a side edge part of a board, an attaching step in which the conductive tape pieces is attached onto the attachment region of a first press position, and a moving step, in which by driving a tape sending mechanism to perform the operation of sending the tape member while a press bonding head and a peeling unit are integrally moved relative to the board, the press bonding head is aligned with the attachment region of a second press position, and a separator is peeled from the tape member attached onto the first press position by the peeling unit during the relative movement, are repeated.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: February 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Shingo Yamada
  • Publication number: 20150033554
    Abstract: Apparatus and methods for an electronic package incorporating shielding against emissions of electromagnetic interference (EMI). According to an integrated circuit structure, a substrate is on a printed circuit board. An integrated circuit chip is on the substrate. The integrated circuit chip is electrically connected to the substrate. An EMI shielding unit is on the integrated circuit chip and the substrate. The EMI shielding unit comprises a lid covering the integrated circuit chip and portions of the substrate outside the integrated circuit chip. A fill material can be deposited within a cavity formed between the lid and the substrate. The fill material comprises an EMI absorbing material. A periphery of the lid comprises a side skirt, the side skirt circumscribing the integrated circuit chip and the substrate. EMI absorbing material is on the printed circuit board, and a portion of the side skirt is embedded in the EMI absorbing material.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: William L. Brodsky, Timothy W. Budell, Samuel R. Connor, Mark Curtis Hayes Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone
  • Publication number: 20150033553
    Abstract: An assembly method of direct-docking probing device is provided. First, a space transforming plate made by back-end-of-line semiconductor manufacturing process is provided, so the thickness of the space transforming plate is predetermined by the client of probe card manufacturer. Then a reinforcing plate in which a plurality of circuits disposed is provided, which has larger mechanical strength than the space transforming plate. After that the reinforcing plate and the space transforming plate are joined and electrically connected by a plurality of solders so as to form a space transformer. Then, a conductive elastic member and a probe interface board are provided. Thereafter, the space transformer and the conductive elastic member are mounted on the probe interface board. After that, at least one vertical probe assembly having a plurality of vertical probes is mounted on the space transforming plate, and the vertical probes is electrically connected with the space transforming plate.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: Chien-Chou Wu, Ming-Chi Chen, Tsung-Yi Chen, Chung-Che Li
  • Patent number: 8943683
    Abstract: A fabricating method of an embedded package structure includes following steps. First and second boards are combined to form an integrated panel. First and second circuit structures are respectively formed on the first and second boards that are then separated. An embedded element is electrically disposed on the first circuit structure. First and second conductive bumps are respectively formed on a conductive circuit substrate and the second circuit structure. First and second semi-cured films are provided; a laminating process is performed to laminate the first circuit structure on the first board, the first and second semi-cured films, the conductive circuit substrate, and the second circuit structure on the second board. The first and second semi-cured films encapsulate the embedded element. The first and second conductive bumps respectively pierce through the first and second semi-cured films and are electrically connected to the first circuit structure and the conductive circuit substrate, respectively.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: February 3, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Ming-Huang Ting
  • Publication number: 20150026971
    Abstract: A method includes forming optical lenses on an ICD at the wafer level, rather than attaching a separate lens assembly. The lenses may be formed as an array of individual lenses or as multiple, e.g., two, arrays of individual lenses. The array of lenses may be coupled to an array of ICDs. The ICDs and individual lenses in the array assembly may be singulated to form individual digital camera modules. Additionally or alternatively, the ICDs and individual lenses may be singulated in separate steps.
    Type: Application
    Filed: May 19, 2014
    Publication date: January 29, 2015
    Applicant: DigitalOptics Corporation
    Inventor: Harpuneet Singh
  • Publication number: 20150031222
    Abstract: An attachment card for Subscriber Identity Module (SIM) cards and a method for manufacturing the same are revealed. The attachment card includes a flexible printed circuit board (FPC) and a chip. The chip is disposed on one surface of the FPC with a plurality of bumps, located at a central area among preset positions for formation of the bumps. The bumps are arranged according to the established specification. The method includes several steps. First arrange a chip at a central area of a FPC by surface mount technology. Then form a plurality of bumps on one surface of the FPC. Thereby the requirement of compact size is achieved. The manufacturing processes are also simplified. Thus the cost is reduced and the attachment card has more application.
    Type: Application
    Filed: July 22, 2014
    Publication date: January 29, 2015
    Inventor: Ta-Lun SUNG
  • Publication number: 20150029275
    Abstract: A circuit including a flexible substrate and at least one electric element attached to the substrate, the substrate including at least one cavity arranged near the electric element and helping to break or distort the electric element in response to a flexion or stretching of the substrate. Application in particular is to the manufacture of tear-proof electronic micromodules.
    Type: Application
    Filed: October 10, 2014
    Publication date: January 29, 2015
    Inventors: Francis Steffen, Gilbert Assaud
  • Patent number: 8935846
    Abstract: A method for contacting a lighting device is provided, wherein the lighting device has a circuit board which is covered at least partly by a sealing compound layer; wherein the lighting device can be separated at a separating point into two lighting device sections and each of the lighting device sections has at least one electrical contact. The method may include: removing at least the sealing compound layer on both sides of the separation point so that the contacts remain covered by a thinner, remaining sealing compound layer; separating the lighting device at the separation point; attaching a connection element at least to the remaining sealing compound layer of at least one of the lighting device sections, wherein the connection element has at least one contacting element, which contacts a respective contact covered by the remaining sealing compound layer after a separation or penetration of the remaining sealing compound layer.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: January 20, 2015
    Assignee: Osram AG
    Inventors: Andreas Kampfrath, Steffen Strauss
  • Publication number: 20150016771
    Abstract: An optical device includes a substrate having an electrooptical effect, and including an optical waveguide that guides light and a reflection groove having a bottom face that reflects light output from the optical waveguide; and a light-receiving element positioned above the reflection groove and fixed to the substrate. The light output from the optical waveguide into the reflection groove is reflected by the bottom face of the reflection groove while traveling through a space inside the reflection groove and is incident to the light-receiving element.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 15, 2015
    Inventors: Shinji MARUYAMA, Yoshihiko YOSHIDA, Tomoyuki ITO, Yoshihiro TAKAHASHI, Yoshinobu KUBOTA
  • Publication number: 20150016044
    Abstract: Exemplary embodiments include a socket interposer having a plurality of connectors and at least one of on-board memory and an external communication controller. The plurality of connectors is configured to fit with a form factor of a socket on a server board. The server board includes at least one processor and a circuit board having the socket and at least one processor socket. The processor(s) are coupled with the processor socket(s). The socket has the form factor configured for a module having a first functional set and the form factor. The at least one of the on-board memory and the external communication controller is coupled with at least some of the connectors. The external communication controller also has a second functional set different from the first functional set. The on-board memory is configured to be usable by the processor(s).
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Inventor: Zhan (John) Ping
  • Patent number: 8925190
    Abstract: It is intended to provide an electronic component mounting device and an operation performing method for mounting electronic components so that both the operation quality and the productivity can be improved. In operation performing procedures, when an electronic component belongs to the first division, an operating head is made to move up and down based on an approximate operation position height derived from an approximate curved surface of the top surface of a board which is calculated by using the height measurement result obtained by measuring a plurality of height measuring points on the surface of the board, and when the electronic component belongs to the second division, the operating head is made to move up and down based on an individual operation position height obtained by individually measuring the board height at the operation position.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: January 6, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tadashi Endo, Hiroshi Ogata, Tomohiro Kimura, Takaaki Yokoi
  • Patent number: 8925193
    Abstract: A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one side of each of the plurality of dielectric sheets, and substantially filling each of the plurality of through holes with a conductive material. The conductive material is both electrically and thermally uninterrupted from a first face to a second face of each of the plurality of dielectric sheets. The plurality of dielectric sheets are then sequentially mounted, one atop another, to form the circuit board. The sequential mounting step is performed after the steps of drilling the plurality of through-holes, forming the conductive layer, and substantially filling the plurality of through-holes.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: January 6, 2015
    Assignee: Advantest (Singapore) Pte Ltd
    Inventor: Romi O. Mayder
  • Publication number: 20140375387
    Abstract: Various embodiments may provide a monolithic transformer for a radio frequency (RF) power amplifier module, such as a microwave frequency power amplifier module. The transformer may include a plurality of pairs of edge-coupled transmission lines, with individual pairs including first and second edge-coupled transmission lines. The first transmission lines may include first ends coupled with one another and second ends coupled with an input terminal of the transformer. The second transmission lines may include first ends coupled with the input terminal and second ends coupled with an output terminal of the transformer. The transformer may pass a communication signal from the input terminal to the output terminal, and provide a first impedance at the input terminal and a second impedance at the output terminal. The second impedance may be higher than the first impedance (e.g., by a factor of four).
    Type: Application
    Filed: June 27, 2013
    Publication date: December 25, 2014
    Inventor: Charles F. Campbell
  • Publication number: 20140369016
    Abstract: Provided is a printed circuit board for a memory card and a method of manufacturing the same, the printed circuit board for the memory card, including: an insulating layer; a mounting unit formed on a first surface of the insulating layer and electrically connected to a memory device; a terminal unit formed on a second surface of the insulating layer and electrically connected to electronic apparatuses of an outside; and metal layers formed at the mounting unit and the terminal unit and made of the same material.
    Type: Application
    Filed: December 12, 2012
    Publication date: December 18, 2014
    Inventors: Seol Hee Lim, Yun Kyoung Jo, Ae Rim Kim, Sai Ran Eom, Chang Hwa Park
  • Patent number: 8912090
    Abstract: An improved microwave mixer manufactured using multilayer processing includes an integrated circuit that is electrically connected to a top metal layer of a substrate. The microwave mixer includes: a first metal layer; a dielectric substrate on the first metal layer; a second metal layer directly on the substrate, at least two passive circuits arranged on the second metal layer and a top layer metal; a thin dielectric layer on the second metal layer, wherein the top layer metal is directly on the thin dielectric layer; an integrated circuit (IC) attached to the second metal layer, wherein the IC includes at least one combination of non-linear devices, and wherein the IC is directly connected to the passive circuits on the second metal layer; and a protection layer on the IC.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: December 16, 2014
    Assignee: Marki Microwave, Inc.
    Inventor: Christopher Ferenc Marki
  • Publication number: 20140355215
    Abstract: An electronic package is fabricated wherein a substrate is provided having three or more layers. A heat slug is embedded completely within the substrate. A die is attached above the substrate. Thermal paths to the heat slug are linked through the ground signal interconnects (traces, vias and planes).
    Type: Application
    Filed: June 3, 2013
    Publication date: December 4, 2014
    Inventors: Baltazar Canete, Melvin Martin, Ian Kent
  • Patent number: 8898895
    Abstract: A method for producing a multilayer substrate involves: a base-material pretreatment step in which a hole forming step and a metal adhesion step are performed in no particular order, the hole forming step being a step of subjecting a core base material having at least an insulating layer and a first metal layer to a hole opening process, the metal adhesion step being a step in which a predetermined metal or metal ion is made to adhere to the other surface of the insulating layer; a desmearing step of performing desmearing by plasma etching; a cleaning step of cleaning the core base material by using an acidic solution; and a plating step of applying a plating catalyst or a precursor thereof onto the insulating layer and performing plating.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: December 2, 2014
    Assignee: FUJIFILM Corporation
    Inventors: Shiki Ueki, Takeshi Hama, Takeyoshi Kano
  • Patent number: 8898891
    Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: December 2, 2014
    Assignee: Force10 Networks, Inc.
    Inventors: Joel R. Goergen, Yi Zheng
  • Publication number: 20140346110
    Abstract: The filtration membrane (102) includes an ozone producing circuit (120) having a plurality of electrically conductive lines (122, 124) disposed directly upon an active surface (102a) of the filtration membrane (102). The electrically conductive lines (122, 124) form spaced-apart and interleaved anodes (122) and cathodes (124). Ozone and other mixed oxidants coming from the ozone producing circuit (120) will prevent and/or remove biofilm formations on the active surface (102a) without the need of an outside source of gas. They can also remove at least some undesirable dissolved gases from the liquid being purified.
    Type: Application
    Filed: August 3, 2012
    Publication date: November 27, 2014
    Applicant: Ozomax Inc.
    Inventors: Amir Salama, Marianne Salama
  • Patent number: 8893379
    Abstract: A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the seed layer. A first patterned dry film layer is formed on the other portion of the seed layer. A surface treatment layer is electroplated on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask. The first patterned dry film layer is removed. A chip bonding process is performed to electrically connect a chip to the surface treatment layer. An encapsulant is formed on the metal substrate. The encapsulant encapsulates the chip, the surface treatment layer, and the patterned circuit layer. The metal substrate and the seed layer are removed to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: November 25, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Shih-Hao Sun, Chang-Fu Chen
  • Patent number: 8895864
    Abstract: An apparatus and method wherein the apparatus includes a deformable substrate; a conductive portion; and at least one support configured to couple the conductive portion to the deformable substrate so that the conductive portion is spaced from the deformable substrate.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: November 25, 2014
    Assignee: Nokia Corporation
    Inventors: Darryl Cotton, Samiul Md Haque, Piers Andrew
  • Publication number: 20140340853
    Abstract: Safety devices are provided having a power generating part and a safety-critical part. A conducting ring is provided at least around the power generating part. The ring may be connected to a reference potential such as ground.
    Type: Application
    Filed: May 14, 2013
    Publication date: November 20, 2014
    Applicant: Infineon Technologies AG
    Inventors: Timo Dittfeld, Peter Hoffmann, Dirk Hammerschmidt
  • Publication number: 20140340860
    Abstract: The invention comprises an at least one-layer electrical circuit board (1) having internal and/or external conducting tracks or electrical circuits (3, 8), which circuit board has copper pads (4, 5) arranged on the surface for population with electrical components and/or which has copper pads (5) for electrically connecting at least two layers of the circuit board, and which is at least partially surrounded by media, in particular liquid media, further in particular oil, or is directly exposed thereto, wherein said copper pads (4, 5) and exposed conducting tracks (8) are coated with a further metal (7).
    Type: Application
    Filed: September 6, 2012
    Publication date: November 20, 2014
    Applicant: ROBERT BOSCH GMBH
    Inventors: Andreas Otto, Sabrina Rathgeber, Marc Fischer
  • Patent number: 8887383
    Abstract: An electrode structure 100 on which a solder bump is placed includes an electrode pattern 50 made of an electrode-constituting material selected from the group consisting of Cu, Al, Cr, and Ti, a Ni layer 52 formed on a part of the electrode pattern 50, a Pd layer 54 formed on at least a part of a region other than the part of the electrode pattern 50, and an Au layer 56 formed on the Ni layer 52 and the Pd layer 54.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: November 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Yasushi Taniguchi, Seiichi Nakatani, Takashi Kitae, Seiji Karashima, Kenichi Hotehama
  • Patent number: 8887382
    Abstract: The invention relates to a pendulous accelerometer including a pendulous electrode formed in a substrate, at least one counter electrode, and an encapsulation cover. The at least one counter electrode is formed under the cover, and spacers are positioned between the cover and the substrate.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: November 18, 2014
    Assignee: MEMSCAP
    Inventors: Béatrice Wenk, Jean-Francois Veneau, Greg Hames
  • Patent number: 8881389
    Abstract: In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: November 11, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Ruban Kanapathippillai, Kenneth Alan Okin
  • Patent number: 8881353
    Abstract: Provided is a method of producing a piezoelectric/electrorestrictive film type device including a vibrating laminate obtained by laminating electrode films and piezoelectric/electrorestrictive films on a substrate containing a cavity. The method of producing the vibrating laminate includes: producing the substrate with a cavity, forming the first photoresist film on first principal surface of substrate, irradiating substrate from the second principal surface side of the substrate, transferring the plane shape of the cavity to the first photoresist film, developing and removing the first photoresist film formed in the region where the shape of cavity was formed, forming a lowermost electrode film by plating, and forming additional films other than the lowermost electrode film constituting the vibrating laminate.
    Type: Grant
    Filed: September 6, 2010
    Date of Patent: November 11, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Hideki Shimizu, Mutsumi Kitagawa
  • Patent number: 8881381
    Abstract: Disclosed herein is a method of manufacturing a printed circuit board, comprising: preparing a first carrier including a first pattern formed on one side thereof; preparing a second carrier including a first solder resist layer and a second pattern sequentially formed on one side thereof; pressing the first carrier and the second carrier such that the first pattern is embedded in one side of an insulation layer and the second pattern is embedded in the other side of the insulation layer and then removing the first carrier and the second carrier to fabricate two substrates; attaching the two substrates to each other using an adhesion layer such that the first solder resist layers face each other; and forming a via for connecting the first pattern with the second pattern in the insulation layer, forming a second solder resist on the insulation layer provided with the first pattern, and then removing the adhesion layer.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: November 11, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Mi Sun Hwang, Myung Sam Kang, Ok Tae Kim, Seon Ha Kang, Gil Yong Shin, Kil Yong Yun, Min Jung Cho
  • Patent number: 8875363
    Abstract: Disclosed are methods of making a dielectric on a metal foil, and a method of making a large area capacitor that includes a dielectric on a metal foil. A first dielectric layer is formed over the metal foil by physical vapor deposition, and a dielectric precursor layer is formed over the first dielectric layer by chemical solution deposition. The metal foil, first dielectric layer and dielectric precursor layer are prefired at a prefiring temperature in the range of 350 to 650° C. The prefired dielectric precursor layer, the first dielectric layer and the base metal foil are subsequently fired at a firing temperature in the range of 700 to 1200° C.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: November 4, 2014
    Assignee: CDA Processing Limited Liability Company
    Inventors: Seigi Suh, Esther Kim, William J. Borland, Christopher Allen Gross, Omega N. Mack, Timothy R. Overcash
  • Patent number: 8875390
    Abstract: A method of manufacturing a laminate circuit board which includes the sequential steps of metalizing the substrate to form the base layer, forming the first circuit metal layer, forming at least one insulation layer and at least one second circuit metal layer interleaved, removing the substrate, forming the support frame and forming the solder resist is disclosed. The laminate circuit board has a thickness less than 150 ?m. The support frame which does not overlap the first circuit metal layer is formed on the edge of the base layer by the pattern transfer process after the substrate is removed. The base layer formed of at least one metal layer is not completely removed. The support frame provides enhanced physical support for the entire laminate circuit board without influence on the electrical connection of the circuit in the second circuit metal layer, thereby solving the warping problem.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: November 4, 2014
    Assignee: Kinsus Interconnect Technology Corp.
    Inventors: Ting-Hao Lin, Yu-Te Lu, De-Hao Lu
  • Publication number: 20140318834
    Abstract: A wiring board of the present invention includes a core substrate in which wiring conductors are formed on both surfaces of an insulating plate, and a build-up layer in which a conductor layer is formed on a surface of an insulating resin layer having a higher coefficient of thermal expansion than that of the insulating plate. At least one build-up layer is stacked on one surface or both surfaces of the core substrate. Both surfaces of the insulating plate have different coefficients of thermal expansion. At least one build-up layer is stacked on a surface having a lower coefficient of thermal expansion. No build-up layer is stacked on the opposite surface, or a smaller number of build-up layers than that of the build-up layer formed on the surface having the lower coefficient of thermal expansion is formed on the opposite surface.
    Type: Application
    Filed: May 6, 2014
    Publication date: October 30, 2014
    Applicant: KYOCERA SLC Technologies Corporation
    Inventor: Tomoharu TSUCHIDA