With Encapsulating, E.g., Potting, Etc. Patents (Class 29/841)
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Patent number: 8806742Abstract: An electronic package has a cover or lid mounted onto a substrate to enclose an electronic device, and a liquid thermal interface material is subsequently inserted (through dispensing, injection molding or printing through apertures in the cover or lid) between the surface of the electronic device and the cover, and cured to a solid state.Type: GrantFiled: September 2, 2009Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Erwin B Cohen, Martin P Goetz, Jennifer V Muncy
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Patent number: 8806743Abstract: A method is presented for forming multiple surface mount technology (SMT) sensor packages in a panel for separation into individual SMT sensor packages. A base plate is mapped as a grid of sensor footprints, and each footprint is populated with electronic and sensor components. A cover plate including window elements is mapped to a similar grid. The cover plate is bonded to the base plate, such that the window elements are positioned to allow incident electromagnetic radiation upon corresponding sensors mounted on the printed circuit board. Each sensor footprint is sealed within a recess or cell beneath the cover. The sensor circuits may be tested before and/or after being separated into individual SMT sensor packages.Type: GrantFiled: August 7, 2012Date of Patent: August 19, 2014Assignee: Excelitas Technologies Singapore Pte. LtdInventor: Arthur Barlow
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Patent number: 8806741Abstract: An electronic device is disclosed. One embodiment provides a metallic body. A first electrically insulating layer is applied over the metallic body and having a thickness of less than 100 ?m. A first thermally conductive layer is applied over the first electrically insulating layer and having a thermal conductivity of more than 50 W/(m·K). A second electrically insulating layer is applied over the first thermally conductive layer and having a thickness of less than 100 ?m.Type: GrantFiled: October 6, 2011Date of Patent: August 19, 2014Assignee: Infineon Technologies AGInventor: Ralf Otremba
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Patent number: 8793868Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.Type: GrantFiled: June 23, 2011Date of Patent: August 5, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
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Patent number: 8789271Abstract: This publication discloses a circuit-board construction and a method for manufacturing an electronic module, in which method at least one component (6) is embedded inside an insulating-material layer (1) and contacts (14) are made to connect the component (6) electrically to the conductor structures (14, 19) contained in the electronic module. According to the invention, at least one thermal via (22), which boosts the conducting of heat away from the component (6) is manufactured in the insulating-material layer (1) in the vicinity of the component (6).Type: GrantFiled: May 29, 2009Date of Patent: July 29, 2014Assignee: AT & S Austria Technologies & Systemtechnik AktiengesellschaftInventors: Günther Weichslberger, Arno Kriechbaum, Mike Morianz, Nikolai Haslebner, Johannes Stahr, Fritz Haring, Gerhard Freydl, Andrea Koertvelyessy, Mark Beesley, Andreas Zluc, Wolfgang Schrittwieser
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Patent number: 8780561Abstract: A method of forming a heat-dissipating structure for semiconductor circuits is provided. First and second semiconductor integrated circuit (IC) chips are provided, where the first and second semiconductor chips each have first and second opposing sides, wherein the first and second semiconductor IC chips are configured to be fixedly attached to a top surface of a substantially planar circuit board along their respective first sides. The respective second opposing sides of each of the first and second semiconductor IC chips are coupled to first and second respective portions of a sacrificial thermal spreader material, the sacrificial thermal spreader material comprising a material that is thermally conductive. The first and second portions of the sacrificial thermal spreader material are planarized to substantially equalize a respective first height of the first semiconductor chip and a respective second height of the second semiconductor chip.Type: GrantFiled: March 30, 2012Date of Patent: July 15, 2014Assignee: Raytheon CompanyInventors: Paul A. Danello, Richard A. Stander, Michael D. Goulet
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Patent number: 8776365Abstract: A method of manufacturing a terminal block for a telecommunication cable, which includes providing a housing having a front side and a back side and positioning multiple pairs of electrical connectors in the housing such that one end of each of the electrical connectors is exposed on the front side of the housing and one end of the connector is exposed on the back side of the housing. Each of electrical connectors having an insulation displacement contact terminal on the end exposed on the back side of the housing, and connecting multiple pairs of insulated electrical wires to the connectors on the back side of the housing. A dielectric material is pressure molded on the back side of the housing to encapsulate the connections of the wires and the connectors on the back side of the housing.Type: GrantFiled: July 27, 2010Date of Patent: July 15, 2014Assignee: Channell Commercial CorporationInventors: William H. Channell, Sr., Edward J. Burke
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Patent number: 8769811Abstract: An electronic circuit component is provided with shielding for electromagnetic interference (“EMI”) by covering at least part of the component with a layer of electrical insulation that conforms to the shape of the surface to which the insulation is applied. At least part of the surface of the insulation is then covered by a layer of EMI shielding that conforms to the shape of the surface of the insulation to which the shielding is applied.Type: GrantFiled: November 3, 2009Date of Patent: July 8, 2014Assignee: Apple Inc.Inventors: Josh Wurzel, Shawn Robert Gettemy, Ahmad Al-Dahle, Carlin James Vieri, Wei Yao
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Publication number: 20140187057Abstract: A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Gregorio R. Murtagian, Bhanu Jaiswal, Sriram Srinivasan, Michael J. Hill
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Publication number: 20140185256Abstract: When forming a module 100 having a configuration in which a column-shaped connection terminal 11, which forms an interlayer connection conductor, and an electronic component 102 are mounted on a wiring substrate 101 and sealed with a resin, the column-shaped connection terminal 11 which has a substantially T-shaped cross section and in which a first end portion has a larger diameter than a second end portion is prepared (the preparation step), an electronic component 102 is mounted on one main surface of the wiring substrate 101 and the connection terminal 11 is mounted on the one main surface in such a manner that the second end portion of the connection terminal 11 having a smaller diameter is connected to the wiring substrate 101 (the mounting step), and the electronic component 102 and the connection terminal 11 are sealed with a resin layer 103 (the sealing step).Type: ApplicationFiled: March 6, 2014Publication date: July 3, 2014Applicant: Murata Manufacturing Co., Ltd.Inventors: Nobuaki Ogawa, Yoshihito Otsubo
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Patent number: 8763220Abstract: Provided is a manufacturing method for a micro device. The manufacturing method includes forming a micro-electronic-mechanical system (MEMS) movable structure, forming a plurality of metal loops over the MEMS movable structure, forming a piezoelectric element over the MEMS movable structure, and a magnet disposed over the plurality of metal loops. The method also includes encapsulating the MEMS movable structure, the plurality of metal loops, and the piezoelectric element.Type: GrantFiled: February 12, 2013Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tien-Kan Chung, Chung-Hsien Lin, Yao-Te Huang, Chia-Hua Chu, Chia-Ming Hung, Wen-Chuan Tai, Chang-Yi Yang
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Patent number: 8763242Abstract: In a method of manufacturing a semiconductor device, a second wiring substrate is stacked over a first wiring substrate using a conductive paste, where each wiring substrate has mounted thereon an electronic component. The conductive paste is hardened to form a metal column which forms an electrical connection between the first wiring substrate and the second wiring substrate. The wiring substrates are sealed with a resin. The semiconductor device can be downsized, thinned, and made highly reliable, and its manufacturing cost can be reduced. By using conductive paste for the electrical connection between the wiring substrates, a connecting pitch can be smaller than that in a connecting method of using a solder ball including Cu core, and a connection at low temperature can be achieved. Also, by coating the conductive paste by a print-coating or dispense-coating method, manufacturing is simplified and the manufacturing cost is reduced.Type: GrantFiled: November 30, 2010Date of Patent: July 1, 2014Assignee: Renesas Electronics CorporationInventors: Kenya Kawano, Chiko Yorita, Yuji Shirai
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Publication number: 20140174307Abstract: A stamping die for hot stamping a material includes a profiled stamping surface, wherein the stamping die includes at least one thermally insulating substrate, on which an electrically conductive structure having a heating resistor is arranged, and wherein the electrically conductive structure is covered by an electrically insulating film. The surface of the electrically insulating film includes the profiled stamping surface and the electrically insulating film covers at least the heating resistor such that the electrically insulating film with the stamping surface can be electrically heated by the heating resistor. A method for hot stamping a material using such a stamping die includes heating the resistor to a temperature between 100° C. and 800° C.Type: ApplicationFiled: June 27, 2012Publication date: June 26, 2014Applicant: HERAEUS SENSOR TECHNOLOGY GmbHInventors: Karlheinz Wienand, Matsvei Zinkevich
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Patent number: 8756776Abstract: A method of manufacturing a microactuator. The method includes providing a sheet of a piezoelectric material having an electrically conductive layer on at least one side of the sheet. The method includes cutting the sheet to form a plurality of piezoelectric elements. Each of the piezoelectric elements includes a first element side with an electrically conductive layer. Each first element side includes a peripheral portion and an exposed portion interior to the peripheral portion. The method includes forming an encapsulation layer over the peripheral portion and not over the exposed portion of at least one of the sides. The encapsulation layer comprises a material of lesser electrical conductivity than the electrically conductive layer. An apparatus for manufacturing the microactuators may also be provided that includes a first fixture and first and second alignment combs.Type: GrantFiled: October 14, 2009Date of Patent: June 24, 2014Assignee: Western Digital Technologies, Inc.Inventors: Yih-Jen D. Chen, Robert J. McNab
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Patent number: 8756801Abstract: One or more light emitting diode diodes (LEDs) are attached to a printed circuit board. The attached LEDs are connectable with a power source via circuitry of the printed circuit board. An overmolding material is insert molded an over at least portions of the printed circuit board proximate to the LEDs to form a free standing high thermal conductivity material overmolding that covers at least portions of the printed circuit board proximate to the LEDs. The free standing high thermal conductivity material has a melting temperature greater than about 100° C. and has a thermal conductivity greater than or about 1 W/m·K. In some embodiments, the free standing high thermal conductivity material is a thermoplastic material.Type: GrantFiled: November 23, 2011Date of Patent: June 24, 2014Assignee: GE Lighting Solutions, LLCInventors: Jeffrey Nall, Matthew Mrakovich
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Patent number: 8745858Abstract: The invention relates to a method for applying soft solder to a mounting surface of a component, wherein a connecting means comprising a carrier layer and a soft solder layer formed by physical vapor deposition on the carrier layer is brought into mechanical contact between the soft solder layer and the mounting surface, such that a first bond strength between the soft solder layer and the mounting surface is greater than a second bond strength between the soft solder layer and the carrier layer. The connecting means is subsequently removed from the component so that the carrier layer releases from the soft solder layer in the area of the mounting surface and thus soft solder remains only at the mounting surface.Type: GrantFiled: February 22, 2011Date of Patent: June 10, 2014Assignee: JEONPTIK Laser GmbHInventors: Dominic Schroeder, Matthias Schroeder
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Publication number: 20140146536Abstract: A light emitting diode (LED) component includes a base having a main body and a wiring pattern. The main body defines an axis and includes two connecting surfaces respectively located at two opposite sides thereof, and a plurality of interconnected mounting surfaces surrounding the axis and connected between the connecting surfaces. The wiring pattern is at least disposed on the mounting surfaces and includes electrically insulated anode and cathode. A plurality of light emitting diode (LED) chips are disposed on the mounting surfaces. Each LED chip is electrically connected to the anode and the cathode.Type: ApplicationFiled: November 26, 2013Publication date: May 29, 2014Applicants: LITE-ON TECHNOLOGY CORP., LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD.Inventor: PO-WEI LI
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Patent number: 8735736Abstract: The electronic component module includes a substrate; an electronic component mounted on an electronic component mounting surface of the substrate; an insulating body that covers the electronic component on the electronic component mounting surface of the substrate; and a metal film formed by electroless plating, the metal film covering an exterior surface of the insulating body and a side surface of the substrate. The substrate has a space section in which a space is formed, the space being dented inward of the substrate in the periphery of a surface opposite to the electronic component mounting surface of the substrate, and the metal film entirely covers at least one side surface of the electronic component module except for at least a portion located on a surface perpendicular to the electronic component mounting surface of the substrate in the space section.Type: GrantFiled: October 21, 2011Date of Patent: May 27, 2014Assignee: SAE Magnetics (H.K.) Ltd.Inventors: Tamon Kasajima, Masashi Shiraishi
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Patent number: 8732924Abstract: A method of manufacturing a piezoelectric vibrator comprises supporting a piezoelectric vibration element in a case by a conductive bonding member, the piezoelectric vibration element having a metal layer formed on a piezoelectric substrate formed of a thickness shear based piezoelectric material, and adding or reducing a thickness of the metal layer to adjust a resonant frequency of the piezoelectric vibration element to a predetermined value. The method also comprises leaving the case into an atmosphere filled with vapor of a material having a nonbonding electron pair, making the metal layer resultantly exposed to the vapor subject to chemical absorption with the material having the nonbonding electron pair, and hermetically encapsulating the case in a state substituted by an inert gas atmosphere.Type: GrantFiled: September 12, 2012Date of Patent: May 27, 2014Assignee: Seiko Epson CorporationInventors: Tsuyoshi Ohshima, Shin Hasegawa, Noriyuki Watanabe
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Publication number: 20140131083Abstract: Disclosed herein is a printed circuit board, including: a mounting substrate having a cavity formed therein; an electronic component inserted into the cavity; and a base substrate formed at least one of an upper part and a lower part of the electronic component, inserted into the cavity, and having an upper substrate pad and a lower substrate pad extended outwardly thereof and connected to each other.Type: ApplicationFiled: March 15, 2013Publication date: May 15, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sung Yeol Park, Suk Jin Ham, Jung Eun Noh
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Patent number: 8724334Abstract: A circuit module and a manufacturing method for the same, reduce a possibility that a defect area where an electrically conductive resin is not coated may occur in a shield layer. A mother board is prepared. A plurality of electronic components are mounted on a principal surface of the mother board. An insulator layer is arranged so as to cover the principal surface of the mother board and the electronic components. The insulator layer is cut such that grooves and projections are formed in and on the principal surface of the insulator layer and the insulator layer has a predetermined thickness H. An electrically conductive resin is coated on the principal surface of the insulator layer to form a shield layer. The mother board including the insulator layer and the shield layer both formed thereon is divided to obtain a plurality of circuit modules.Type: GrantFiled: July 12, 2012Date of Patent: May 13, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroshi Nishikawa, Makoto Fujita, Fumikiyo Kawahara
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Publication number: 20140126157Abstract: An electronic circuit module includes a substrate with built-in component, a mount component mounted on the substrate with built-in component, a sealing portion covering the mount component, and a shield made of a conductive synthetic resin covering the sealing portion. The substrate with built-in component has a core layer made of a metal, an outer cover made of an insulating synthetic resin, and a first protrusion. The core layer has corners and side faces. The outer cover covers the corners and the side faces, and has a first surface. The first protrusion has a first end face exposed at the outer cover and a second surface adjacent to the first surface, and is formed away from the corners of the side faces to protrude outwardly. The sealing portion covers the mount component. The shield covers the sealing portion, and has a third surface bonded to the first surface and the second surface.Type: ApplicationFiled: November 6, 2013Publication date: May 8, 2014Applicant: TAIYO YUDEN CO., LTD.Inventors: Tatsuro SAWATARI, Masashi MIYAZAKI, Yoshiki HAMADA, Yuichi SUGIYAMA, Kazuaki IDA
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Publication number: 20140126165Abstract: An assembled component and a method for assembling a component are disclosed. In one embodiment the assembled component includes a component carrier, an attachment layer disposed on the component carrier and a component disposed on the attachment layer, the component having a nano-structured first main surface facing the component carrier.Type: ApplicationFiled: November 6, 2012Publication date: May 8, 2014Applicant: Infineon Technologies Austria AGInventors: Khalil Hosseini, Joachim Mahler, Georg Meyer-Berg
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Publication number: 20140116763Abstract: A wiring board with a built-in electronic component includes a core substrate having a cavity, an electronic component accommodated in the cavity of the core substrate and having a body portion and multiple conductive portions formed on a surface of the body portion, a filling resin filling the space formed in the cavity having the component positioned in the cavity, and an resin insulation layer formed on the core substrate such that the resin insulation layer is covering an opening of the cavity and a surface of the component. The core substrate has an inclination suppressing structure formed on one or more side walls forming the cavity such that the distance between the side wall forming the cavity and the component varies in a portion of the side wall having the inclination suppressing structure and a portion of the side wall other than the portion having the inclination suppressing structure.Type: ApplicationFiled: October 25, 2013Publication date: May 1, 2014Applicant: IBIDEN CO., LTD.Inventors: Kenji SATO, Masahiro ZANMA
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Publication number: 20140117201Abstract: A sensor assembly is disclosed that includes a hollow casing having a radiation entrance opening. A radiation-transmissive optic is at the radiation entrance opening. A substrate is inside and sealed against the hollow casing. An optical sensing element is coupled to the substrate and configured to sense radiation that has passed through the radiation-transmissive optic. A method of manufacturing the sensor assembly also is disclosed.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: EXCELITAS TECHNOLOGIES SINGAPORE PTE. LTD.Inventor: Arthur John Barlow
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Patent number: 8701272Abstract: A method of forming a power module located on a conductive substrate by providing power conversion circuitry. The method of providing the power conversion circuitry includes forming a magnetic device by placing a magnetic core proximate a conductive substrate with a surface thereof facing a conductive substrate, and placing a conductive clip proximate a surface of the magnetic core. The method of forming the magnetic device also includes electrically coupling ends of the conductive clip to the conductive substrate to cooperatively form a winding therewith about the magnetic core. The method of providing the power conversion circuitry also includes providing at least one switch on the conductive substrate. The method of forming the power module also includes depositing an encapsulant about the power conversion circuitry.Type: GrantFiled: October 5, 2005Date of Patent: April 22, 2014Assignee: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Mathew A. Wilkowski, Trifon M. Liakopoulos, John D. Weld
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Publication number: 20140104803Abstract: Disclosed herein is a circuit board that includes a resin substrate including a substrate wiring layer, and an electronic component embedded in the resin substrate and having a plurality of external electrodes. The resin substrate includes a plurality of via holes that expose the external electrodes and a plurality of via conductors embedded in the via holes to electrically connect the substrate wiring layer to the external electrodes. At least some of the via holes are different in planar shape from each other.Type: ApplicationFiled: October 15, 2013Publication date: April 17, 2014Applicant: TDK CorporationInventor: Kazutoshi TSUYUTANI
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Patent number: 8695209Abstract: A method of producing a surface-mount inductor by encapsulating a coil with an encapsulation material containing a resin and a filler using a mold die assembly is provided. In the method, a tablet and a coil are used. The tablet is prepared by preforming the encapsulation material into a shape having a flat plate-shaped portion and a pillar-shaped convex portion on a peripheral thereof. The coil is a wound conductive wire having a cross-section of rectangular-shape. The coil is placed on the tablet to allow both ends of the coil to extend along an outer side surface of the pillar-shaped convex portion of the tablet. The coil and the encapsulation material are integrated together while clamping the both ends of the coil between an inner wall surface of the mold die assembly and the outer side surface of the pillar-shaped convex portion of the tablet, to form a molded body.Type: GrantFiled: April 9, 2010Date of Patent: April 15, 2014Assignee: TOKO, Inc.Inventors: Koichi Saito, Chitoshi Sakai
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Patent number: 8695208Abstract: A method for manufacturing a monolithic inductive component is provided. The method may include providing a green body comprising a green sheet composite for forming a multilayer ceramic body with an integrated winding and a shaped body of ferritic core material, the green sheet composite being combined with an encapsulation so as to create a cavity with a cavity opening between the encapsulation and the green sheet composite, and the cavity being filled with the ferritic core material through the cavity opening; and heat-treating the green body, a multilayer ceramic body with an integrated winding being created from the green sheet composite and a magnetic core comprising the ferritic core material being created from the green sheet composite.Type: GrantFiled: June 18, 2008Date of Patent: April 15, 2014Assignee: Siemens AktiengesellschaftInventor: Richard Matz
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Publication number: 20140098505Abstract: An improved method for producing a PCB assembly requiring at least two different encapsulants is disclosed. The PCB assembly may have two or more separate regions in which electronic devices are attached. In each region, a unique encapsulant with different mechanical, electrical, physical and or chemical properties is used according to the particular requirements of the electronic devices in that region.Type: ApplicationFiled: October 5, 2012Publication date: April 10, 2014Applicant: Apple Inc.Inventor: John J. Baker
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Patent number: 8683674Abstract: Method for stacking microelectronic devices using two or more carriers, each holding microelectronic devices in an array so they may be registered. Each device is releasably held by its edges in a carrier to allow access to top and bottom surfaces of the device for joining. Arrays of devices held in two or more carriers are juxtaposed and joined to form an array of stacked devices. A resulting stacked device is released from the juxtaposed carriers holding each device by releasing forces of the corresponding carrier urging upon edges of the device, thereby permitting removal of the stacked device.Type: GrantFiled: December 6, 2011Date of Patent: April 1, 2014Assignee: Centipede Systems, Inc.Inventor: Thomas H. Di Stefano
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Patent number: 8686299Abstract: An electronic element unit (1) includes an electronic element (2) having a plurality of connecting terminals (12) on a lower surface thereof, a circuit board (3) having a plurality of electrodes (22) corresponding to the connecting terminals (12) on an upper surface thereof. The connecting terminals (12) and the electrodes (22) are connected by solder bumps (23), and the electronic element (2) and the circuit board (3) are partly bond by a resin bond part (24) made of a thermosetting material of a thermosetting resin, and a metal powder (25) is included in the resin bond parts (24) in a dispersed state. The metal powder (25) has a melting point lower than a temperature at which the resin bond parts (24) are heated when a work (a repairing work) is carried out for removing the electronic element (2) from the circuit board (3).Type: GrantFiled: May 26, 2010Date of Patent: April 1, 2014Assignee: Panasonic CorporationInventors: Koji Motomura, Seiichi Yoshinaga, Tadahiko Sakai
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Publication number: 20140085850Abstract: Electronic devices may contain electrical systems in which electrical components are mounted on a substrate such as a printed circuit board. The electrical components may include surface mount technology components. Multiple surface mount technology components may be stacked on top of each other and beside each other to form an electrical component that minimizes the amount of area that is consumed on a printed circuit board. Noise suppression circuits and other circuits may be implemented using stacked surface mount technology components. Surface mount technology components placed on the printed circuit board may be pushed together and subsequently injection molded to form packed component groups. An integrated circuit may be mounted to the printed circuit board via an interposer and may cover components mounted to the printed circuit board. An integrated circuit may be mounted over a recessed portion of the printed circuit board on which components are mounted.Type: ApplicationFiled: September 26, 2012Publication date: March 27, 2014Inventors: Xingqun Li, Carlos Ribas, Dennis R. Pyper, James H. Foster, Joseph R. Fisher, JR., Scott P. Mullins, Sean A. Mayo, Wyeman Chen
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Patent number: 8677613Abstract: Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.Type: GrantFiled: May 20, 2010Date of Patent: March 25, 2014
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Patent number: 8677615Abstract: A method for embedding at least one component into a dielectric layer. obtain a good result, it is provided that the method includes the following steps: a) Position and affix the at least one component on a carrier; b) Cast a liquid dielectric around the at least one component, thereby enclosing the at least one component completely; c) Harden the liquid dielectric to form a solid dielectric layer; and d) Apply, in particular by lamination thereon, another layer, in particular an electrically conductive layer. The use of a dielectric layer formed entirely of liquid dielectric, wherein the liquid dielectric is not converted into a solid state until the dielectric is processed.Type: GrantFiled: July 8, 2011Date of Patent: March 25, 2014Assignee: DYCONEX AGInventors: Marc Hauer, Markus Riester
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Patent number: 8667673Abstract: A method for fabricating a laminated structure includes (i) preparing a first substrate having electroconductivity, (ii) forming a first electroconductive film having a prescribed hardness on the first substrate by an electroforming, (iii) forming a second electroconductive film having a hardness that is lower than the prescribed hardness on the first electroconductive film by an electroforming, (iv) patterning the first electroconductive film and the second electroconductive film to a prescribed pattern to form a plurality of electroconductive film patterns, and (v) subjecting the first substrate and a second substrate repeatedly to pressure contact and release to transfer sequentially the plurality of electroconductive film patterns on the first substrate onto the second substrate.Type: GrantFiled: July 21, 2010Date of Patent: March 11, 2014Assignee: Fuji Xerox Co., Ltd.Inventors: Takayuki Yamada, Kazuaki Tabata
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Publication number: 20140049449Abstract: A dual-display device includes a flexible substrate comprising first and second surfaces opposing each other, the first surface comprising a first area and a second area, the flexible substrate being bent to allow the first and second areas of the first surface to face each other, the second surface comprising first and second areas opposing the first and second areas of the first surface, respectively. The device further includes a first display unit formed over the first area of the second surface of the bent flexible substrate, and realizing an image; a second display unit formed over second area that is opposite to the first area of the second surface of the bent flexible substrate, electrically connected to the first display unit via lines, and realizing another image; and a common driver unit electrically connected to a pad area that extends from the first display unit, and configured to transmit at least a signal to drive the first display unit and the second display unit.Type: ApplicationFiled: January 28, 2013Publication date: February 20, 2014Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Jin-Oh Park, Dong-Wan Choi, Hyo-Sang Yang
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Patent number: 8650748Abstract: A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.Type: GrantFiled: May 12, 2011Date of Patent: February 18, 2014Assignee: National Semiconductor CorporationInventors: Artur Darbinyan, David T. Chin, Kurt E. Sincerbox
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Publication number: 20140041916Abstract: In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer.Type: ApplicationFiled: August 8, 2013Publication date: February 13, 2014Applicant: Marvell World Trade Ltd.Inventors: Sehat Sutardja, Albert Wu, Hyun J. Shin
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Publication number: 20140041214Abstract: A method is presented for forming multiple surface mount technology (SMT) sensor packages in a panel for separation into individual SMT sensor packages. A base plate is mapped as a grid of sensor footprints, and each footprint is populated with electronic and sensor components. A cover plate including window elements is mapped to a similar grid. The cover plate is bonded to the base plate, such that the window elements are positioned to allow incident electromagnetic radiation upon corresponding sensors mounted on the printed circuit board. Each sensor footprint is sealed within a recess or cell beneath the cover. The sensor circuits may be tested before and/or after being separated into individual SMT sensor packages.Type: ApplicationFiled: August 7, 2012Publication date: February 13, 2014Applicant: EXCELITAS TECHNOLOGIES SINGAPORE PTE. LTD.Inventor: Arthur Barlow
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Publication number: 20140043754Abstract: An electronic device having one or more components that generate heat during operation includes a structure for temperature management and heat dissipation. The structure for temperature management and heat dissipation comprises a heat transfer substrate having a surface that is in thermal communication with the ambient environment and a temperature management material in physical contact with at least a portion of the one or more components of the electronic device and at least a portion of the heat transfer substrate. The temperature management material comprises a polymeric phase change material having a latent heat of at least 5 Joules per gram and a transition temperature between 0° C. and 100° C., and a thermal conductive filler.Type: ApplicationFiled: October 16, 2013Publication date: February 13, 2014Applicant: Outlast Technologies LLCInventors: Mark Hartmann, Greg Roda
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Publication number: 20140029208Abstract: The present invention pertains to a component-containing module that is: provided with a substrate configured from flat sections and a projecting section, and electronic components mounted on the flat sections and the projecting section; and characterized in that the electronic components mounted on the flat sections are sealed in resin, and the electronic component mounted on the projecting section has an upper part thereof exposed above the resin surface.Type: ApplicationFiled: April 2, 2012Publication date: January 30, 2014Applicant: NEC CORPORATIONInventors: Nozomu Nishimura, Nobuhiro Mikami
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Patent number: 8631566Abstract: A method for manufacturing a circuit board structure comprising at least one electrical component. The method comprises the steps of fabricating a conductive pattern on the surface of an essentially plane-like layer on the back side of the plane-like layer, and forming an electrical contact between the at least one electrical component and the conductive pattern.Type: GrantFiled: August 24, 2009Date of Patent: January 21, 2014Assignee: Imbera Electronics OyInventors: Petteri Palm, Tuomas Waris
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Patent number: 8627563Abstract: A process relating to a one step low pressure injection molding method of encapsulating high voltage circuitry while incorporating a unique recessed high voltage connector contact means within the injection molding material, greatly reducing the component size, while increasing the capabilities of this type of circuitry. The process reduces the manufacturing time and maintains a clean sealed contact point for repeated usage by the means of a conductive rubber slug. An additional advantage is by creating cavities through the circuit board; axially leaded high voltage components may be conveniently mounted without additional assembly components while being fully encapsulated.Type: GrantFiled: February 6, 2008Date of Patent: January 14, 2014Assignee: LHV Power, Inc.Inventors: Kenneth E. Wing, Scott T. Carroll
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Publication number: 20140000941Abstract: In a method for integrating at least one electronic component into a printed circuit board or a printed circuit board intermediate product, the following steps are provided: providing a layer for at least temporarily supporting the electronic component, fixing the electronic component on the layer, arranging a conductive layer on the supporting layer with at least one cutout corresponding to the dimensions of the electronic component to be fixed, at least partly encapsulating or covering the component fixed on the supporting layer with an insulating material, exposing the electronic component, and at least partial regions of the conductive layer, which adjoins the component and is arranged on the supporting layer, and at least partly making contact between the electronic component and the conductive layer adjoining the component. Furthermore, a printed circuit board and a printed circuit board intermediate product having an integrated electronic component are provided.Type: ApplicationFiled: January 24, 2012Publication date: January 2, 2014Applicant: AT & S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Gerald Weidinger, Andreas Zluc, Johannes Stahr
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Publication number: 20140002998Abstract: An apparatus may include an electrical component body, where the electrical component body is operative to vary power during operation. The apparatus may also include a thermal component in contact with at least a portion of the electrical component body, in which the thermal component comprises a matrix material, and a thermal energy storage material embedded in the matrix material to absorb heat generated by the electrical component body. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Applicant: Intel CorporationInventors: David Pidwerbecki, Alexander B. Uan-Zo-li
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Patent number: 8613136Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.Type: GrantFiled: November 9, 2009Date of Patent: December 24, 2013Assignee: Ibiden Co., Ltd.Inventors: Hironori Tanaka, Kazuhiro Yoshikawa, Naoaki Fujii, Atsunari Yamashita
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Publication number: 20130329373Abstract: An implantable bio-compatible integrated circuit device and methods for manufacture thereof are disclosed herein. The device includes a substrate having a recess. An input/output device including at least one bio-compatible electrical contact is coupled to the substrate in the recess. A layer of hermetic bio-compatible, hermetic insulator material is deposited on a portion of the input/output device. An encapsulating layer of bio-compatible material encapsulates at least a portion of the implantable device, including the input/output device. At least one bio-compatible electrical contact of the input/output device is then exposed. The encapsulating layer and the layer of bio-compatible, hermetic insulator material form a hermetic seal around the at least one exposed bio-compatible electrical contact.Type: ApplicationFiled: June 6, 2012Publication date: December 12, 2013Inventors: Brian R. Smith, Tirunelveli S. Sriram, Bryan L. McLaughlin
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Publication number: 20130326872Abstract: A medical measurement device, such as an electronic thermometer, having a probe. The probe includes a molded plastic substrate having a conductive circuit pattern formed directly on its surface. The circuit pattern extends at least from a first end margin of the molded plastic substrate to a second end margin opposite the first. The device also includes a sensor mounted on the molded plastic substrate for detecting a physiological parameter, such as temperature. The sensor is positioned on the molded plastic substrate at the first end margin by at least one positioning element integrally formed in the substrate. The conductive circuit pattern provides an electrical connection between the sensor and a processor.Type: ApplicationFiled: July 1, 2013Publication date: December 12, 2013Inventors: James Harr, Joseph T. Gierer
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Patent number: RE44629Abstract: The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.Type: GrantFiled: November 30, 2004Date of Patent: December 10, 2013Assignee: Intel CorporationInventors: Suresh Ramalingam, Nagesh Vodrahalli, Michael J. Costello, Mun Leong Loke, Ravi V. Mahajan