By Molding Of Insulating Material Patents (Class 29/856)
  • Patent number: 6631555
    Abstract: A method includes populating components in a cavity of a substrate, disposing a polymer over the components and within the cavity. The polymer is cured and a thin film is formed on the polymer. In addition, a method includes forming an EMI shield within a medical device by depositing a thin film of metal on a surface within the medical device. The thin film of metal, of gold, aluminum, or copper, is formed by vapor deposition or sputtering.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: October 14, 2003
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Nick A. Youker, Ronald L. Anderson
  • Publication number: 20030188428
    Abstract: Removable mask films 303 are formed on the both sides of the substrate having the adhesive layer 302 by applying and drying a resin varnish 304 including a ultraviolet-absorbing agent, and fine through holes 306 are formed by using a third harmonics YAG solid-state laser light with a relatively short wavelength not longer than that in the ultraviolet range in such a way that the effects of such a residual strain as the conventional embodiment forming a removable mask film by a laminating process may be decreased as well as the more fine hole drilling compared with conventional embodiment using the carbon dioxide gas laser with a relatively long wavelength may be performed.
    Type: Application
    Filed: March 31, 2003
    Publication date: October 9, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Fumio Echigo, Hideki Higashitani, Daizo Andoh, Noritake Fukuda, Yasuhiro Nakatani, Tadashi Nakamura
  • Patent number: 6629351
    Abstract: An apparatus and a method for separating a cull from a molded part including a chip mounted on a tape circuit board are provided. The apparatus includes a cull support block for supporting a cull and a cull holder for clamping the cull. The cull holder is disposed above the cull support block. The apparatus further includes a frame support block for mounting a molded part and a frame holder for pressing the molded part against the frame support block to fix the molded part thereon. The frame support block is hinged on a first axis near the cull support block. The frame holder is hinged on a second axis near the cull support block. The apparatus also includes a pressing means configured to move downward against a distal end of the frame holder to cause the frame support block and the frame holder to rotate about the first and second axes, respectively, to separate the cull from the molded part.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: October 7, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Sung Lee, Byoung-Cheol Jeon
  • Patent number: 6629361
    Abstract: A wire capable of operating at high temperatures and a method of making the same is disclosed. The high temperature wire comprises fiberglass, which surrounds the conductor. The fiberglass insulates the conductor and enables it to operative at relatively high temperatures. The fiberglass is heat-treated without any additional, or in lieu of, other chemical treatment and is sufficiently frangible to be easily removable from the conductor. The frangible fiberglass may be easily stripped away from the conductor without leaving strands which need to be individually removed.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: October 7, 2003
    Assignee: Electrovations
    Inventor: Daniel Polasky
  • Patent number: 6625883
    Abstract: Disclosed is a bump structure, which has a hollow body, for electrically connecting a first member and a second member. Also disclosed is a method for making a bump structure, which has the steps of: preparing a molding plate with a concave mold to mold a bump-forming member; forming a conductive thin film so as to form a predetermined cavity in the concave mold of the molding plate; preparing a substrate to which the conductive thin film is to be transferred; and transferring the conductive thin film formed on the molding plate to the substrate.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: September 30, 2003
    Assignee: NEC Corporation
    Inventors: Koji Soejima, Naoji Senba
  • Patent number: 6625879
    Abstract: A method for making an electrically shielded housing for an electrical device includes the steps of at least partially forming an insert member having a non-conductive outer surface portion and a conductive inner surface portion, insert molding the at least partially formed insert member in a cavity of a non-conductive housing body member so that the conductive inner surface portion of the insert member is disposed adjacent an outer surface portion of the body member cavity and the non-conductive outer surface portion of the insert member forms a housing cavity. An electrical device received in the housing cavity is electrically shielded by the conductive inner surface portion of the insert member and insulated from the conductive inner surface portion of the insert member by the non-conductive outer surface portion thereof.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: September 30, 2003
    Assignee: Illinois Tool Works Inc.
    Inventors: Peter Michael Frederick Collins, Terry Dean Thomason, Ralph A. Hausler
  • Patent number: 6610162
    Abstract: A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: August 26, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Timothy J. Allen, Jerry M. Brooks
  • Publication number: 20030145461
    Abstract: A semiconductor device is disclosed which can prevent the leakage of resin and improve the production efficiency. The semiconductor device comprises a substrate, the substrate having plural connecting terminals formed around a recess and plural bump lands arranged side by side around the connecting terminals, a semiconductor chip disposed in the recess, plural wires for connecting pads on the semiconductor chip and the connecting terminals on the substrate with each other, a seal portion embedded in the recess, and plural ball electrodes provided on the bump lands of the substrate. A dummy wiring covered with solder resist is formed in an area between the plural connecting terminals and the plural bump lands on the substrate. According to this construction, a gap between a mold surface of an upper mold and the surface of the substrate, which gap is formed at the time of die clamping, is filled up with the dummy wiring and the solder resist which covers the dummy wiring.
    Type: Application
    Filed: October 25, 2002
    Publication date: August 7, 2003
    Inventors: Norihiko Kasai, Hiromasa Ohno
  • Patent number: 6602735
    Abstract: A lead frame for a semiconductor chip package includes a frame body and at least two chip-receiving windows formed in the frame body. Each chip-receiving window receives a respective integrated circuit chip therein. A plurality of internal connection leads are formed on the frame body adjacent to the chip-receiving windows, and are connected electrically to bonding pads on the integrated circuit chips in the chip-receiving windows such that internal electrical connection among the integrated circuit chips can be established via the internal connection leads. A plurality of external connection leads are formed on the frame body adjacent to at least one of the chip-receiving windows, and are connected electrically to the bonding pads on the integrated circuit chip in the adjacent chip-receiving window.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: August 5, 2003
    Assignee: Winbond Electronics, Corporation
    Inventor: Rong-Fuh Shyu
  • Patent number: 6593643
    Abstract: A semiconductor device lead frame made of copper or a copper alloy used for a resin sealing type semiconductor device, comprising a lead frame body made of copper or a copper alloy, a double-layer under plating film formed on the lead frame body and comprising a lower layer made of zinc or a copper-zinc alloy and an upper layer made of copper having a thickness of 0.02 to 0.4 &mgr;m and a precious metal plating film formed on at least a wire bonding portion of an inner lead of the copper upper layer of the under plating film. This lead frame is excellent in adhesion with a sealing resin, is free from contaminate a precious metal plating solution (particularly a silver plating solution), has a good appearance of the precious metal plating film, is excellent in corrosion resistance and moisture resistance, and has a good appearance and adhesion of an external solder plating film.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: July 15, 2003
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazumitsu Seki, Takashi Yoshie, Harunobu Sato
  • Patent number: 6588098
    Abstract: A system for manufacturing electronic device packages includes a conveyor with an adhesive work surface to support a predetermined array of external connectors for flip-chip bonding of dies thereto. After assembly, the dies with associated external connectors bonded thereto are encapsulated on a work surface of the conveyor whereby the work surface forms at least part of an inner surface of an encapsulating mold.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: July 8, 2003
    Assignee: Semiconductor Components Industries LLC
    Inventors: Boon Huat Lim, Saat Shukri Embong, Kevin J. Theseira, Kenneth Teik Kheong Low
  • Publication number: 20030110630
    Abstract: This invention provides a material for a multi-layer circuit board, excellent in insulating property and burying properties and free from occurrence of cracks, a production method, and a multi-layer circuit board using the insulating material. The invention provides an insulating material having a curable composition layer wherein the curable composition layer contains 0 to 50 pieces/cm2 of foreign matter having particle sizes falling within a range of 30 to 50 &mgr;m, a production method, and a production method for a multi-layer circuit board using the insulating material.
    Type: Application
    Filed: September 30, 2002
    Publication date: June 19, 2003
    Inventors: Kazuyuki Onishi, Toshiyasu Matsui, Hiroshi Kurakata, Masahiko Sugimura
  • Publication number: 20030088976
    Abstract: A method and device for providing a gate blocking material. Specifically, a method for molding a substrate having known good and bad sites thereon, by blocking the gate area of the bad sites during the molding process. A blocking material or an injection pin are used to interrupt the flow of molding compound through an injection molding system, and thereby prevent molding compound from flowing onto the known bad substrate sites.
    Type: Application
    Filed: December 24, 2002
    Publication date: May 15, 2003
    Inventors: Bret K. Street, Casey L. Prindiville, Cary Baerlocher
  • Patent number: 6551859
    Abstract: Techniques for improving the manufacture and structure of leadframe chip scale packages and land grid array packages are described. One aspect of the invention pertains to a method for patterning a conductive substrate, which is utilized to form a packaged semiconductor device, wherein a metallic barrier layer and a second metallic layer are utilized as an etching resist. A method, according to another aspect of the invention pertains to covering a metallic barrier layer and second metallic layer with a etch resistant cap such that the etch resistant cap is used as a etching resist. In another aspect of the present invention, a method for treating a conductive leadframe with a CZ treatment is disclosed. In yet another aspect of the present invention, techniques relating to locking grooves within the studs of a studded leadframe are disclosed.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: April 22, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Shaw Wei Lee, Thanh Lequang, Wayne W. Lee, Glenn Narvaez, William Jeffery Schaefer
  • Patent number: 6519822
    Abstract: A method for producing an electronic component includes placing an enclosed frame on a baseplate. A chip is provided to be fitted within the frame, forming a first given space between the chip and the baseplate and forming a second given space between the chip and the frame. The first given space is enclosed in a hermetically sealed manner by pressing a film onto the chip, except on a surface of the chip facing the baseplate, such that the film surrounds the chip and at least reaches the surface of the baseplate. The second given space is filled with a casting compound. The film is then removed at surface regions of the film being free of the casting compound. Finally, a cover composed of an electrically conductive material is applied on the chip, the casting compound and the frame.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: February 18, 2003
    Assignee: EPCOS AG
    Inventors: Alois Stelzl, Hans Krüger
  • Publication number: 20030029010
    Abstract: A method is provided for making a backing layer for an ultrasonic matrix array transducer useful in medical imaging and the like. A conductive grid is provided which includes a plurality of micro-contacts each joined together by a common base so that spaces are provided between the free ends of the contacts. The method includes placing the grid in a mold, filling the mold with an acoustically absorbent material such that the absorbent material fills the spaces between the contacts, curing the material in the mold so as to form a block formed by the cured absorbent material and the grid, and releasing the block from the mold. The common base is removed by, e.g., machining the grid, so as to separate the contacts from one another within the block. Further machining is used to expose the opposite ends of micro-contacts so that a like number of contact faces are provided at opposed surfaces of the backing layer so formed. The grid can be prepared in several ways.
    Type: Application
    Filed: October 21, 2002
    Publication date: February 13, 2003
    Inventor: Flesch Aime
  • Publication number: 20030030964
    Abstract: During molding of a brush holder which is a resin-molded part in an alternator, a capacitor component is molded integrally with a capacitor positive electrode terminal and a capacitor negative electrode terminal joined by crimping to a positive terminal and a negative terminal, respectively. The capacitor component is thereby embedded in a first resin portion.
    Type: Application
    Filed: July 8, 2002
    Publication date: February 13, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Atsushi Oohashi, Yoshihito Asao, Hideki Morikaku
  • Patent number: 6518098
    Abstract: An integrated circuit device has a heat spreader attached to each of the major outer encapsulant surfaces. One or both of the heat spreaders has a pair of end posts configured for insertion into through-holes in a substrate to position and support the device during and following the outer lead solder reflow step at board assembly. The heat spreaders provide high heat dissipation and EMR shielding, and may be connected to the substrate ground to become ground planes.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: February 11, 2003
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 6501031
    Abstract: A multi-layer electronic circuit board design 10 having a core member 12, a pair of dielectric layers 14, 16 disposed thereon, and a first circuit portion 20 which is coupled to the dielectric layer 14 and core member 12 using a layer of adhesive material 18. Circuit board design 10 further having selectively formed “blind” apertures, vias or cavities 22 formed through the first circuit portion 20, dielectric layer 14, and adhesive layer 18, thereby exposing core member 12.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: December 31, 2002
    Assignee: Visteon Global Tech., Inc.
    Inventors: Andrew Z. Glovatsky, Jay D. Baker, Robert Edward Belke, Myron Lemecha, Richard Keith McMillan, Thomas B. Krautheim
  • Patent number: 6500698
    Abstract: A stacked semiconductor chip package includes: a substrate including a plurality of conductive pads; a first semiconductor chip mounted on the substrate; and electrically connected to the conductive pads; a plurality of electrical leads provided about the substrate; a first molding part for sealing the substrate and the first semiconductor chip; a second semiconductor chip mounted on an upper surface of the first molding part and electrically connected to the electrical leads; and a second molding part for sealing the second semiconductor chip, the second conductive wires and a portion of the leads.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: December 31, 2002
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Myoung-Jin Shin
  • Publication number: 20020186552
    Abstract: The invention relates to a module component having chip components buried in a circuit board, and a method of manufacturing the same, and more specifically it relates to a module component capable of obtaining desired circuit characteristics and functions stably if the size of the component is reduced, being produced very efficiently, and suited to machine mounting, and a method of manufacturing the same.
    Type: Application
    Filed: August 7, 2002
    Publication date: December 12, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Suzushi Kimura, Tsuyoshi Himori, Koji Hashimoto
  • Patent number: 6489183
    Abstract: Printed tape is used to form a leads on chip (LOC) ball grid array (BGA) semiconductor device. Leads for a plurality of devices may be applied simultaneously. Bond wires, glob top encapsulant, and the ball grid arrays for the devices may be formed in single process steps. A low temperature curing adhesive material may be used to reduce the effects of differential thermal expansion between the tape and surface of the wafer. In another embodiment of the invention, anisotropically conductive adhesive material is used to connect bond pads on a wafer to leads printed on a tape.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: December 3, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Patent number: 6489182
    Abstract: A chip size package is fabricated by: etching portions of a copper film on an insulating film tape, forming a solder mask on the insulating film tape excluding inner holes of metal pattern units and four edge portions of the copper film, electroplating, attaching the semiconductor chip, sealing the semiconductor chip with an epoxy, etching to expose the chip pads, electrically connecting the chip pads by wires, eliminating portions of the copper film remaining at the four edge portions and cutting the insulating film tape into individual units.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: December 3, 2002
    Assignee: Hynix Semiconductur, Inc.
    Inventor: Yong-Tae Kwon
  • Patent number: 6490501
    Abstract: A monitoring and control system for use in curing composite materials includes a model for a workpiece being cured. The model calculates current internal states of the workpiece and predicts, based upon past and current states of the workpiece, future states of the cure process. These future states are represented as virtual inputs to the controller, which controls operation of the cure process based upon both real and virtual inputs. Cure rates are affected by both external temperatures and internal heat generated by the curing process itself. The internally generated heat is considered by the model when calculating current states and predicting future states. By projecting the cure state into the future, problems caused by high cure rates can be avoided. In addition, pressure can be optimally controlled in response to estimated internal material state.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: December 3, 2002
    Assignee: Bell Helicopter Textron Inc.
    Inventor: Arven H. Saunders
  • Patent number: 6485334
    Abstract: Connector terminals 13 connected to ends of respective electric wires 12 are inserted into an electric wire insertion section 11b formed in a housing body 11 of a waterproof connector 10. The connector terminals 13 are attached to respective terminal attachment sections 11a. The connector comprises a plug 14 which is molded on the outer peripheral surfaces of the electric wires 12 situated in the electric wire insertion section 11b and which is removably fitted into the electric wire insertion section 11b with a slight gap between the inner peripheral surface of the electric wire insertion section 11b and the plug 14; and a resiliently-deformable annular sealing body 15 which is retained in a retention groove formed along an outer peripheral surface of the plug 14 and which is brought into intimate contact with the inner peripheral surface of the electric wire insertion section 11b.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: November 26, 2002
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Yasuhiro Hattori, Hirotaka Yamada
  • Publication number: 20020148112
    Abstract: An encapsulation method for a ball grid array (BGA) semiconductor package, includes: adhering one sided adhesive tape to an upper portion of the semiconductor package after performing a wire bonding; carrying out a molding by using a mold having a groove of a certain size inside; and removing the one side adhesive tape after completing the molding, whereby a flash is prevented from occurring during the BGA encapsulation process.
    Type: Application
    Filed: June 17, 2002
    Publication date: October 17, 2002
    Applicant: LG Semicon Co., Ltd.
    Inventors: Seong-Jae Heo, Chi-Jung Song
  • Patent number: 6455354
    Abstract: An apparatus and method for preventing damage to tape attachment semiconductor assemblies due to encapsulation filler particles causing damage to a semiconductor die active surface and/or to a corresponding semiconductor substrate surface by providing an adhesive tape which extends across areas of contact between the semiconductor die active surface and the semiconductor substrate. The present invention also includes extending the adhesive tape beyond the areas of contact between the semiconductor die active surface and the semiconductor substrate to provide a visible surface of visual inspection of proper adhesive tape placement.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: September 24, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Tongbi Jiang
  • Patent number: 6451628
    Abstract: An object of the present invention is to provide a method of manufacturing a semiconductor device which enables a decrease in mounting area on a printed circuit board and an increase in space efficiency on the printed circuit board.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: September 17, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takayuki Tani, Takao Shibuya, Haruo Hyodo
  • Patent number: 6428357
    Abstract: An electrical connector assembly has an overmolded housing which is preferably injection-molded of thermoplastic resilient or elastic material onto a base housing containing an electrical connector. A strain relief is preferably integral with the overmolded housing. A pre-mold housing is preferably molded onto the base housing before the overmold housing.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: August 6, 2002
    Assignee: Amphenol Corporation
    Inventors: Thomas J. Dolinshek, Daniel D. Robinson, Walter Budd, Scott Wilton
  • Patent number: 6423581
    Abstract: An encapsulated integrated circuit is provided including a semiconductor die, a printed circuit board, and an encapsulant. The printed circuit board is conductively coupled to the semiconductor die and comprises a laminate defining first and second major faces. The laminate includes a solder resist layer, an electrically conductive layer, and a bismaleimide triazine resin laminate including a selected laminated layer and an adjacent laminated layer. The electrically conductive layer is interposed between the solder resist layer and the underlying substrate. The selected laminated layer is disposed closer to the first major face than the adjacent laminated layer. The laminate includes at least one void formed therein so as to extend from one of the major faces through the solder resist layer and the electrically conductive layer at least as far as the adjacent laminated layer.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Brand
  • Patent number: 6399425
    Abstract: In one aspect, the invention includes a method of encapsulating a semiconductor device, comprising: a) providing a semiconductor device; b) providing a dispensing apparatus having a plurality of dispensing orifices proximate the semiconductor device; and c) dispensing a liquid encapsulating material through the plurality of orifices and over the semiconductor device. In another aspect, the invention includes a method of forming an electronic package, comprising: a) providing a circuit board having a circuit pattern; b) joining a plurality of semiconductor devices to the circuit board in electrical connection with the circuit pattern; c) providing a dispensing apparatus having a plurality of dispensing orifices proximate the semiconductor devices; d) simultaneously dispensing liquid encapsulating material through at least two of the plurality of orifices and over at least two of the semiconductor devices; and e) curing the liquid encapsulating material.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: June 4, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. Brand, Scott Gooch
  • Patent number: 6395584
    Abstract: A flat plate mold with special treatment or a metallic flat plate mold is adopted to flatten the resin painted over on IC chips during package dispensing process, such that it is able to maintain a consistent flatness of the surface of IC products after dispensing for laser or ink marking. And heat sinks can be attached to the flat plate mold to increase the heat-dissipating rate of IC products after dispensing.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: May 28, 2002
    Assignee: FICTA Technology Inc.
    Inventors: Chi-Hsing Hsu, Chin-Hsing Chung, Wen-Fu Hsu
  • Patent number: 6395374
    Abstract: A platform is provided for the manufacture of microwave, multilayer integrated circuits and microwave, multifunction modules. The manufacturing process involves bonding fluoropolymer composite substrates into a multilayer structure using fusion bonding. The bonded multilayers, with embedded semiconductor devices, etched resistors and circuit patterns, and plated via holes form a self-contained surface mount module. Film bonding, or fusion bonding if possible, may be used to cover embedded semiconductor devices, including embedded active semiconductor devices, with one or more layers.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: May 28, 2002
    Assignee: Merrimac Industries, Inc.
    Inventors: Joseph McAndrew, James J. Logothetis
  • Patent number: 6313524
    Abstract: A chip module has a contact area disposed on its outer side formed of a plurality of essentially flat contact elements of electrically conductive material insulated from one another. At least one semiconductor chip having one or more integrated semiconductor circuits that are electrically connected to the contact elements of the contact area via bonding wires. The contact elements of the chip module are formed by a prefabricated lead frame for supporting the at least one semiconductor chip and have on two opposing sides of the chip module outwardly offset terminals arranged in rows next to one another. The outwardly offset terminals are provided for surface mounting the chip module on the mounting surface of an external printed circuit board or an external circuit board substrate.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: November 6, 2001
    Assignee: Infineon Technologies AG
    Inventors: Frank Pueschner, Michael Huber, Peter Stampka, Jürgen Fischer, Josef Heitzer
  • Patent number: 6295221
    Abstract: A method of manufacturing a small, thin card-type storage device is capable of easily manufacturing a frame for the storage device from a variety of resin materials without molding a very thin recessed bottom of the supporter. The method prepares a card-type support frame member from resin and a sheet material, cuts the sheet material into the size of the support frame member, to form a support sheet, bonds the support sheet to a bottom surface of the support frame member, to form a frame, and fits a memory module to be fixed in an opening of the support frame member in the frame, thereby completing the card-type storage device.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: September 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Iwasaki, Osami Suzuki
  • Patent number: 6277225
    Abstract: A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: August 21, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Timothy J. Allen, Jerry M. Brooks
  • Publication number: 20010011415
    Abstract: A nozzle assembly for use in injection molding comprises a pair of spacers acting between the manifold and either a cover plate or a hot runner plate of an injection molding machine to apply a contact pressure between the nozzle body melt channel and the manifold melt channel to achieve a seal therebetween. The resilience of the spacers result in an increased operational temperature range for the nozzle assembly, the contact pressure being generated and/or maintained over the range of the operational temperatures. An additional advantage is provided in that the nozzle assembly is compact and can be closely spaced with similar nozzle assemblies to achieve center spacings as small as eight millimeters. The assemblies can be mounted and/or removed from the cavity of the manifold plate, and/or changing of the nozzle heater elements, without requiring removal of the mold from the injection mold machine.
    Type: Application
    Filed: December 15, 2000
    Publication date: August 9, 2001
    Inventor: Jacek Kalemba
  • Patent number: 6269539
    Abstract: A method for fabricating a connector for coupling with a counter connector having an array of pairs of contacts therein includes providing an insulated housing having an array of openings receiving a plurality of first contact modules each having first and second isolated contacts and a second contact module having isolated first and second conducting members respectively having first and second contacts and a terminal, and a third contact and a second terminal, selectively inserted into corresponding openings of the insulating housing such that each of the respective first and second contacts of the first contact modules are connected with the corresponding contact of the counter connector while maintaining the first and second contacts electrically isolated from each other.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: August 7, 2001
    Assignee: Fujitsu Takamisawa Component Limited
    Inventors: Norihiro Takahashi, Fumio Kurotori, Hideo Miyazawa, Osamu Daikuhara, Kazuyuki Futaki, Hiroyuki Suzuki, Takahiro Yoshiike, Kazuhiko Ikeda
  • Patent number: 6259606
    Abstract: An electronic card for electromagnetic data exchange, the electronic card including an electronic circuit (2) which is contained in a housing (1), the housing (1, 1′) being provided with a bottom element (10) and a top element (20), the electronic circuit (2) being contained between inner surfaces (10′, 20′) of the bottom and top elements (10, 20). At least one of the bottom element (10) and the top element (20) is provided with at east one recess (11, 12, 21, 22, 11a, 12a, 21a, 22a), into which the electronic circuit (2) is inserted, the shape (11′, 12′, 21′, 22′, 11a′, 12a′, 21a′, 22a′) of the recess (11, 12, 21, 22, 11a, 12a, 21a, 22a) corresponding to an outer shape (2a′, 2b′, 2c′; 2a′, 2c′) of the electronic circuit (2), the electronic circuit (2) being at least partially covered by the top element (20), and the housing (1; 1′) being encased by a sheathing (50) made of plastics.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: July 10, 2001
    Inventor: Peter Bunert
  • Patent number: 6256881
    Abstract: There is provided a new and improved method for connecting electrical components in a mold with a molding press. The method includes the steps of connecting electrical leads to coded electrical connectors secured to the mold; connecting electrical connectors to detachable electrical cables; and extending and detachably connecting electrical cables to coded connectors of a junction panel or box. The electrical connectors at the mold may be color-coded and/or shape-coded as to pins or keys on the connectors; and likewise, the cables and the electrical connectors at the junction box may also be similarly color-coded and/or shape-coded.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: July 10, 2001
    Inventor: Glenn Starkey
  • Patent number: 6256549
    Abstract: The present invention provides a computerized database comprising a first table representing a list of part numbers. The database provides computerized links between individual part numbers and associated manufacturing process data for different process steps for that part number. Rather than correlate data by hand, a user may click on a process step for a particular part number to instantly and accurately retrieve that data. Manufacturing process data may include, for example, backgrind process data, wire binding data, either in numerical or graphical form, testing parameters, packaging data, and labeling data. The database system of the present invention may be used to automatically program various process equipment in an assembly facility with appropriate process data to automatically process finished semiconductor wafers into packaged semiconductor circuits.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: July 3, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Bernadette P. Romero, Carl H. Fong
  • Patent number: 6195263
    Abstract: In an electronic control unit, a pad portion thereof is firmly fixed to a terminal plate and vibration of the terminal plate under supersonic vibration is prevented so as to secure the bonding strength between the terminal plate and the wire during wire bonding. One lead portion of each terminal plate is connected to a pin of the connector and another lead portion is wire bonded to the terminal of the circuit substrate. The leads have bent portions extending from an exposed surface to be bonded in opposite directions to be embedded in the pad portion of the case such that the lead portion of the terminal plate is firmly fixed to the case.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: February 27, 2001
    Assignee: Aisin AW Co., Ltd.
    Inventors: Koji Aoike, Naotaka Murakami, Hiroki Takata, Osamu Yamato
  • Patent number: 6099677
    Abstract: A platform is provided for the manufacture of microwave, multilayer integrated circuits and microwave, multifunction modules. The manufacturing process involves bonding fluoropolymer composite substrates into a multilayer structure using fusion bonding. The bonded multilayers, with embedded semiconductor devices, etched resistors and circuit patterns, and plated via holes form a self-contained surface mount module. Film bonding, or fusion bonding if possible, may be used to cover embedded semiconductor devices, including embedded active semiconductor devices, with one or more layers.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: August 8, 2000
    Assignee: Merrimac Industries, Inc.
    Inventors: James J. Logothetis, Joseph McAndrew
  • Patent number: 6072312
    Abstract: An encapsulated transducer (10) includes an injection molded encapsulation (20) having a front end (22) and a back end (24). The encapsulation (20) is a monolith of cured moldable material ensconcing a sensing element (90) proximate the front end (22) and a portion of an information transmitting medium (120) emanating from the back end (24). A component alignment preform (40) operatively couples the sensing element (90) with the information transmitting medium or cable (120). The component alignment preform (40) includes a front ferrule (70) and a rear ferrule (80) bonded thereto and linearly spaced apart along a long axis "A". The component alignment preform (40) further includes an annular recess (44) in which the sensing element or coil (90) is placed so that it is linearly spaced and aligned along the common long axis "A" in which the front and rear ferrules (70), (80) are aligned.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: June 6, 2000
    Assignee: Bently Nevada Corporation
    Inventor: Dave Van Den Berg
  • Patent number: 6052879
    Abstract: A method for embedding piezoelectric ceramic transducers in thermoplastic composites. The piezoelectric ceramic transducer to be embedded in a graphite/PEEK composite is first bonded with two fine silver wires for electrical connection, one on each major surface. The bonding agent is a high temperature conductive adhesive compound, such as a silver/glass frit. The fusing of the frit bonding agent is done in an over at a high temperature (i.e. 600.degree. F. or higher) for 5 to 10 minutes. Bonds are applied at several discrete spots on the zig zag wire which relieves thermal stresses induced during cooling due to a mismatch of the coefficient of thermal expansion between the ceramic material and the wire. After the connecting wires are attached, the wires and transducer are wrapped with several plies of insulating glass/PEEK cloth to prevent electrical shorting between the two silver wires through the graphite/PEEK host.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: April 25, 2000
    Assignee: McDonnell Douglas Corporation
    Inventors: Shu-Yau Wu, Creed E. Blevins
  • Patent number: 5951804
    Abstract: A method for simultaneously manufacturing chip-scale packages employing a lead frame strip having a plurality of lead frames. The method includes the steps of forming the lead frame strip and the plurality of TAB tapes, and then simultaneously bonding bottom surfaces of parallel leads and tie bars of each of the respective lead frames to a top surface of the TAB tape. A plurality of chips are attached to the top surface of the TAB tape and the chips are electrically connected to contact leads formed on the TAB tape. The chips and electrical connections are then encapsulated with a molding resin to form individual packages. The individual packages are then separated from the lead frame strip.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: September 14, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Do Kweon, Kwang Soo Kim
  • Patent number: 5926952
    Abstract: In a method of producing a connector in which a metal terminal is supported by a core, and then a resin is molded around the core: the metal terminal is covered by a tubular member into which the metal terminal can be inserted, and a tubular distal end edge portion of the tubular portion is pressed against a surface of the core to thereby seal the metal terminal; and the resin is molded around the core.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: July 27, 1999
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventor: Katsuya Ito
  • Patent number: 5878485
    Abstract: A method for fabricating a carrier for testing an unpackaged semiconductor die is provided. The carrier includes a carrier base for supporting the die; an interconnect for establishing a temporary electrical connection with the die; and a force distribution mechanism for biasing the die and interconnect together. In an illustrative embodiment the carrier is formed with a laminated ceramic base. The ceramic base includes internal conductive lines that are wire bonded to the interconnect and metal plated external contacts that are connected to external test circuitry. In an alternate embodiment the carrier is formed with an injection molded plastic base and includes 3-D circuitry formed by a metallization and photolithographic process. In either case, the carrier is adapted for testing different die configurations by interchanging different interconnects.
    Type: Grant
    Filed: March 13, 1996
    Date of Patent: March 9, 1999
    Assignee: Micron Technologoy, Inc.
    Inventors: Alan G. Wood, Warren M. Farnworth, David R. Hembree
  • Patent number: 5754398
    Abstract: A circuit-carrying automotive component and a method of manufacturing the same are provided. In a preferred embodiment of the invention, the component includes a substrate made from a polymer that is molten at a predetermined elevated temperature. The component further includes a circuit board which defines an aperture therethrough adapted to receive the molten polymer at the elevated temperature and a fastener formed from the molten polymer through the aperture. The fastener is integral with the substrate and mechanically secures the circuit board to the substrate. The circuit board is made from a material that is resistant to fusing with the molten polymer at the elevated temperature.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: May 19, 1998
    Assignee: Ford Motor Company, Inc.
    Inventors: Andrew Z. Glovatsky, Alice Zitzmann
  • Patent number: RE37413
    Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: October 16, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Gi Bon Cha