Abstract: A method for inspecting a semiconductor memory having nonvolatile memory cells using ferroelectric capacitors is disclosed which comprises, after shelf-aging the ferroelectric capacitor in a first polarized state, the steps of: (a) writing a second polarized state opposite to the first polarized state; (b) shelf-aging the ferroelectric capacitor in the second polarized state; and (c) reading the second polarized state. The temperature or voltage in the step (a) is lower than the temperature or voltage in the step (c). This method for inspecting a semiconductor memory enables to evaluate the imprint characteristics in a short time.

Abstract: A system for detecting the location of arc faults in an aircraft electrical wiring arrangement is provided. The system comprises a controller, operable to generate a test signal and a directional coupler for coupling the test signal into electrical wiring and for coupling reflected test signals from the electrical wiring to the controller. The electrical wiring comprises one or more wire under test and the controller is further operable to detect test signals reflected from arc faults in the wire under test and to analyse reflected test signals in order to determine one or more arc fault position therefrom. The wire under test may be live and testing can be performed without the need to use invasive in-line components.

Abstract: A sensor device determines a value based on a sensed parameter by applying a voltage across two voltage terminals of a sensor. In response, the sensor provides an electrical signal representative of a sensed parameter to a controller via a pair of conductors. The controller samples the electrical signal to determine the value. In addition, the controller alternates the polarity of the voltage applied to the voltage terminals, thereby reducing the risk of damage to the conductors due to ion drift.

Abstract: Apparatus, systems, and methods for testing SAS cables by applying a signal to one end of a SAS cable, receiving the signal from another end of the SAS cable, and generating an output of information relating to the testing. The testing apparatus may test one or more configuration characteristic of the SAS cable, including, for example a crossover status, a polarity status of transmit (“TX”) wires, and a polarity status of receive (“RX”) wires.

Abstract: A method is provided for visual inspection of an array of interferometric modulators in various driven states. This method may include driving multiple columns or rows of interferometric modulators via a single test pad or test lead, such as test pad, and then observing the array for discrepancies between the expected optical output and the actual optical output of the array. This method may particularly include, for example, driving a set of non-adjacent rows or columns to a state different from the intervening rows or columns and then observing the optical output of the array.

Abstract: In a method and system of detecting abnormality in an imaging device, multiple digital data are received in sequence from the imaging device via at least one data output pin. The multiple digital data correspond respectively to multiple pixel data. Subsequently, the multiple digital data for a specific pin are compared to determine whether they are, or how many of them are, the same. Accordingly, the specific pin is determined as abnormal when the number of the same digital data exceeds a predetermined value.

Abstract: Methods and systems using Pade' Approximant expansion ratios provide mappings between nonlinear sensors and a more linear output domain. The method includes a method of converting an input digital signal having a nonlinear dependency on a physical variable into an output digital signal that exhibits a substantially linear dependency with respect to the variable is disclosed. The method includes: (a) multiplying the input digital signal by a variable multiplying factor to thereby generate a multiplied digital version of the input signal; (b) adding to the multiplied digital version of the input signal, a predefined digital offset signal to thereby produce the output digital signal; (c) multiplying the output digital signal by a predefined feedback gain correction factor to thereby produce a digital feedback signal; (d) using the digital feedback signal to produce the variable multiplying factor.

Abstract: Methods are provided for reducing interference from stray currents in buried pipelines/metal structures during MEIS testing or other current-sensing applications in the pipeline. Methods are also provided for measuring bulk complex electrical impedance between a buried pipe and the soil, thereby rendering an indication of the quality of the anti-corrosive coating. Methods are also provided for measuring the complex propagation constant of AC voltages propagating along an attenuative pipeline. This information is useful for assessing the general condition of the anti-corrosive coating involved, or to enhance MEIS inspection of the pipeline.

Abstract: An overhead power transmission line system includes detector circuitry to detect a flashover event on a power line conductor in response to test over voltage excitations applied to the power line conductor applied. Processing circuitry establishes an operational voltage level for the power line conductor taking into account the lowest applied test over voltage excitation that causes a flashover event.

Abstract: A semiconductor integrated circuit having a test circuit for collecting test data at any time based on interaction with an external source is provided. A communication circuit receives a data frame that is transferred to a data buffer. Data portions are transferred to a test unit of a test circuit. A counter starts a count operation based on a system clock when count information is transferred. If one of the data portions indicates the transferred data is test data, and another portion indicates a data collection specification command, the test unit outputs decoded address data to interact with a circuit-under-test when the counter completes the count operation based on another portion of the frame. A data buffer is supplied with the address data to facilitate storage of the data transferred from the circuit-under-test.

Abstract: Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern determined according to a test signal to be supplied to the device under test; a timing signal generating section that generates a timing signal indicating a timing for supplying the test signal to the device under test; a digital filter that filters the test pattern to output a jitter control signal representing jitter corresponding to the test pattern; a jitter injecting section that injects the timing signal with jitter by delaying the timing signal according to the jitter control signal; and a waveform shaping section that generates the test signal formed according to the test pattern, with the timing signal into which the jitter is injected as a reference.

Abstract: A circuit arrangement, system, and method to test a device with a plurality of pins for electric overstress and transient induced latch-up characteristics. The circuit arrangement includes an inverting operational amplifier with a unity gain to receive a triggering signal and supply an inverted signal to a power amplifier. The power amplifier transforms the inverted signal into a test signal, which is received by a ratio circuit. The test signal is further operable to test the electric overstress and transient induced latch-up characteristics of the device. The ratio circuit transforms the test signal into a ratio signal. The ratio signal has a voltage magnitude that corresponds to the current magnitude of the test signal. The test signal and ratio signal are measured to determine if, during testing, the device or a component of the device has failed.

Abstract: Aspects of a method and system for matching an integrated FM system to an antenna utilizing on-chip measurement of reflected signals are provided. In this regard a portion of a signal output by an integrated FM radio transmit block and reflected by an antenna may be routed to an on-chip signal analyzer. Accordingly, measurements of the reflected signals may be utilized to configure a matching network in order to provide a best impedance match between the FM radio and the antenna. In this regard, a best impedance match may maximize radiation efficiency and/or radiated power. Additionally, the configuration of the matching network may incorporate a correction algorithm/offset experimentally determined via a calibration utilizing external components.

Abstract: A method for fabricating pipeline coating samples containing synthetic disbonds to be used in estimating a condition of a coating of an underground pipeline. The method includes the steps of providing a section of a pipe having a predetermined diameter and length; installing end caps on opposing ends of the pipe section, each end cap having an electrical connection extending therefrom; applying a material having a low dielectric coefficient around the pipe segment between the end caps to simulate an air-filled disbond; varying the coverage area of material to simulate various disbond sizes; and wrapping the pipe segment and end caps with tape to cover the material having a low dielectric coefficient.

Abstract: An evaluation board, on which is mounted a chip to be evaluated is provided. Particularly, the evaluation board includes a monitoring window for monitoring a power supply part, a ground part, and a surface of the chip, a first signal input part for inputting signals to the chip, and a second signal input part for inputting signals to the chip, wherein the second signal input part is placed as to sandwich said monitoring window between itself and the first signal input part.

Abstract: The present invention is related to a system and a method for detecting a location of fault in a cable.

Abstract: A system determining whether the shielding on a shielded signal or power cable has been compromised without the need of detaching the cable. A special-made cable is used with a dedicated shielding surveillance conductor and a process for injecting a known current on the shield of the cable and monitoring a voltage on the shielding surveillance conductor.

Abstract: Methods and systems for auto detecting and auto switching antennas in a multi-antenna FM transmit/receive system are disclosed and may include detecting when an external antenna may be coupled to an external port of the wireless device and utilizing the external antenna for transmitting and/or receiving FM signals. The decoupling of an external antenna from an external port may be detected, which may cause the FM radio transmitter/receiver to be configured to transmit and/or receive FM signals utilizing antennas internal to the wireless device. One or more test signals, which may include AC signals, may be generated within the chip for detecting whether an external antenna may be coupled to an external port. A reflected signal from an external port may be measured and compared to a prestored value corresponding to a reflection due to an open circuit at the one or more external ports of the wireless device.

Abstract: A physical layer module (PHY) of a network device includes a control module and a cable-test module. The control module selectively generates a cable-test enable signal to test a cable including four pairs of twisted wire. The cable-test module tests the cable based on the cable-test enable signal. The cable-test module transmits test signals on the four pairs at a first time and receives return signals. The cable-test module determines that the cable is not faulty when the return signals received on first and second pairs of the four pairs have an amplitude less than a first predetermined amplitude, and when the return signals received on third and fourth pairs of the four pairs have an amplitude greater than a second predetermined amplitude and are received substantially contemporaneously.

Abstract: An automatic multi-cable continuity tester. The multi-conductor electrical continuity tester includes a controller that is configured to generate a first serial stream of input test signals. The first serial stream of input test signals includes a plurality of signals equal in number to a plurality of conductors in a cable. A data input module is configured to convert the first serial stream of input test signals into a first parallel stream of test signals. A data output module is configured to receive and convert the first parallel stream of test signals to a first serial stream of output test signals.

Abstract: Methods are provided for reducing interference from stray currents in buried pipelines/metal structures during MEIS testing or other current-sensing applications in the pipeline. Methods are also provided for measuring bulk complex electrical impedance between a buried pipe and the soil, thereby rendering an indication of the quality of the anti-corrosive coating. Methods are also provided for measuring the complex propagation constant of AC voltages propagating along an attenuative pipeline. This information is useful for assessing the general condition of the anti-corrosive coating involved, or to enhance MEIS inspection of the pipeline.

Abstract: Method and apparatus for simulating electrical pipe-to-soil impedance of a coated segment of a pipeline includes simulating a current injection point to a buried pipe section, simulating a first output signal from a magnetometer positioned at a first location over the buried pipe section, simulating a second output signal from a magnetometer positioned at a second location over the buried pipe section, simulating bonding of pipe coating of the pipe section, and simulating soil resistance of a soil environment surrounding the buried pipe section. The invention includes both field-test simulation with calibration pipe samples, and bench-test simulation using electronic simulation of the pipe coating. The simulations may be used for test and general calibration of MEIS pipeline coating inspection systems.

Abstract: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.

Abstract: Systems and methods for determining the configuration of a connection between two devices by measuring an electrical characteristic are provided. Using the measured electrical characteristic, a device is able to select an appropriate communication interface, such as serial, Universal Serial Bus (USB), FireWire, parallel, PS/2, etc., and configure itself appropriately. Systems and methods which determine the physical orientation of a connector with respect to another connector may also be provided alone or in combination with such systems and methods for selecting communication interfaces. The physical orientation of a connector can be determined by measuring an electrical characteristic and a device can then configure itself appropriately. In accordance with the principles of the present invention, device designs can decrease in size and cost as well as simplify operation for the end-user.

Abstract: Methods and systems using Pade' Approximant expansion ratios provide mappings between nonlinear sensors and a more linear output domain. The method includes (a) generating a variably amplified version of the input signal in accordance with a produced and variable gain defining signal; (b) generating an output signal that exhibits a substantially linear dependency from a sum of a supplied offset signal and the variably amplified version of the input signal; (c) multiplying the output signal by a supplied gain correction factor to produce a feedback gain correction signal; and (d) using the feedback gain correction signal to produce the variable gain defining signal.

Abstract: A test signal is supplied to a test switch provided between a D/A converter for selecting and outputting a gray scale voltage of the driving circuit and an amplifier for amplifying and supplying an output voltage at the D/A converter to set a test mode, and an output voltage of the D/A converter is directly measured by a measuring device through the test switch to measure an ON resistance of a gray scale voltage selection circuit of the D/A converter.

Abstract: A test circuit according to the present invention includes: a synthesis circuit that synthesizes a first test result signal output from a first test target circuit in response to a test instruction, and a second test result signal output from a second test target circuit in response to the test instruction; an inter-block delay generation circuit that delays the second test result signal with respect to the first test result signal; and a test result holding circuit that holds a synthesized test result signal every predetermined timing, the synthesized test result signal being output from the synthesis circuit.

Abstract: A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.

Abstract: To provide a signal transmitting/receiving apparatus etc. where a cable length can be measured by using a general-purpose cable, without using an interface. A differential transmission circuit by the present invention includes a signal output circuit sending a high-speed differential signal and a pulse wave; a signal input circuit including a terminating resistor; a bias controller controlling a bias voltage on a transmission path; a terminating resistance controller disconnecting the terminating resistor on sensing a bias voltage and connecting it on sensing no bias voltage, by a bias sensing circuit; a sensing input circuit sensing a pulse wave reflected at the signal input circuit; and an output setting controller setting an electric characteristic of a signal outputted from the signal output circuit by a propagation time from sending the pulse wave by the signal output circuit to receiving the reflected pulse wave by the sensing input circuit.

Abstract: A method for calibrating a hands-free system is provided. The hands-free system comprising a hands-free unit and a mobile phone, the method comprising the following steps of setting up a connection between the hands-free system and a distant terminal via a mobile telephony network of the mobile phone, transmitting a predetermined test signal from one of the hands-free system and the distant terminal to the other of the hands-free system and the distant terminal, the predetermined test signal being provided in both the hands-free system and the distant terminal as reference test signal, comparing the received test signal to the reference test signal stored in the other of the hands-free system and the distant terminal, and determining the calibration parameters of the hands-free system in accordance with the comparison.

Abstract: A test apparatus tests a device under test. The test apparatus includes a period generator that generates a rate signal determining a test period according to an operating period of the device under test, a phase comparing section that inputs an operational clock signal for the device under test generated from the device under test and detects a phase difference between the operational clock signal and the rate signal using the rate signal as a standard, a test signal generating section that generates a test signal to be supplied to the device under test in synchronization with the rate signal, a delaying section that delays the test signal in accordance with the phase difference to substantially synchronize the delayed signal with the operational clock signal, and a test signal supplying section that supplies the delayed test signal to the device under test.

Abstract: Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.

Abstract: A multi-chip module (MCM) assembly has two modules interconnected by respective interposers and a printed circuit board, and diagnostic logic within the modules uses the principal of signal reflection to located any open fault in the circuit path across the interposers. A first test signal is sent from module to the other and a determination is made as to whether any reflected signal represents an open fault of the circuit path at either of the interposers. If a reflected signal is received during a predetermined time, the diagnostic logic concludes that a single open fault exists only at the far interposer. If no reflected signal is received then the diagnostic logic concludes that there is at least one open fault at the near interposer, and the second module runs a similar test to check to see if both interposers have failures.

Abstract: A simulated battery test device and method that is capable of testing a battery charging circuit and logic circuit to determine proper operation. An operational amplifier is used that can both source and sink current to simulate the operation of the battery. A battery low signal can be generated using the simulated battery test device to test a battery charging circuit and logic circuit in a battery low condition. In addition, a battery open signal can be generated to test the battery charging and logic circuit in a battery open condition. Charging currents are detected to determine if currents fall within an acceptable range.

Abstract: A system on a circuit board includes a plurality of devices designed to access an electronic system on the circuit board, and a programmable logic device (PLD) connected to the plurality of devices. Each of the plurality of devices complies with a test port architecture. The PLD interfaces the plurality of devices with a test port. The PLD is capable of configuring different connectivity among the plurality of devices based on the program implemented and the assertion of input control signals. A method and apparatus configures a plurality of devices on a circuit board into a desired configuration using the PLD. The configuration includes (a) receiving a control signal at the PLD, (b) configuring at least one of the plurality of devices into a chain based on the control signal, and (c) coupling the configured chain to the test port via the PLD.

Abstract: A communications connector tester for quickly and accurately analyzing communications connectors at production to determine whether the connectors are fit for use in certain communications applications is disclosed. Test signals at several discrete frequencies are sequentially inputted into pairs of conductors in the communications connector under test, and output signals are detected for the pairs under test. The output signals are compared to acceptable ranges for certain applications of the communications connector and the connector is passed or failed for certain applications based on the output signal values. Near-end crosstalk, far-end crosstalk, return loss, insertion loss, and other communications connector qualities may be measured using the present invention.

Abstract: A driving chip package, a display device including the same, and a method of testing the driving chip package are disclosed. Any contact failure between the driving chip package and the display substrate can be easily detected, thus reducing the quality management cost and preventing additional failures and increasing the manufacturing yield. The driving chip package includes a base film made of an insulating material, a plurality of interconnection lines formed (e.g., patterned) on the base film (that conduct externally processed driving signals to driving chip and that conduct the driving signals processed in and output by the driving chip), and at least one test interconnection line (e.g., a test signal input interconnection line or a test signal output interconnection line) formed parallel to the interconnection lines on the base film. A test signal input interconnection line and a corresponding test signal output interconnection line are electrically connected through a link on the display substrate.

Abstract: A method for measuring a tangential tightness of a stator coil within an armature slot of a stator assembly in an electric generator. The stator coil is excited to produce a vibratory response therein. The vibratory response of the stator coil is detected and a frequency response function of the vibratory response is determined. A tangential tightness of the stator coil within the armature slot is estimated based on the frequency response function of the vibratory response of the stator coil.

Abstract: There is provided a state detecting method adopted to an insulation resistance detector including the steps of: calculating a difference between the output of the filter when a pulse signal having a first pulse width is applied to the series circuit, and the output of the filter when a pulse signal having a second pulse width shorter than the first pulse width is applied to the series circuit; and detecting the state of the insulation resistance detector based on the calculated difference.

Abstract: A method for verifying the integrity of the electrical connection between at least one signal path of a substrate and at least one respective contact of a component mounted on the substrate is disclosed. The method includes generating a step signal on one of the at least one signal path connected to a respective contact, and capturing a capacitively coupled signal due to the step signal at the contact. The method further includes determining the integrity of the electrical connection from a characteristic of the capacitively coupled signal or a response signal obtained from the capacitively coupled signal. A tester in which the method is implemented is also disclosed.

Abstract: A cable fault detection component (168) receives input data indicative of a fault in an electrical power system. The component (168) analyzes the input data to determine if the fault is indicative of a temporary or self-clearing cable fault and generates corresponding output data (276). In one implementation, the cable fault detection component (168) is implemented as a software module which operates on a computer (105) of a substation intelligence system (104).

Abstract: A device for measuring and isolating noise-creating imbalances in a paired telecommunications line has an internal circuit which comprises a balanced center tapped termination consisting of precisely equal resistor pairs. The circuit includes an adjustable sine wave burst generator which generates a low voltage longitudinal ac signal that is transmitted across the balanced pathways. A differential amplifier in the circuit measures this difference and displays it in units of noise or balance. The output of the differential amplifier is transmitted to an analog-to-digital converter. A microprocessor collects the samples in an array, and filters the results for presentation on a display. Advantageously, the microprocessor provides for adjustable and selectable bandpass filtering.

Abstract: In accordance with the present invention, a first shorting bar drives the data lines of a TFT array having integrated gate driver circuitry. Another set of shorting bars drive the corresponding terminals of the gate driver circuitry. The pixel voltages are measured after all the pixels are charged by the driving signals applied to the shorting bars. Gate voltages are progressively applied to the gate lines by the gate driver integrated circuit (IC) via the set of shorting bars that, in turn, are driven by clock signals received from one or more pattern generators. Voltages are concurrently applied to the data lines which are connected together by the first shorting bar. The application of voltages generates a display pattern that is subsequently compared to an expected display pattern. By comparing the resulting display pattern and the expected display pattern, possible defects are detected.

Abstract: A memory device includes a latch component including a first input configured to receive a functional data bit associated with a functional operation, a second input configured to receive a memory test/repair data bit associated with a memory test operation, and a latch comprising a data input and a data output and select logic configured to selectively connect one of the first input or the second input to the data input of the latch based on a mode of operation of the memory device. A method includes operating a memory device in a first mode associated with a memory test operation and in a second mode associated with a functional operation. The method further includes storing a memory test/repair data bit at a latch component of the memory device in the first mode and storing a functional data bit at the latch component in the second mode.

Abstract: The present disclosure is directed to cable diagnostic test methods, systems and apparatus that advantageously utilize “standing wave”principles to facilitate the identification and location of defect(s) along a power cable. The disclosed methods/systems are effective in measuring dissipation factors and dielectric constants associated with shielded power cable insulation at any number of points or sections along the axial length of the cable. In essence, the disclosed methods/systems perform what may be termed axial tomography, allowing the dielectric loss or dissipation factor and the dielectric constant of the insulation as well as the resistance and inductance of the cable conductor system to be determined at one or more pre-determined points/sections of the cable along its axis.

Abstract: A cable fault detection component (168) receives input data indicative of a fault in an electrical power system. The component (168) analyzes the input data to determine if the fault is indicative of a self-clearing cable fault and generates corresponding output data (276). In one implementation, the cable fault detection component (168) is implemented as a software module which operates on a computer (105) of a substation intelligence system (104).

Abstract: Detecting ingress of a transmitted signal into a cable communication system due to a radio frequency signal transmitted from a moving vehicle and interrogation of transmitter location over a separate wireless link provides monitoring of shielding integrity or flaws there in a cable communication system. The location of a shielding flaw may then be precisely located in a closed loop fashion without risking overload of the cable communication system or interference with upstream signaling therein by detecting ingress signal strength and controlling transmitted signal strength while providing a user-perceptible indication of ingress signal strength which is compensated for the control of transmitted signal strength and thus indicates proximity of a hand-held instrument or transmitter to said shielding flaw.

Abstract: Apparatus includes an arc wave generator for testing an arc fault circuit interrupter (AFCI) for use in a test system for testing whether or not an arc fault circuit interrupter (AFCI) is operating normally, in which a false arc is generated for use in testing the arc fault circuit interrupter (AFCI). The arc wave generator includes a rectifier which receives a commercial power source as an input source and rectifies alternating-current voltage of the commercial power source to generate a rectified signal. A drop resistor drops the voltage of the rectified signal to generate a voltage-dropped signal. A mono-stable multivibrator adjusts a voltage level and a pulse width of the voltage-dropped signal and generates a pulse signal which is used to generate a false arc for testing the arc fault circuit interrupter (AFCI). Thus, a false arc is generated with a simple circuit to accurately test the actions of the arc fault circuit interrupter (AFCI).

Abstract: The integrated circuit (10) has an internal power supply domain with a power supply voltage adaptation circuit (14) to adapt the power supply voltage in the power supply domain. Typically, a plurality of such domains is provided wherein the power supply voltage can be adapted independently. During testing an internal power supply voltage is supplied to a temporally integrating analog to digital conversion circuit (16) in the integrating circuit (10). A temporally integrated value of the power supply voltage is measured during a measurement period. Preferably, integrating measurements of a plurality of internal supply voltages are performed in parallel during the same measurement time interval. Preferably a further test is performed by changing over between mutually different supply voltages during a further measurement period. In this way the measured integrated supply voltage can be used to check the speed of the change over between the different voltages.

Abstract: A method and device for testing an electric circuit, wherein exhaustive electric circuit modulation is not required yet circuit errors can be recognized in a reliable manner is provided. A marking signal is produced, indicating a predefined circuit state that might occur in specific components of an electric circuit, wherein a transformed network list is formed from an original network list describing the circuit, whereby all electric components of at least one predefined component group, with regard to a respective connection pair, are treated as short-circuited, all network nodes connected by one or several components that are to be treated as short-circuited are respectively combined to form an equivalence category, wherein respectively all states of the associated network nodes are assigned to each equivalence category, it is possible to determine whether and in which components the predefined circuit state can occur by taking into account the equivalence categories.