Abstract: A method, an adjusting tool system and an accuracy adjustment system are provided for faster and more reliable adjustment of a HV-divider. A secondary unit includes a plurality of electronic components for adjusting a dividing ratio of the voltage divider. The adjusting tool system is connected to the secondary unit. The adjusting tool system evaluates the accuracy of the voltage divider for a plurality of circuit configurations. A circuit configuration interconnects a subset of the electronic components to generate an electronic circuit that influences the dividing ratio of the voltage divider. A circuit configuration that results in a sufficiently accurate dividing ratio is selected. A connector is programmed by the adjusting tool system in such a way that the secondary unit establishes the selected one of the circuits when the connector is connected to the secondary unit. Preferably, the connector is programmed by burning fuses within the connector.

Abstract: The present invention relates to a magnetic resonance tomography apparatus for generating tomography data of an examination object in a magnetic field by means of an electromagnetic pulse sequence, having a memory for storing reference tomography data of a reference examination object; an acquisition facility for generating tomography data of the reference examination object by means of the pulse sequence; and an adjustment facility for reducing a deviation between the tomography data and the reference tomography data by adjusting a physical parameter in the pulse sequence.

Abstract: A likely value is calculated by a maximum-likelihood method for all coefficients of a relative error correction circuit network model derived by assuming that, for all pairs of two ports selected from among signal line ports related to application or detection of a high frequency signal and non signal line ports other than the signal line ports, there exists a leak signal directly transferred between the ports. A coefficient of a first relative error correction circuit network submodel derived by assuming that, for all pairs of two ports selected only from among signal line ports, there exists a leak signal directly transferred between the ports, and a coefficient for a non signal line port of a second relative error correction circuit network submodel derived by assuming that there exists a signal reflected at a non signal line port are used as initial values.

Abstract: Methods and apparatus to determine a power state of an information presentation device. The method includes measuring power drawn by the information presentation device during a calibration period to generate a log of measurement values, determining, by executing an instruction with a processor, respective counts indicating respective numbers of times respective different ones of the measurement values were detected during the calibration period, and determining, by executing an instruction with the processor, a first threshold based on at least one of the counts. The method also includes determining whether the presentation device is in an ON state based on a comparison of measured power drawn by the information presentation device after the calibration period to the first threshold.

Abstract: An inspection jig for a display device includes a jig body, the jig body includes a limit groove configured to limit the position of the display device to be inspected, and the jig body is provided with a soldering point testing portion, the soldering potin testing portion is provided with a plurality of testing terminal pairs; each of the testing terminal pairs comprises two testing terminals; in every two adjacent testing terminal pairs, one testing terminal of one testing terminal pair and one testing terminal of the other testing terminal pair are serially connected with an indicator lamp therebetween; along a serial connection direction of the testing terminals, a testing terminal located at two ends are electrically connected with a positive pole and a negative pole of a power source.

Abstract: Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit.

Abstract: A measuring system for performing measurements on a device under test is provided. The measuring system comprises a measuring device, a probe connected to the measuring device, a power sensor and a positioning unit. The positioning unit is adapted to connect the probe to the power sensor in a first configuration and to the device under test in a second configuration. The measuring device is adapted to generate a first signal. The probe is adapted to supply the first signal to the power sensor and the first configuration and to supply the first signal to the device under test and the second configuration. The power sensor is adapted to determine the power of the first signal and the first configuration. The measuring device is adapted to regulate the power of the first signal in the second configuration based upon the power determined by the power sensor.

Abstract: A first S parameter of a first circuit network including an input port and a connection port is prepared, a second S parameter of a second circuit network is measured, and an overall S parameter of an overall circuit network is calculated. The S parameter of the overall circuit network is calculated as the overall S parameter corresponding to the input port among virtual S parameters of a virtual overall circuit network in which the connection port of the virtual first circuit network is connected with the second circuit network, by using, as an unknown value, a parameter corresponding to the dummy port among virtual T parameters of a virtual first circuit network obtained through conversion of the first circuit network into a symmetric circuit network by adding a dummy port to the input port side of the first circuit network.

Abstract: A current clamp circuit includes a current-source circuit, a current-sense circuit, and a feedback circuit. The current-sense circuit includes a transistor, a resistive network, and a multiplexer. The transistor outputs a sensed current signal having a current that is equal to a current of an output signal provided by the current-source circuit. The feedback circuit limits the current of the sensed current signal and the output signal below a threshold current. The multiplexer modifies a resistance of the resistive network based on a first control signal. The multiplexer circuit and the feedback circuit are programmed using the first control signal and a second control signal when the transistor operates in a linear region and in a saturation region, respectively, to accurately output the sensed current signal.

Abstract: A microcontroller-based system for measuring the impedance of a device under test (DUT) (35) responsive to a square wave stimulus. A clock generator circuit (26) in the microcontroller (20) generates a clock signal at a base clock frequency. A first timer (25) divides down the base clock frequency by a first frequency divisor integer to set the stimulus frequency of a square wave generated by a general purpose input/output (GPIO) function (24), and a second timer (28) divides down the base clock frequency by a second frequency divisor integer to set the sampling frequency of an analog-to-digital converter (ADC) (30). A discrete Fourier transform executed by a processor (22) is used to determine the impedance of the DUT at the stimulus frequency. The first and second integers are selected so that aliased harmonics fall in different DFT bins from the fundamental tone.

Abstract: A touch screen controller is provided. The touch screen controller includes: an offset cancellation circuit configured to cancel offset capacitance of a touch screen panel including a first channel and a second channel crossing the first channel, the offset cancellation circuit connected to the touch screen panel through a sensing node; a charge amplifier configured to generate a sensing voltage from a sensing signal output from the touch screen panel, the charge amplifier including an amplifier having a first input terminal connected to the sensing node and a second input terminal to which an input voltage is applied; and a channel driver configured to provide a driving voltage, which is equal to or greater than the input voltage, to the second channel in a self capacitance sensing mode for the first channel.

Abstract: In a method for making calibration measurements in a magnetic resonance (MR) system, in order to acquire an MR image of an examination subject, wherein the MR unit has a computer for operating the MR scanner, and a system control computer designed to control multiple system components of the MR scanner, a preparation step is executed by the computer to prepare a first calibration step, in which a first parameter of a system component is matched to the examination subject via the system control computer, and to prepare a second calibration step, in which a second parameter of a system component is matched to the examination subject via the system control computer. The first calibration step is executed by the system control computer as is the second calibration step. The preparation step is executed by the computer to prepare one of the first or second calibration steps before one of the calibration steps is initiated by the system control computer.

Abstract: A tester including a source and measuring device and a TX port connected to the source and measuring device is provided. The tester is configured to determine a source reflection coefficient using an extension circuit. The extension circuit includes a TX port connectable to the source and measuring device, a termination switch and a calibration device providing one or more terminations, wherein each of the terminations is individually connectable to the TX port by the termination switch, wherein one of the terminations is a power sensor. The source and measuring device is configured to measure one or more reflection coefficients at the TX port for the one or more terminations provided by the calibration device including the reflection coefficient for the power sensor. The tester is configured to determine the source reflection coefficient based on the one or more measured reflection coefficients including the measured reflection coefficient for the power sensor.

Abstract: Technologies for determining the parameters of a transmission line such as a printed circuit board trace and a cable are disclosed. By measuring a reflection coefficient and a transmission coefficient of two different electrical structures with the same type of fixture on each end and transmission lines of different lengths, the attenuation coefficient of the transmission lines can be determined. The attenuation coefficient can indicate whether or not the performance of the transmission line is acceptable or may be used to calibrate a measuring device for subsequent measurements.

Abstract: A tester including a source and measuring device and a TX port connected to the source and measuring device is configured to determine a source reflection coefficient using an extension circuit. The extension circuit includes a calibration device having a power sensor. The calibration device is configured to provide a plurality of different terminations at the TX port. The tester is configured to calibrate a source power of the source and measuring device using the determined source reflection coefficient and the power sensor.

Abstract: A method for detecting water level in a water tank that includes a probe voltage value acquiring step comprising periodically acquiring a voltage value of a water level probe as a probe voltage value; a voltage value comparing step that compares the probe voltage value with a stored voltage threshold value, if the probe voltage value is lower than the voltage threshold value, the method determines that the water tank level is higher than the water level probe and updates the water data to be the probe voltage value, and if the probe voltage value is higher than the voltage threshold value, the method determines that the water tank level is lower than the water level probe and updates the waterless data to be the probe voltage value; and a threshold value updating step that updates the voltage threshold value in response to the water data and the waterless data.

Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor, a register storing timing information, and an arbiter circuit configured to determine whether the resistor is available based, at least in part, on the timing information stored in the register. The timing information stored in the register of each respective chip of the plurality of chips is unique to the respective chip among the plurality of chips.

Abstract: A digital-to-analog converter (DAC) includes a DAC circuit, a switch circuit and a control circuit. The DAC circuit includes most significant bit digital-to-analog converter (MDAC) circuits and calibration digital-to-analog converter (CDAC) circuits. The switch circuit includes a current source circuit and a detection circuit. The MDAC, CDAC circuits and the current source circuit are coupled to a first output terminal and a second output terminal of the DAC circuit. In a calibration mode, the current source circuit generates current deviation of the first output terminal and the second output terminal. The detection circuit detects the current differences to generate detection signals. The control circuit outputs control signals to the CDAC circuits to adjust output currents of the CDACs at the first output terminal and the second output terminal. In a regular mode, the current source circuit is configured to function as a dual DC current source.

Abstract: An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, and a charge overflow circuit. The charge storage region may be used to operate the image sensor array in global shutter mode. During high light level illumination, the charge overflow circuit may divert charge away from the photodiode such that only a predetermined portion of the accumulated charge remains in the photodiode. During low light level illumination all of the accumulated charge may be stored in the pixel photodiode. The charge overflow circuit may include a transistor and a resistor or capacitor. By implementing a charge overflow circuit, the size of the charge storage region may be reduced while still preserving the high dynamic range and low noise of the image sensor during all light illumination conditions.

Abstract: An output buffer circuit may include a pulse generator, a transmitter, and an emphasis controller. The pulse generator generates a pulse signal for determining an emphasis execution period. The transmitter may receive an input data and to have a first output resistance value, which is determined by the input data and a resistance calibration code, and to have a second output resistance value different from the first output resistance value, which is determined by the input data and an emphasis code different from the resistance calibration code for executing an emphasis operation during the emphasis execution period, based on the pulse signal. The emphasis controller provides the resistance calibration code or the emphasis code to the transmitter based on the pulse signal. The emphasis code may include a first code determined by the input data regardless of the resistance calibration code.

Abstract: There is provided a test module for testing a fingerprint sensing device comprising: an electrically conductive bottom element comprising an exterior surface portion configured to contact a sensing surface of the fingerprint sensing device; an electrically conductive intermediate element, connected to the bottom element on a side opposing the exterior surface, the intermediate element comprising a flexible material enabling the bottom element to change alignment in response to an applied force occurring when the exterior surface is pressed against a surface being tilted with respect to the exterior surface of the bottom element; and a top element configured connect the test module to a test fixture. There is also provided a method for testing a fingerprint sensing device using the described test module.

Abstract: An integrated circuit and an operation method of a SERDES PHY layer circuit thereof are provided. When the SERDES PHY layer circuit is in a calibration preparation state and a signal of a first calibration input pin is an enable state, or when the SERDES PHY layer circuit is in the calibration preparation state, and signals of first and second calibration input pins are in the enable state, the SERDES PHY layer circuit enters a calibration state (using a reference resistor for current calibration). After the current calibration is completed, the SERDES PHY layer circuit enters a calibration completion state (without using the reference resistor and connecting the first calibration input pin to the first calibration output pin). The SERDES PHY layer circuit sets the signal of the first calibration output pin to a disable state when the SERDES PHY layer circuit is not in the calibration completion state.

Abstract: A quadrature demodulator includes a quadrature demodulating circuit configured to generate an analog in-phase signal and an analog quadrature signal based on an output signal of a low noise amplifier, and a controller configured to cause a thermal noise, instead of the output signal of the low noise amplifier, to be input to the quadrature demodulating circuit, when a correction parameter to correct a mismatch between the in-phase and quadrature signals is being calibrated.

Abstract: The present invention relates to a novel means and a novel method for detecting a capacitance connected to AC power, which detect a sensor capacitance on the basis of a charge sharing phenomenon occurring due to a difference between voltages applied to a sensor capacitor and an auxiliary capacitor connected to a detection system when an AC voltage applied to the detection system alternates. According to the present invention, since the sensitivity of a signal detected by a detection system is improved, a magnitude and a change amount of a sensor capacitance are stably acquired.

Abstract: Embodiments of the present invention provide enhanced methods of calibrating arbitrary waveform generators using s-parameters, and arbitrary waveform generators calibrated according to those methods. Methods are provided for calibrating a single, non-interleaved channel of an arbitrary waveform generator, calibrating multiple interleaved channels, and calibrating pairs of channels, both interleaved and non-interleaved, to generate differential signals.

Abstract: The present disclosure relates to wireline communication systems, and in particular to aspects of a method and a line estimation device for estimating a characteristic impedance of a section of a transmission medium. The method comprises determining, by a test equipment having a test port with known impedance Zref, an S11 scattering parameter vector S11ref[f] of the transmission medium, indexed by frequency f. The method also comprises generating, based on Zref and S11ref[f], a model of reflection in the transmission medium corresponding to an observation of the transmission medium via a test port having a test impedance ZT, and also estimating the characteristic impedance of the section as a value of ZT which minimizes a difference between a reflection value of the model of reflection and a respective target reflection value of the section.

Abstract: A method for calibrating a test apparatus, having a first and a second directional coupler, for gauging a two-port test object that has a first port and a second port in a calibration plane, wherein for the purpose of calibrating the test apparatus a vectorial network analyzer having a 1st-6th test port is connected to the first and second ports in the calibration plane such that the first and second test ports are connected to respective port in the calibration plane, the third and fourth test ports are connected to the first directional coupler and the fifth and sixth test ports are connected to the second directional coupler via a respective waveguide for electromagnetic waves. For different calibration standards, scatter parameters are determined for each desired frequency point. For the different calibration standards, corrections to the scatter matrix are made in order to obtain a corrected scatter matrix.

Abstract: A calibration module for a tester, for testing a device under test, includes a pair of RF-channel terminals, a calibration device, a pair of measurement terminals and a mode selector. The pair of RF-channels terminals is configured to send or receive measurement signals to or from an RF-channel of the tester. The calibration device is configured to perform a calibration of the RF-channel based on the measurement signals sent to, or received from, the RF-channel. The pair of measurement terminals is configured to send or receive measurement signals to or from the device under test. The mode selector is configured to connect, in a calibration phase, the pair or RF-channel terminals to the calibration device for calibrating the RF-channel and to connect, in a measurement phase, the pair of RF-channel terminals to the pair of measurement terminals for routing measurement signals from the RF-channel to the device under test or vice versa.

Abstract: The present invention relates to a calibration method and a calibration arrangement for a RF test apparatus for testing a RF device under test. Instead, a calibration board is provided and connected to each of the cables of the RF test apparatus. A calibration board is configured to provide a plurality of connection loops by connecting the input/output channel terminals of the test apparatus one after the other with each other. This results to a bunch of different connection loops. Then a physical parameter, such as the attenuation over frequency, is measured for each of these connection loops. Since each physical parameter can be described by a single equation, this results to an amount of different equations which form an equation system. The idea underlying the present invention is that the amount of equations of this equation system, which amount corresponds to the different connection loops, is at least equal or higher than the amount of unknown parameters of the equation system.

Abstract: A detection device includes a chamber for vacuum coating, a capacitance measurement device and a baffle mechanism located in the chamber. The baffle mechanism is a closed structure encompassed by a number of baffle walls, wherein at least one baffle wall includes a fixed baffle plate and a moveable baffle plate. The moveable baffle plate is pivotable about the fixed baffle plate. The moveable baffle plate, after pivoting, may get parallel with an adjacent baffle wall. The adjacent baffle wall and the moveable baffle plate are respectively connected to the capacitance measurement device, and the capacitance measurement device is used to measure the capacitance between the adjacent baffle wall and the moveable baffle plate. The detection device may accurately detect the service life of the baffle mechanism and achieve precise management of the apparatus.

Abstract: The present disclosure relates to an innovative method of assigning signals to general-purpose input/output pads of an integrated circuit chip. An inductance matrix for the input/output pads is obtained. A candidate assignment is made of a differential signal to a pair of the input/output pads, and a differential mutual inductance is determined for each open pad location in relation to the pair of input/output pads. Single-ended signals are assigned to open pad locations having the lowest differential mutual inductances. The jitter contribution due to each assigned single-ended signal is computed, and a total jitter is updated. In a first embodiment, said assigning, computing and updating steps are repeated until the total jitter exceeds a total jitter budget. In a second embodiment, said assigning, computing and updating steps are repeated until a number of assigned single-ended signals is equal to a target number. Other embodiments and features are also disclosed.

Abstract: A system and method corrects the phase of measurement signals obtained from remote heads during testing of a device. A first signal is transmitted along first and second transmission lines to respective remote heads. A shunt switch is connected between a remote end of the first transmission line and a first remote head, and another shunt switch is connected between a remote end of the second transmission line and a second remote head. The shunt switches in a first configuration respectively reflect the first signal back to a phase measurement apparatus as first and second reflected signals. The phase measurement apparatus determines a first reference phase and a second reference phase respectively based on the first and second reflected signals. A compensation unit compensates phase of the measurement signals based on the first and second reference phases.

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.

Abstract: A method for determining electric voltage u(t) and/or electric current i(t) of an RF signal in the time domain in a calibration plane, wherein by at least one directional coupler having two outputs and one signal input a first component of a first RF signal that runs from the signal input in the direction of the calibration plane, and a second component of a second RF signal that runs from the calibration plane in the direction of the signal input is decoupled. For a two-port error of the directional coupler, the error terms e00, e01, e10 and e11, are determined as a function of a frequency f and the signal values v1(t) and v2(t) are transformed into the frequency domain as wave quantities V1(f) and V2(f), and absolute wave quantities a1 and b1 in the frequency domain in the calibration plane are calculated from the wave quantities V1(f) and V2(f) by the error terms e00, e01, e10 and e11.

Abstract: A test system for monitoring the performance of a radio frequency signal generator is introduced. The system operates to predict approaching or imminent failure of the radio frequency generator. The system includes a directional coupler, a first detector, a second detector, and a processor to collect, process, and analyze data from the radio frequency generator under test.

Abstract: The appliance for the switching of radiofrequency signals comprises a first port and a second port connectable along a transmission/receiving line of a radiofrequency communication system, a third port connectable to a monitoring appliance of radiofrequency signals and at least a switching circuit which is able to switch between: a monitoring configuration, wherein the first port and the second port are connected together for the transmission/receiving of signals along the transmission/receiving line and wherein the signals are in part taken and sent to the third port for the analysis by means of the monitoring appliance; a test configuration, wherein the third port and the second port are connected together for sending at least a predefined test signal from the monitoring appliance to the transmission/receiving line.

Abstract: The present disclosure involves method and apparatus for de-embedding test fixture to extract the electrical behavior of device under test. A calibration board with both “1× open” and “1× short” test structures is fabricated and measured by equipment such as vector network analyzer that produces S parameters. The S parameters of “1× open” and “1× short”, with or without correction factors, are combined to produce the S parameters of equivalent “2× thru” test structure. The S parameters of equivalent “2× thru” are used subsequently to de-embed the test fixture. This present disclosure gives a simpler and more accurate method to create the S parameters of “2× thru” for de-embedding.

Abstract: Methods and devices for determining device usability, e.g., for point of care assay devices. In one embodiment, the invention is to a method of determining device usability in a sensing device, including the steps of: providing a device comprising a first electrical pad; a second electrical pad; and a first polymer layer contacting at least a portion of the first and the second electrical pads and a second polymer layer contacting the first polymer layer and not the first and second electrical pads; applying a potential across the first and the second electrical pads; measuring an electrical property associated with the first and the second polymer layers; and determining whether the measured electrical property associated with the first and the second polymer layers has exceeded a threshold level associated with the device usability.

Abstract: Systems and methods are disclosed for monitoring a voltage received by a data storage device. A connection cable or data storage device may include a power monitoring module monitor the voltage received by the data storage device. The power monitoring module may provide an indication of whether voltage received by the data storage device is within a range of voltages.

Abstract: A system and method for testing a power supply. A power-end of the power supply is received in a power port of a power supply tester. Information about the power supply is received. A load is dynamically configured for the power supply in response to the information. The power supply tester is automatically activated to power the power supply in response to the power supply being received by the power supply tester and the load being configured. Performance characteristic of the power supply are measured. The performance characteristics of the power supply are displayed to the user indicating functionality of the power supply.

Abstract: A method for adjusting a current sensor with a measuring element having a broken rational current-voltage characteristic curve, including:—changing the broken rational profile of the broken rational current-voltage characteristic curve of the measuring element on the basis of at least one predetermined condition.

Abstract: System and method for implementing a Vector Network Power Meter (VNPM) as a new class of electronic test instrument that uses a novel topology based upon a reflectometer to combine the functionality of a Power Meter with that of a Vector Network Analyzer (VNA). The VNPM overcomes application limitations of the two existing classes of test instruments, including parallel and simultaneous measurement capability, in-circuit operation, and improved accuracy and repeatability by eliminating the calibration of interconnecting cabling. Also provided are alternate implementations of a correlator for the reflectometer which reduce the size and complexity of the correlator while extending its frequency range without limit.

Abstract: Systems and methods are provided for a replaceable internal open-short-load (OSL) calibrator and power monitor. A calibration system can include a test port; and a replaceable module including a first lookup table corresponding to an open-short-load (OSL) component and a second lookup table corresponding to a power measuring component.

Abstract: Disclosed are systems and methods for identifying and reporting failures of an analog to digital (A/D) conversion system. An A/D conversion system includes a test signal generator configured to generate a test signal including an identifiable characteristic, an A/D converter configured to convert an analog signal measured at an input of the A/D converter to a digital output, and signal injection circuitry configured to inject at least a portion of the test signal from the test signal generator as an injected signal into the analog signal using trace-to-trace crosstalk. A method includes determining whether the digital output generated by the A/D converter indicates the identifiable characteristic.

Abstract: A computer implemented method of calibrating a device comprising the steps of: deriving an analytic expression for a variable to be optimized of the device in terms of at least one parameter of the device, transforming the analytic expression into polynomial form of the at least one parameter of the device, the polynomial form comprising N coefficients, capturing at least N samples of a value of the variable from the device under calibration, each sample being a result of a different independent pre-determined value of the at least one parameter, applying the captured variable values and the corresponding at least one parameter values to the polynomial form, obtaining optimal values of the at least one parameter from the applying step to calibrate the device.

Abstract: A calibration device for use in a memory system includes a bias circuit providing bias current, and a calibration unit generating a control signal for calibration. The bias circuit includes an internal resistor and measures a second bias current generated by mirroring a first bias current through the internal resistor, and adjusts the second bias current to generate the second bias current in a predetermined range as a third bias current. The calibration unit generates the control signal based on a comparison result between a reference voltage and a voltage generated based on the third bias current through an adjustable resistor.

Abstract: A test switch signal analyzer comprising: an analyzer hub operably couplable to a test switch base that includes test switch conductors; signal probe(s) couplable to the analyzer hub and to the plurality of test switch conductors when the analyzer hub is coupled to the test switch base, a signal processing unit coupled to the analyzer hub; the signal processing unit, the analyzer hub, and at least a portion of the at least one signal probe being positionable within a test switch cover that mates with the test switch base when the signal probe is coupled to the test switch conductor(s) and the test switch cover is secured to the test switch base.

Abstract: System and method for calibrating a step attenuator. N attenuation measurements of a step attenuator may be received, where the step attenuator includes M series-connected attenuation sections. Each attenuation section may be configured to switchably provide a respective level of attenuation, where N is greater than M, and where the step attenuator may be modeled via M+1 coefficients, including a coefficient for a no-attenuation state and respective coefficients for the attenuation sections. Values of the coefficients may be determined via least squares estimation using the N attenuation measurements, thereby calibrating the step attenuator.

Abstract: A method for measuring scattering parameters in a device under test (DUT) using a vector network analyzer (VNA), includes calibrating the VNA to generate corrections for deterministic setup defects and mapping a plurality of error terms based on a plurality of time indices, wherein each time indicia is associated with an error term. A test signal is transmitted to the DUT to obtain a measurement signal from the DUT in response to the test signal. The generated corrections to obtained measurements are time aligned based on the mapped error terms.

Abstract: An electronic device may have control circuitry that uses a reflectometer to measure antenna impedance during operation. The reflectometer may have a directional coupler that is coupled between radio-frequency transceiver circuitry and an antenna. A calibration circuit may be coupled between the directional coupler and the antenna. The calibration circuit may have a first port coupled to the antenna, a second port coupled to the directional coupler, and a third port that is coupled to a calibration resistance. The reflectometer may have terminations of identical impedance that are coupled to ground. Switching circuitry in the reflectometer may be used to route signals from the directional coupler to a feedback receiver for measurement by the control circuitry or to ground through the terminations. Calibrated antenna reflection coefficient measurements may be used in dynamically adjusting the antenna.