Semiconductors For Nonelectrical Property Patents (Class 324/71.5)
  • Patent number: 7170275
    Abstract: Method and system for periodically measuring the junction temperature of a semiconductor device. The junction is excited by at least two sequential predetermined currents of different magnitudes. The voltage response of the junction to the at least two currents is measured and the temperature of the junction is calculated, while substantially canceling ohmic effects, by using the voltage response and a correction factor. Whenever desired, the junction is excited by a set of at least four sequential different currents having known ratios. The voltage response to the set is measured and the correction factor is calculated by using each voltage response to the set.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: January 30, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Ohad Falik
  • Patent number: 7139671
    Abstract: A semiconductor device fabrication method comprises; a first step S1 of fabricating a plurality of semiconductor chips on a plurality of semiconductor wafers, respectively; a second step S4 of making a probe test on the plural semiconductor chips respectively, which are present in a sampling region of one semiconductor wafer of the plural semiconductor wafers; and the third step S5 of computing a yield of the plural semiconductor chips present in the sampling region, when the yields of the plural semiconductor chips computed in the third step are a reference value or above, the probe test is not made on the plural semiconductor chips, which are present outside the sampling region of said one semiconductor wafer and on the rest semiconductor wafers of the plural semiconductor wafers fabricated in the same lot as said one semiconductor wafer.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: November 21, 2006
    Assignee: Fujitsu Limited
    Inventor: Nobuo Satake
  • Patent number: 7084641
    Abstract: A measuring cell for recording an electrical potential of an analyte situated on the measuring cell. The measuring cell has a sensor, a layer arranged above the sensor and electrically insulating the analyte from the sensor, and an amplifier circuit connected to the sensor on a substrate and having an input stage containing a field-effect transistor or a bipolar transistor, the sensor being at least indirectly connected to a control terminal of the field-effect transistor or of the bipolar transistor. An operating point of the amplifier circuit is set by means of a voltage or a current applied at the control terminal of the field-effect transistor or of the bipolar transistor of the input stage of the amplifier circuit.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: August 1, 2006
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Bjorn-Oliver Eversmann, Ivo Koren, Christian Paulus, Roland Thewes
  • Patent number: 7078919
    Abstract: The present invention provides techniques for an in-situ measurement of resistivity profiles and dopant concentration distributions in semiconductor structures, such as shallow junctions. A substrate with a resistor test structure having a conduction circuit may be placed at a measurement station, surface layers may be successively removed from the conduction circuit at the measurement station, a sheet resistance of the conduction circuit may be measured at the measurement station after the removal of each surface layer to generate a plurality of sheet resistance measurements, and the resistivity profile may be calculated from the plurality of sheet resistance measurements.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: July 18, 2006
    Inventor: Simon A. Prussin
  • Patent number: 6963193
    Abstract: An a-C:H ISFET device and manufacturing method thereof. The present invention prepares a-C:H as the detection membrane of an ISFET by plasma enhanced low pressure chemical vapor deposition (PE-LPCVD) to obtain an a-C:H ISFET. The present invention also measures the current-voltage curve for different pH and temperatures by a current measuring system. The temperature parameter of the a-C:H ISFET is calculated according to the relationship between the current-voltage curve and temperature. In addition, the drift rates of the a-C:H ISFET for different pH and hysteresis width of the a-C:H ISFET for different pH loops are calculated by a constant voltage/current circuit and a voltage-time recorder to measure the gate voltage of the a-C:H ISFET.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: November 8, 2005
    Assignee: National Yunlin University of Science and Technology
    Inventors: Jung-Chuan Chou, Hsuan-Ming Tsai
  • Patent number: 6948388
    Abstract: A sensing system includes a ring oscillator that emits electromagnetic radiation at a characteristic frequency. The ring oscillator comprises an odd number plurality of inverters that are electrically connected in series. The sensing system also comprises a temperature stabilized voltage source that is used to supply voltage to the inverters of the ring oscillator. A sensing load for sensing a change in a preselected environmental condition is operably connected to the ring oscillator. When the load senses the preselected environmental condition, the sensing load alters the characteristic frequency of the ring oscillator and hence the electromagnetic radiation as emitted by the ring oscillator. A pick-up antenna receives the electromagnetic radiation as emitted by the ring oscillator and detection electronics, operably coupled to the pick-up antenna, measure the frequency of the electromagnetic radiation as received by the pick-up antenna.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: September 27, 2005
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Stanley R. Clayton, Stephen D. Russell, Mark R. Roser, Richard L. Waters
  • Patent number: 6902942
    Abstract: A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices with vertical transistors. In the test device, an active area is disposed in the scribe line region. An H-type deep trench capacitor is disposed in the active area, and has parallel first and second portions and a third portion. Each of the first and second portions has a center and two ends. The third portion is disposed between the centers of the first and second portions. First to fourth conductive pads are disposed on the two ends of the first and second portions respectively. A bar-type conductive pad is disposed between the first and second portions, having a center aligned with a center of the third portion.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: June 7, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Tie Jiang Wu, Chien-Chang Huang, Bo Ching Jiang, Yu-Wei Ting, Chin-Ling Huang
  • Patent number: 6890772
    Abstract: A method of forming a SIMS monitor device for determining a doping profile of a semiconductor device structure including providing a plurality of regularly repeating semiconductor structures including a doping profile to form a monitor device including at least one layer of the regularly repeating semiconductor structures; planarizing the monitor device through a thickness of the regularly repeating semiconductor structures to reveal a target surface overlying the doping profile to form a monitor pattern; and, sputtering the target surface over a sputtering area including the monitor pattern through a thickness thereof while simultaneously detecting and counting over a time interval at least one type of species ejected from the target surface according to a secondary ion mass spectroscopy procedure (SIMS).
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: May 10, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chin-Kai Liu, Jun-Yean Chiou, Pei-Fen Chou, Han-Shun Lui
  • Patent number: 6870357
    Abstract: Method and system for periodically measuring the junction temperature of a semiconductor device. The junction exited by at least two sequential predetermined currents of different magnitudes the voltage response of the junction to the at least two currents is measured and the temperature of the junction is calculated, while substantially canceling ohmic effects, by using the voltage response and a correction factor obtained by periodically. Whenever desired, the junction is exited by a set of at least four sequential different currents having known ratios. The voltage response to the set is measured and the correction factor is calculated by using each voltage response to the set.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: March 22, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Ohad Falik
  • Patent number: 6867059
    Abstract: An a-C:H ISFET device and manufacturing method thereof. The present invention prepares a-C:H as the detection membrane of an ISFET by plasma enhanced low pressure chemical vapor deposition (PE-LPCVD) to obtain an a-C:H ISFET. The present invention also measures the current-voltage curve for different pH and temperatures by a current measuring system. The temperature parameter of the a-C:H ISFET is calculated according to the relationship between the current-voltage curve and temperature. In addition, the drift rates of the a-C:H ISFET for different pH and hysteresis width of the a-C:H ISFET for different pH loops are calculated by a constant voltage/current circuit and a voltage-time recorder to measure the gate voltage of the a-C:H ISFET.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: March 15, 2005
    Assignee: National Yunlin University of Science and Technology
    Inventors: Jung-Chuan Chou, Hsuan-Ming Tsai
  • Patent number: 6864107
    Abstract: A system of testing wafer process-splits in a semiconductor wafer is provided. A first test is performed on a semiconductor wafer in a plurality of locations to obtain first data. The first data is clustered into a plurality of bins to obtain process-split locations. Second tests are performed on the semiconductor wafer in the process-split locations to obtain second data. The first data and second data arc correlated to determine process-split data.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: March 8, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeffrey P. Erhardt, Shivananda S. Shetty
  • Patent number: 6847067
    Abstract: An a-C:H ISFET device and manufacturing method thereof. The present invention prepares a-C:H as the detection membrane of an ISFET by plasma enhanced low pressure chemical vapor deposition (PE-LPCVD) to obtain an a-C:H ISFET. The present invention also measures the current-voltage curve for different pH and temperatures by a current measuring system. The temperature parameter of the a-C:H ISFET is calculated according to the relationship between the current-voltage curve and temperature. In addition, the drift rates of the a-C:H ISFET for different pH and hysteresis width of the a-C:H ISFET for different pH loops are calculated by a constant voltage/current circuit and a voltage-time recorder to measure the gate voltage of the a-C:H ISFET.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: January 25, 2005
    Assignee: National Yunlin University of Science and Technology
    Inventors: Jung-Chuan Chou, Hsuan-Ming Tsai
  • Patent number: 6838866
    Abstract: A process for measuring depth of a source and drain of a MOS transistor. The MOS transistor is formed on a semiconductor substrate on which a trench capacitor is formed and a buried strap is formed between the MOS transistor and the trench capacitor. The process includes the following steps. First, resistances of the buried strap at a plurality of different depths are measured. Next, a curve correlating the resistances with the depths is established. Next, slopes of the resistance to the depth for the curve are obtained. Finally, a depth corresponding to a minimum resistance before the slope of the resistance to the depth reaches to zero is obtained.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: January 4, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Tzu-Ching Tsai, Hui Min Mao
  • Patent number: 6831451
    Abstract: According to one exemplary embodiment, a method for determining a Weibull slope at a specified temperature utilizing a test structure comprises a step of performing a number of groups of failure tests on the test structure to determine a number of groups of test data, where each of the groups of failure tests is performed at a respective one of a number of test temperatures, and where each group of failure tests corresponds to a respective group of test data. The method further comprises utilizing the number of groups of test data to determine a scaling line. The method further comprises determining a scaling factor at the specified temperature utilizing the scaling line. The method further comprises utilizing the scaling factor to determine the Weibull slope. The method may further comprise utilizing the Weibull slope to determine a lifetime of the semiconductor die.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: December 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hyeon-Seag Kim, Jongwook Kye
  • Patent number: 6822430
    Abstract: A cost-efficient and reliable method for assessing lateral dopant profiles includes the estimation of a reference profile formed below a gate structure of a transistor device. The overlap capacitance is then determined for at least two different overlaps, created by different spacer widths, and the lateral extension of a dopant profile to be measured, is estimated on the basis of a relationship between overlap capacitance and spacer width for the reference dopant profile.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: November 23, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Feudel, Manfred Horstmann, Rolf Stephan
  • Patent number: 6808590
    Abstract: A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded in the wafer carrier. The sensor is configured to induce an eddy current in the wafer to determine a proximity and a thickness of the wafer. A sensor array external to the CMP tool is included. The sensor array is in communication with the sensor embedded in the wafer carrier and substantially eliminates a distance sensitivity. The sensor array provides an initial thickness of the wafer to allow for a calibration to be performed on the sensor embedded in the wafer carrier. The calibration offsets variables causing inaccuracies in the determination of the thickness of the wafer during CMP operation. A method and an apparatus are also provided.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: October 26, 2004
    Assignee: Lam Research Corporation
    Inventors: Yehiel Gotkis, Rodney Kistler, Aleksander Owczarz, David Hemker, Nicolas J. Bright
  • Publication number: 20040207384
    Abstract: A measuring cell for recording an electrical potential of an analyte situated on the measuring cell. The measuring cell has a sensor, a layer arranged above the sensor and electrically insulating the analyte from the sensor, and an amplifier circuit connected to the sensor on a substrate and having an input stage containing a field-effect transistor or a bipolar transistor, the sensor being at least indirectly connected to a control terminal of the field-effect transistor or of the bipolar transistor. An operating point of the amplifier circuit is set by means of a voltage or a current applied at the control terminal of the field-effect transistor or of the bipolar transistor of the input stage of the amplifier circuit.
    Type: Application
    Filed: January 9, 2004
    Publication date: October 21, 2004
    Applicant: Infineon Technologies AG
    Inventors: Ralf Brederlow, Bjorn-Oliver Eversmann, Ivo Koren, Christian Paulus, Roland Thewes
  • Patent number: 6806696
    Abstract: According to one exemplary embodiment, a method for determining a Weibull slope at a specified bias voltage comprises a step of performing a number of groups of failure tests on a test structure to determine a number of groups of test data, where each of the groups of failure tests is performed at a respective one of a number of test bias voltages, and where each group of failure tests corresponds to a respective group of test data. The test structure may be an array of MOS transistors, for example. The method further comprises utilizing the number of groups of test data to determine a scaling line. According to this exemplary embodiment, the method further comprises utilizing the scaling line to determine the Weibull slope at the specified bias voltage. The method may further comprise utilizing the Weibull slope to determine a lifetime of a semiconductor die.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: October 19, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Hyeon-Seag Kim
  • Patent number: 6798184
    Abstract: An integrated sensor device having a structure suited for mass production despite of a short lifetime and automatically replaceable, and a measuring system realizing a continuous monitoring at a low cost by using the integrated sensor device are disclosed. The integrated sensor device is constructed into a signal integrated circuit device comprising a sensor unit (6) for measuring a change in the quantity or concentration of a substance; a control unit (7) for processing a signal representing the measurement result; and an antenna unit (10) for transmitting the processed signal to the outside and for receiving an energy necessary for the transmission and the operations of the sensor unit (6) and the control unit (7).
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: September 28, 2004
    Assignee: Yamatake Corporation
    Inventor: Nobuaki Honda
  • Patent number: 6797927
    Abstract: The present invention relates to a measuring system adapted for providing a measurement of an optical parameter of an optical device under test —DUT—, comprising a measuring instrument adapted to perform the measurement and to provide a measurement signal comprising a plurality of values of the measured optical parameter of the DUT over the time. To improve the measurement the measuring system is adapted to receive a temperature signal comprising a plurality of values of the measured temperature of the DUT over the time, and to provide an output signal wherein values of the measured temperature are associated to such values of the measured optical parameter of the DUT that correspond in time.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: September 28, 2004
    Assignee: Agilent Technologies, Inc.
    Inventor: Patrick Ziegler
  • Patent number: 6788050
    Abstract: A system and method for determining a component of an eddy current sensor (ECS) signal attributable to a substrate includes placing a substrate in a first position relative to an ECS at a first distance from the ECS. A first surface of the substrate can include a conductive film. A first ECS signal can be detected with the substrate in the first position. The substrate can then be inverted relative to the ECS. A second ECS signal is detected with the substrate in the second position. A difference signal is determined. The difference signal is equal to a difference between a first signal level on a calibration graph for the ECS and the second signal level.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: September 7, 2004
    Assignee: Lam Research Corp.
    Inventor: Yehiel Gotkis
  • Patent number: 6774613
    Abstract: A semiconducting gas sensor includes a gas-sensitive layer, a heater for heating the layer to a defined measuring temperature, and contact electrodes for measuring the electrical resistance of the gas-sensitive layer enclosed within a microchamber, in which the gas-sensitive layer is arranged. The chamber can be sealed from the outside, and is constructed so that the chamber volume is small enough to allow at least one component of the gas or gas mixture that is to be analyzed to be at least largely exhausted via conversion on the gas-sensitive layer, within a predetermined measuring interval. With the limited gas store and the conversion of a component of the gas during the measurement process, gases or gas mixtures comprising several components can be analyzed. In this, the measuring signal is reexamined following the conversion of at least one component. Within the chamber, several sensor elements may be arranged with gas-sensitive layers, and may be operated at different temperatures.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: August 10, 2004
    Assignee: EADS Deutschland GmbH
    Inventors: Thomas Becker, Stephan Muehlberger, Gerhard Mueller
  • Publication number: 20040119469
    Abstract: A system and method for determining a component of an eddy current sensor (ECS) signal attributable to a substrate includes placing a substrate in a first position relative to an ECS at a first distance from the ECS. The substrate can include a conductive film on a first surface of the substrate. A first ECS signal can be detected with the substrate in the first position. The substrate can then be inverted relative to the ECS such that the substrate is in a second position relative to the ECS at a second distance from the ECS. The second distance is equal to the first distance less about a thickness of the substrate. A second ECS signal is detected with the substrate in the second position. A difference signal is determined. The difference signal is equal to a difference between a first signal level on a calibration graph for the ECS and the second signal level. The second signal level being shifted a distance about equal to the thickness of the substrate.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Applicant: LAM CORPORATION
    Inventor: Yehiel Gotkis
  • Patent number: 6731130
    Abstract: A non-destructive and non-intrusive, user friendly, easy to setup and efficient system and method of determining the gate oxide thickness of an operational MOSFET used in real circuit applications is provided. Additionally, the present invention determines the gate oxide thickness when the operational MOSFET is operating in the inversion mode.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: May 4, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nian Yang, Zhigang Wang, Tien-Chun Yang
  • Publication number: 20040032244
    Abstract: A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 19, 2004
    Inventors: Herbert Palm, Hans Taddiken, Erdmute Wohlrab
  • Patent number: 6677766
    Abstract: A method for measuring the step height of a STI structure is described. The method involves measuring the change in resistance of a polysilicon structure as the step height changes. The resistance of the polysilicon structure is measured by applying a voltage and measuring the resulting current.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: January 13, 2004
  • Patent number: 6661299
    Abstract: Circuits include at least one-odor sensitive organic transistor having a conduction channel whose conductivity changes in response to certain odors. The organic transistors are interconnected to increase their response to selected odor signals. The organic transistors may be interconnected to form a ring oscillator whose frequency of oscillation changes in response to an odor signal and in which the alternating signal applied to the gate electrodes of the organic transistors enhances their recovery and reduces their drift.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: December 9, 2003
    Assignee: Lucent Technologies Inc.
    Inventors: Ananth Dodabalapur, Alan Gelperin, Howard Edan Katz
  • Publication number: 20030210058
    Abstract: A test structure pattern includes a first comb, a second comb, and a serpentine line. The first comb includes a first set of tines of the same orientation. The second comb includes a second set of tines of the same orientation that are interdigitated with the first set of tines. The serpentine line runs between the interdigitated tines of the first metal comb and the second metal comb. The test structure pattern forms a first metal comb, a second metal comb, and a serpentine metal line on a die. Print quality and resolution is tested by checking for electrical continuity in the serpentine metal line and bridging between the serpentine metal line and one of the first metal comb and the second metal comb.
    Type: Application
    Filed: April 23, 2003
    Publication date: November 13, 2003
    Inventors: Robert W. Rumsey, Hiu F. Ip, Arthur Lam
  • Patent number: 6639392
    Abstract: A highly sensitive charged particle measuring device capable of measuring low-level alpha rays comprises in a measurement chamber 7 provided with a sealable door 15, a test sample 2 and a semiconductor detector 1, a radiation measuring circuit 30 including a preamplifier 30c connected to the semiconductor detector 1, a linear amplifier 30d, and a pulse height analyzer 30e, a charged particle emission amount arithmetic unit 40 for performing the quantitative analysis of charged particles from its measurement, a display unit for displaying its analysis result, and further has an evacuation pipe line and a pure gas supply pipe line for performing supply and replacement of the pure gas in the measuring chamber 7.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: October 28, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyoshi Kogawa, Hiroshi Kitaguchi, Tetsuya Matsui, Akihisa Kaihara, Junichi Arita
  • Patent number: 6580280
    Abstract: An exhaust gas side electrode is provided on one surface of a solid electrolytic substrate. A reference gas side electrode is provided on an opposite surface of the solid electrolytic substrate so as to be exposed to a reference gas stored in a reference gas chamber. Each lead of the electrode is connected to a signal output terminal. This sensor satisfies a relationship B/A<0.5, wherein ‘A’ represents an overall resistance value of an electric path including the solid electrolytic substrate, the electrodes, and their leads in a sensor activated condition, while ‘B’ represents a resistance value of the leads at a room temperature. Some embodiments may be arranged such that at least one of the leads has a low resistance portion located in the vicinity of the electrodes and a high resistance portion located in the vicinity of signal output terminals.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: June 17, 2003
    Assignee: Denso Corporation
    Inventors: Makato Nakae, Syuichi Nakano, Toshitaka Saito
  • Patent number: 6556025
    Abstract: A method of measuring changes in signal level output of an integrated circuit sensor by providing a direct current (DC) or low frequency (AC) bias to the sensor and placing a floating gate semiconductor device on-chip and coupling the floating gate of the semiconductor device with the sensor. As a result, changes in signal level output of the sensor modulate charge at the gate. The semiconductor device in turn converts the modulated charge at the gate into output signals proportional to the changes in the signal level output. The measurement method provides a resolution in the sub-atto range.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: April 29, 2003
    Assignee: University of Waterloo
    Inventors: Arokia Nathan, Yong Lu, Tajinder Manku
  • Patent number: 6531859
    Abstract: The invention relates to an electrode arrangement for an electronic component, also acting as a support for sensors. Said electrode arrangement is mounted on a substrate (1) as a suitably dimensioned surface-structure of two electro-conductive electrodes which are not electrically connected to one another. The electrode arrangement reproduces the conductivities and/or the substance of a sensor-active layer on the conductance of a measuring head or a functional element when said conductivities of the electrode arrangement and/or substance of a sensor-active layer are reproduced in a highly flexible manner. Said electrode arrangement can be produced in a simple and cost-effective manner. The invention provides for a plurality of conductive islands (3) which are not linked or not essentially linked to one another and which are mounted on a dielectric substrate (1) between two electrodes (2) in the form of a planar two-dimensional arrangement.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: March 11, 2003
    Inventor: Robert Bischoff
  • Patent number: 6525554
    Abstract: A method and an apparatus for measuring the temperature parameters of an ISFET that uses hydrogenated amorphous silicon as a sensing film, which uses the measurements of the temperature parameters and the source/drain current and gate voltage in an unknown solution to sense the ion concentration and the pH value of the unknown solution.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: February 25, 2003
    Assignee: National Yunlin University of Science and Technology
    Inventors: Jung Chuan Chou, Yii Fang Wang
  • Patent number: 6498470
    Abstract: A system for detecting imminent failure of rotatable equipment that has lost centerline control and is near catastrophic failure is housed in a linear tubular element within which is permanently potted a thin gage insulated wire protected by an optional fuse. The contact end of the wire is located immediately adjacent to a semiconductor disk and an optional abradable disk placed at close proximity to the rotatable equipment being monitored. The thin gage insulated wire return is connected between the fuse and the semiconductor disk providing an electrical return path for detection of a change in electrical continuity. The semiconductor and abradable disks between the contact wire and the rotatable equipment act as insulators from errant grounding. Loss of rotatable equipment centerline control will cause physical contact between the contact wire and rotatable equipment, breaking electrical continuity, the resulting ground path being instantly detected through the internally potted fuse.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: December 24, 2002
    Assignee: Honeywell International, Inc.
    Inventors: Jeff M. Kelly, Benton C. Lewis
  • Patent number: 6484559
    Abstract: A circuit includes at least one odor-sensitive organic field effect transistor (OFET) having a conduction channel whose conductivity changes in response to certain ambient odors and a feedback loop coupled between an output and an input of the circuit. The feedback loop generates a feedback signal which stabilizes the output signal of the circuit for time drift of the odor-sensitive organic transistor. In one embodiment, the OFET is an integral part of an amplifier and generates input signals to the amplifier in response to certain odors. A selectively enabled switch may be coupled between the output and the input of the amplifier circuit to provide negative feedback that tends to cancel the effect on the amplifier of time drift due to the OFET.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: November 26, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: Ananth Dodabalapur, Rahul Sarpeshkar
  • Patent number: 6484563
    Abstract: The present invention relates to a method at detection of presence of hydrogen gas and measurement of content of hydrogen gas. The detection is performed by means of a hydrogen gas sensitive semiconductor sensor, whose output signal is used for determination of the content of hydrogen gas in the gas sample. The semiconductor sensor is exposed to the gas sample during a detection interval, which is preceded by a time-interval of preconditioning treatment during which the semiconductor sensor is exposed to a surrounding gas atmosphere. The invention is characterized in that the gas atmosphere contains a negligible amount of oxygen, hydrogen and carbon monoxide compared to the gas sample and that the time interval is many times longer than the detection interval.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: November 26, 2002
    Assignee: Sensistor Technologies AB
    Inventors: Fredrik Enquist, Peter Hebo
  • Patent number: 6483283
    Abstract: A method and apparatus for manufacturing a semiconductor physical quantity sensor according to the present invention achieves the high sensing accuracy and reliability and prevents a sticking phenomenon. Specifically, a semiconductor physical quantity sensor is cleaned by a displacement liquid and is dried while a SOI substrate is revolving. The number of revolutions is determined so that a suction force (FS), which acts on a silicon substrate by a surface tension of the displacement liquid, a sensor spring force FK and a centrifugal force (Fr) generated by the acceleration in the revolution can satisfy the following condition: (FK+Fr)>FS. In order to prevent the sticking phenomenon after the stop of the spray, the semiconductor physical quantity sensor is dried by spraying an inert gas such as nitrogen including minus ions so that the revolving SOI substrate can eliminate static electricity generated by friction of the air flow.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: November 19, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Katsumichi Uayanagi, Mitsuo Sasaki, Mutsuo Nishikawa, Shiho Katsumi
  • Patent number: 6475728
    Abstract: An apparatus and method for identifying and/or quantifying a charged biological substance in a conductive liquid medium.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: November 5, 2002
    Assignees: Ecole Centrale de Lyon, Centre National de la Recherche Scientifique (C.N.R.S)
    Inventors: Jean-René Martin, Eliane Souteyrand
  • Publication number: 20020125875
    Abstract: A system for detecting imminent failure of rotatable equipment that has lost centerline control and is near catastrophic failure is housed in a linear tubular element within which is permanently potted a thin gage insulated wire protected by an optional fuse. The contact end of the wire is located immediately adjacent to a semiconductor disk and an optional abradable disk placed at close proximity to the rotatable equipment being monitored. The thin gage insulated wire return is connected between the fuse and the semiconductor disk providing an electrical return path for detection of a change in electrical continuity. The semiconductor and abradable disks between the contact wire and the rotatable equipment act as insulators from errant grounding. Loss of rotatable equipment centerline control will cause physical contact between the contact wire and rotatable equipment, breaking electrical continuity, the resulting ground path being instantly detected through the internally potted fuse.
    Type: Application
    Filed: March 2, 2001
    Publication date: September 12, 2002
    Applicant: Honeywell International, Inc.
    Inventors: Jeff M. Kelly, Benton C. Lewis
  • Patent number: 6429675
    Abstract: An integrated circuit device structure having probe pad extensions in electrical communication with the wire bond pads and a method for performing failure analysis thereon. The invention provides an improved probing system for wire bond packages such that neither the wire nor the wire bond from the pads on the chip surface need be removed during testing procedures. Included in the integrated circuit device is a plurality of conductive pads having a first area for receiving a wire bond and a second area for receiving a probe, wherein the second area abuts, and is an electrical communication with the first area.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventor: Paul Davis Bell
  • Patent number: 6418784
    Abstract: A substrate covered with an insulating layer and a catalytic gate electrode 26 disposed on the insulating layer. The catalytic gate electrode 26 has a first end having a first contact pad 30 and a second end having a second contact pad 32. A meander 28 is placed between the first contact and the second contact. A third contact pad 24 is coupled to the underside of the substrate 22. The temperature is measured between the first contact pad 30 and second contact pad 32 while sensor's response to gas concentration is sensed between the gate electrode 26 and the third contact 24.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: July 16, 2002
    Assignee: Ford Global Technologies, Inc.
    Inventors: Amer Mohammad Khaled Samman, Samuel Admassu Gebremariam, Lajos Rimai
  • Patent number: 6369404
    Abstract: An electron device for single spin measurement, comprising: a semiconductor substrate into which at least one donor atom is introduced to produce a donor nuclear spin electron system having large electron wave functions at the nucleus of the donor atom. An insulating layer above the substrate. A first conducting gate on the insulating layer above the donor atom to control the energy of the bound electron state at the donor. A second conducting gate on the insulating layer adjacent the first gate to generate at least one additional electron in the substrate. In use, a single electron is bound to the donor, and the donor atom is weakly coupled to the additional electron(s) in the substrate. The gates are biased so that the additional electron(s) in the substrate will move to the donor, but only if the spins of the electrons and the donor electron or nucleus are in a relationship which permits the movement.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: April 9, 2002
    Assignee: Unisearch Limited
    Inventor: Bruce Kane
  • Publication number: 20020011827
    Abstract: A transient power supply current testing technique which affords a high level of observability is used to prepare a list of detectable faults including a gate delay fault, an open fault and a path delay fault. A test pattern sequence formed by two or more test patterns is obtained (202), a train of transition signal values which occur on various signal lines within the circuit when the pattern sequence is applied to operate IC under test is determined by a transition simulation (203), and the train of transition signal values occurring on various signal lines is used to prepare a fault list which are detectable by the transient power supply current testing when the pattern sequence is used to operate the IC under test (204).
    Type: Application
    Filed: June 13, 2001
    Publication date: January 31, 2002
    Inventors: Masahiro Ishida, Takahiro Yamaguchi
  • Patent number: 6309831
    Abstract: A method of manufacturing items in parallel. Selected samples of items to be manufactured are subjected to additional steps in a manufacturing process. If such sample items meet the requisite quality control standard, remaining items are subjected to further manufacturing steps. If the sample items which have been further processed do not meet the requisite quality control standard, the lot from which the samples do not undergo the additional manufacturing step. Invention provides an improved method of manufacturing in that it prevents unnecessary manufacturing steps.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: October 30, 2001
    Assignee: Affymetrix, Inc.
    Inventors: Martin J. Goldberg, Richard P. Rava
  • Patent number: 6278267
    Abstract: The method obtains a first C-V curve prior to irradiation with light and a second C-V curve after the irradiation with light. The method determines the amount of the intra-film impurity ions in an insulating film in the state prior to the irradiation with light, based on the first and the second C-V curves.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: August 21, 2001
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Hiroshi Okada, Sadao Hirae, Motohiro Kono
  • Patent number: 6222206
    Abstract: A technique is described for determining the performance of substrate-side emitting VCSELs formed on a wafer. The technique involves forming top-emitting VCSELs on the same wafer as bottom-emitting VCSELs and then testing the top-emitting VCSELs and using the results to determine the performance of the bottom-emitting VCSELs of the wafer.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: April 24, 2001
    Assignee: Lucent Technologies INC
    Inventors: Leo Maria Chirovsky, John Edward Cunningham, Keith Wayne Goossen, Sanghee Park Hui, Betty Jyue Tseng