In Or On Support For Device Under Test Patents (Class 324/754.08)
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Patent number: 11940491Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.Type: GrantFiled: April 19, 2023Date of Patent: March 26, 2024Assignee: Apple Inc.Inventors: Fabien S. Faure, Arnaud J. Forestier, Vikram Mehta
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Patent number: 11914287Abstract: A pod for transporting reticles includes an inner cover and an inner base plate. The inner base plate cooperates with the cover to establish a space for mounting a reticle. The inner base plate includes a hole having a perimeter and first and second flanges extending inward from the perimeter. A window assembly is mounted in the hole. The window assembly includes a transparent plate, a seal and a retainer. The seal contacts the outer or side planar surface of the transparent plate and the perimeter of the hole to seal an interface between the window assembly and the hole. The retainer contacts the second flange to retain the seal and transparent plate within the hole.Type: GrantFiled: July 16, 2018Date of Patent: February 27, 2024Assignee: ENTEGRIS, INC.Inventors: Russ V. Raschke, Shawn D. Eggum
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Patent number: 11879912Abstract: A cantilever probe card and a carrier thereof are provided. The carrier includes a seat, a metal sheet, and a plurality of coarse adjustment members. The metal sheet is assembled to the seat and has a carrying surface. The coarse adjustment members are spaced apart from each other and are disposed between the seat and the metal sheet. Each of the coarse adjustment members is configured to be independently operable along a testing direction for changing a distance between the carrying surface and the seat. The carrying surface has a plurality of assembling regions spaced apart from each other, and at least two of the assembling regions have an assembling tolerance therebetween along the testing direction. The metal sheet of the carrier is deformable through at least one of the coarse adjustment members so as to reduce the assembling tolerance along the testing direction.Type: GrantFiled: November 3, 2022Date of Patent: January 23, 2024Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.Inventors: Wei-Jhih Su, Chao-Hui Tseng, Hao-Yen Cheng, Rong-Yang Lai
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Patent number: 11854894Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.Type: GrantFiled: December 4, 2020Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Valluri R. Rao, Patrick Morrow, Rishabh Mehandru, Doug Ingerly, Kimin Jun, Kevin O'Brien, Paul Fischer, Szuya S. Liao, Bruce Block
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Patent number: 11696396Abstract: An electrical contact assembly that uses an elastomer strip for each row of individual contacts. Each contact comprises a rigid bottom pin and a flexible top pin with a pair of arms which extend over and slide along sloped surfaces of the bottom contact. The elastomer strip is located between rows of the bottom and top pins. A bottom socket housing is provided with grooves which receive each elastomer strip. A row of top pins is then placed over each elastomer strip, and through ducts in the bottom socket housing. Bottom pins are then snapped into place in between the pair of arms.Type: GrantFiled: January 26, 2022Date of Patent: July 4, 2023Assignee: JF MICROTECHNOLOGY SDN. BHD.Inventors: Wei Kuong Foong, Kok Sing Goh, Shamal Mundiyath, Eng Kiat Lee, Grace Ann Nee Yee
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Patent number: 11619656Abstract: A probe head includes a middle die, upper and lower die units, at least one of which includes inner and outer dies detachably fastened to the middle die and each other, and a plurality of buckled probes inserted through the upper and lower die units. The inner die has an outer connecting surface connected with an inner surface of the outer die, where an installation recess is provided, an inner connecting surface connected with the middle die, and a probe installation section having a protruding portion protruding from the outer connecting surface and located in the installation recess, and a recessed portion recessed from the inner connecting surface and located correspondingly to the protruding portion. The protruding portion and the installation recess have a horizontal distance therebetween. Therefore, the outer die is horizontally fine adjustable to make the positions of the probes meet the requirement.Type: GrantFiled: December 29, 2021Date of Patent: April 4, 2023Assignee: MPI CORPORATIONInventors: Chin-Yi Lin, Keng-Min Su, Che-Wei Lin, Hsin-Cheng Hung
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Patent number: 11275106Abstract: A test assembly for testing a device under test includes a probe card assembly and a cap secured to the probe card assembly. The probe card assembly includes a probe tile having a plurality of openings. The probe tile includes a plurality of probe wires including a probe needle portion and a probe tip portion. A seal is disposed on a surface of the probe tile and forms an outer perimeter of a pressurized area. The probe tile includes an insulation layer formed within the pressurized area that is configured to separate the probe needle portion from the device under test. The insulation layer includes an aperture through which the probe tip portion extends to contact the device under test. The cap includes a fluid inlet and a fluid return outlet that are in fluid communication with the plurality of openings of the probe tile.Type: GrantFiled: October 7, 2019Date of Patent: March 15, 2022Assignee: CELADON SYSTEMS, INC.Inventors: Adam J. Schultz, William A. Funk, Bryan J. Root
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Patent number: 11262398Abstract: The present disclosure provides a testing fixture. The testing fixture includes a carrier, a plurality of sets of electrical lines and a plurality of electrical lines. The carrier includes a base and a frame extending along an upper surface of the base. The base and the frame define a first recess, a second recess extending longitudinally from the first recess, and a third recess extending transversely from the first recess. The plurality of sets of electrical contacts are disposed on the base and arranged in a rotationally symmetrical manner, and the electrical lines are electrically connected to the plurality of sets of electrical contacts.Type: GrantFiled: October 31, 2019Date of Patent: March 1, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Ching-Chung Wang, Jui-Hsiu Jao
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Patent number: 11226658Abstract: Apparatus and methods may be provided that may include a single bracket (e.g., a single universal support or anchor bracket) capable of operably mounting or supporting multiple diverse configurations of system hardware components (e.g., such as solid state drive (SSD) cards) to an existing motherboard or other system support component/surface on or within the same system chassis of an information handling system.Type: GrantFiled: June 25, 2018Date of Patent: January 18, 2022Assignee: Dell Products L.P.Inventors: Yi-Ning Shen, Mei-Chih Wu, Chih-Wei Chang, Yen-Kai Chiu, Chin-Chung Wu
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Patent number: 11193955Abstract: The present invention provides a guide plate for a probe card. The guide plate for the probe card according to the present invention includes: a first guide plate including a plurality of first pin insertion holes formed therein, and made of an anodic oxide film; and a second guide plate disposed to be spaced apart from the first guide plate by a predetermined distance, and including a plurality of second pin insertion holes through which probe pins passing through the first pin insertion holes pass, wherein a buffer part is provided at least partially on each of an upper portion and a lower portion of the first guide plate.Type: GrantFiled: February 18, 2020Date of Patent: December 7, 2021Assignee: POINT ENGINEERING CO., LTD.Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun
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Patent number: 11139217Abstract: A method for modifying a portion of a substrate after production is described herein. The method can include diagnosing a circuit operation error causing a malfunction, identifying a first contact on the substrate, and connecting, electrically, the first contact to a second contact with at least one trace. The trace is done with a focused ion beam. The method can include diagnosing an error on an operative area of a post-manufacture circuit board causing a malfunction; introducing a metal precursor into a focused ion beam chamber; ionizing the metal precursor by contacting it with a gallium ion beam into a conductive metal and a further ion; depositing a first portion of a conductive metal onto a substrate to form a first trace; and forming the first trace between the operative area and a non-operative area thereby connecting the operative area and the non-operative area.Type: GrantFiled: September 9, 2019Date of Patent: October 5, 2021Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Jeffrey A. Zimmerman, Landon J. Caley, Richard J. Ferguson
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Patent number: 10976348Abstract: A test socket assembly for electrically connecting a contact point to be tested in a test object and a contact point for testing in a testing circuit. The test socket assembly includes: a plurality of signal probes; a socket block including a bottom surface facing toward the testing circuit, a top surface facing toward the test object, a plurality of probe holes for accommodating the plurality of signal probes to be parallel with one another while opposite ends of the signal probes are exposed from the top surface and the bottom surface, and a recessed portion recessed from at least partial area of the top surface and the bottom surface excluding a circumferential area of the probe holes; and an elastic grounding member accommodated in the recessed portion and made of a conductive elastic material to come into contact with at least one of the test object and the testing circuit.Type: GrantFiled: September 19, 2018Date of Patent: April 13, 2021Inventor: Jae-hwan Jeong
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Patent number: 10884025Abstract: A testing device with enhanced accessibility for repair and replacement purposes includes a base, an upper seat, a test board and a needle seat. The upper seat is mounted on the base. The test board is sandwiched between the base and the upper seat. A receiving groove is defined on the upper seat. The receiving groove extends through the upper seat to partially expose the test board. The needle seat is detachably fixed to the upper seat. A lower part of the needle seat is received in the receiving groove and abuts against the test board. An upper portion of the needle seat protrudes from the upper seat and is configure for connecting connection terminals of a product to be tested.Type: GrantFiled: December 28, 2018Date of Patent: January 5, 2021Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO. LTD.Inventors: Chun-Yao Huang, Cheng-An Lin
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Patent number: 10818583Abstract: Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.Type: GrantFiled: September 25, 2017Date of Patent: October 27, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: I-Ting Chen, Ying-Ching Shih, Po-Hao Tsai, Szu-Wei Lu, Jing-Cheng Lin
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Patent number: 10721088Abstract: One embodiment can provide a home-automation system. The home-automation device can include a mechanical supporting structure and a plurality of components mechanically coupled to the mechanical supporting structure. The plurality of components can include a central controller, one or more printed circuit boards (PCBs), and a plurality of sensors mounted on the one or more PCBs. The central controller can be configured to detect a user event based on output from multiple sensors, with each sensor being configured to sense parameters in a different physical domain.Type: GrantFiled: May 21, 2018Date of Patent: July 21, 2020Assignee: BrainofT Inc.Inventors: Ashutosh Saxena, Lukas Kroc, Yu Zhou, Deng Deng
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Patent number: 10663382Abstract: A testing apparatus for applying a test load to a specimen, comprises a cradle and a test bed supported on the cradle. The test bed has a chamber which receives a specimen and is hermetically sealed with the specimen received inside. There is a vacuum source in communication with the chamber. The vacuum source provides vacuum pressure to the chamber, thereby applying a uniform load to the specimen.Type: GrantFiled: August 30, 2018Date of Patent: May 26, 2020Assignee: Canada Scaffold Supply Co. Ltd.Inventors: Keith Iwasaki, Chris Musil
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Patent number: 10663484Abstract: Device and system for characterizing samples using multiple integrated tips scanning probe microscopy. Multiple Integrated Tips (MiT) probes are comprised of two or more monolithically integrated and movable AFM tips positioned to within nanometer of each other, enabling unprecedented micro to nanoscale probing functionality in vacuum or ambient conditions. The tip structure is combined with capacitive comb structures offering laserless high-resolution electric-in electric-out actuation and sensing capability. This “platform-on-a-chip” approach is a paradigm shift relative to current technology based on single tips functionalized using stacks of supporting gear: lasers, nano-positioners and electronics.Type: GrantFiled: February 14, 2018Date of Patent: May 26, 2020Assignee: Xallent, LLCInventor: Kwame Amponsah
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Patent number: 10571487Abstract: Contact engines, probe head assemblies, probe systems, and associated methods for on-wafer testing of the wireless operation of a device under test (DUT). A contact engine includes a flexible dielectric membrane having a first surface and a second surface and a plurality of probes supported by the flexible dielectric membrane. The plurality of probes are oriented to contact a plurality of contact locations on the DUT. Each probe in the plurality of probes includes a corresponding probe tip that projects from the second surface of the flexible dielectric membrane and is configured to electrically and physically contact a corresponding contact location of the plurality of contact locations. The contact engine further includes at least one membrane antenna supported by the flexible dielectric membrane. A probe head assembly includes the contact engine. A probe system includes the probe head assembly. Associated methods include methods of utilizing the contact engine.Type: GrantFiled: November 22, 2017Date of Patent: February 25, 2020Assignee: FormFactor Beaverton, Inc.Inventors: Daniel Mark Bock, Tim Cleary
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Patent number: 10564202Abstract: A test set-up for testing a system-in package with an integrated antenna is described herein. According to one exemplary embodiment, the test set-up includes a carrier with an RF probe arranged thereon and a test socket with resilient electric contacts. The test socket is mounted on the carrier and provides an electric contact to interconnects of the package when it is placed on the test socket. The test socket has an opening which is arranged superjacent to the RF probe.Type: GrantFiled: June 27, 2017Date of Patent: February 18, 2020Assignee: Infineon Technologies AGInventors: Jochen O. Schrattenecker, Oliver Frank, Alexander Kaineder
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Patent number: 10184978Abstract: A probe card for a wafer tester includes a mother card having a reinforcing element and at least one daughter card which is rigidly connected to the reinforcing element detachably. The mother card includes electrical contacts for producing an electrical connection with the wafer tester. The at least one daughter card includes electrical contact elements for making contact with an electrical circuit on a wafer. In addition, the mother card and the at least one daughter card are electrically detachably connected to one another via an electrical interface.Type: GrantFiled: December 16, 2014Date of Patent: January 22, 2019Assignee: Infineon Technologies AGInventors: Karl Dominizi, Oliver Frank, Klaus Standner, Stefan Zielke
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Patent number: 10161964Abstract: An inspection unit includes: a metal block having at least a through hole; a ground bush disposed in the through hole, and being an electrically conductive body including: a cylindrical body part; and a projected part which is projected sideward from an outer face of the body part, and which is in contact with an area around an opening of the through hole in the metal block; and a contact probe for ground passing through an interior of the ground bush.Type: GrantFiled: November 25, 2015Date of Patent: December 25, 2018Assignee: Yokowo Co., Ltd.Inventor: Masataka Miyagawa
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Patent number: 10114055Abstract: Apparatus for testing a device by delivering an electrostatic discharge signal to one or more device terminals, comprising a first part configured for mechanically mounting the device and comprising one or more first part connectors for electrically coupling to the one or more device terminals and thus providing electrical access to the one or more device terminals, a second part comprising one or more second part connectors configured for electrically coupling the one or more first part connectors to the one or more second part connectors for testing the device via the second part connectors, and a guide arranged for mechanically moving the first part relative to the second part. The guide is configured to physically disconnect the one or more first part connectors from the one or more second part connectors while the electrostatic discharge signal is delivered to the one or more device terminals.Type: GrantFiled: November 30, 2016Date of Patent: October 30, 2018Assignee: NXP USA, Inc.Inventors: Alain Salles, Jean Dalmon, Roger Stivanin
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Patent number: 9952122Abstract: An electronic test plate includes a test plate comprising plurality of wells, each well configured to contain a substance to be analyzed. Sensors are arranged to sense characteristics of the substance and to generate sensor signals based on the sensed characteristics over time. The sensors are arranged so that multiple sensors are associated with each well. At least one sensor of the multiple sensors senses a characteristic of the substance that is different from a characteristic sensed by another sensor of the multiple sensors. Sensor select circuitry is arranged on a backplane disposed along the test plate. The sensor select circuitry is coupled to the sensors and enable the sensor signals of selected sensors to be accessed at a data output of the backplane.Type: GrantFiled: August 3, 2015Date of Patent: April 24, 2018Assignee: Palo Alto Research Center IncorporatedInventors: Mandana Veiseh, JengPing Lu, Eugene M. Chow, David K. Biegelsen, Ramkumar Abhishek, Felicia Linn
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Patent number: 9905954Abstract: A power transmission device includes a first circuit board, a conductive base, a connection element, a second circuit board, and a fixing element. The conductive base is fixed on the first circuit board. The connection element is disposed on the conductive base. The second circuit board is fixed on the connection element. The fixing element is disposed on the second circuit board, and connected to the conductive base by penetrating through the second circuit board and the connection element. The first circuit board is electrically connected to the second circuit board via the conductive base and the connection element.Type: GrantFiled: December 30, 2016Date of Patent: February 27, 2018Assignee: Delta Networks, Inc.Inventors: I-Wen Chan, Shu-Hong Chu, Kuo-Shung Huang
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Patent number: 9857678Abstract: A method of controlling distortion of an exposure process is provided. The method includes aligning an exposure mask with a wafer, forming a first test pattern on the wafer by performing a first exposure with the exposure mask and a first illumination system, forming a photoresist layer on an entire surface of the wafer including the first test pattern, performing a second exposure with the exposure mask and a second illumination system to form a second test pattern overlapping with the first test pattern, extracting a distortion value between the first test pattern and the second test pattern, and correcting the exposure mask or fabricating a corrected exposure mask using the distortion value.Type: GrantFiled: January 18, 2017Date of Patent: January 2, 2018Assignee: SK Hynix Inc.Inventors: Chan Ha Park, Shin Young Kim
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Patent number: 9817032Abstract: To provide a measurement device which allows long-term accurate measurement of voltage without adversely affecting a device under test, by ensuring a predetermined level of resistance to ESD and reducing leakage current. A measurement device includes a probe needle for contacting a device under test, a first FET for detecting voltage of the device under test, and a protection circuit for protecting the first FET from static electricity. The protection circuit includes a second FET having an oxide semiconductor film as a channel formation region.Type: GrantFiled: May 16, 2013Date of Patent: November 14, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kei Takahashi, Noboru Inoue
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Patent number: 9817062Abstract: A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.Type: GrantFiled: January 23, 2017Date of Patent: November 14, 2017Assignee: CELERINT, LLC.Inventor: Howard H. Roberts, Jr.
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Patent number: 9696402Abstract: Provided is a probe card inspection apparatus including: a substrate; a first insulating layer which covers the substrate; and a first detection unit which is formed on the first insulating layer and detects physical defects of a probe of a probe card. The first detection unit includes: a ground detection unit including a first conductive pattern which defines a plurality of openings which expose a portion of the first insulating layer and detect defects of a ground probe of the probe card and; and a signal and power detection unit including a second conductive pattern which defines a plurality of openings which expose another portion of the first insulating layer and detect defects of a signal and power supply probe of the probe card.Type: GrantFiled: November 26, 2014Date of Patent: July 4, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shin-ho Kang, Joon-su Ji, Jung-woo Kim
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Patent number: 9658279Abstract: A power semiconductor device includes a semiconductor body. The semiconductor body includes an active semiconductor region and a perimeter semiconductor region surrounding the active semiconductor region. The active semiconductor region has an active surface area, and the perimeter semiconductor region has a perimeter surface area. The power semiconductor device further includes a test structure for contactless testing of the perimeter semiconductor region. The test structure includes an electrically conductive path mounted on the perimeter surface area. The test structure is configured to extract energy from a remotely generated electromagnetic radio frequency test field.Type: GrantFiled: October 26, 2015Date of Patent: May 23, 2017Assignee: Infineon Technologies AGInventors: Eric Graetz, Hermann Bilban, Rudolf Pairleitner
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Patent number: 9595773Abstract: A probe pin has a coil spring having a first end and a second end, a first plunger having a major portion, and a first elastic extension and a second elastic extension that from the major portion in the same direction, and a second plunger forcedly inserted between the first and the second elastic extensions. The first and the second plungers have electric conductivity. The first and the second plungers are inserted from the first and second ends of the coil spring, respectively, so that the first and the second elastic extensions of the first plunger hold the second plunger with the first elastic extension making a forced contact with a surface of the second plunger to form thereat an electric connection between the first and the second plungers.Type: GrantFiled: July 18, 2014Date of Patent: March 14, 2017Assignee: OMRON CorporationInventors: Yoshinobu Hemmi, Takahiro Sakai, Hirotada Teranishi
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Patent number: 9551740Abstract: A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.Type: GrantFiled: May 18, 2012Date of Patent: January 24, 2017Assignee: CELERINT, LLC.Inventor: Howard H. Roberts, Jr.
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Patent number: 9128121Abstract: A mechanism is described for facilitating a dynamic electro-mechanical interconnect capable of being employed in a test system according to one embodiment. A method of embodiments of the invention may include separating, via a cavity, a first conductor of an interconnect from a second conductor of the interconnect, and isolating, via the cavity serving as a buffer, a first electrical path provided through the first conductor from a second electrical path provided through the second conductor.Type: GrantFiled: September 28, 2012Date of Patent: September 8, 2015Assignee: Intel CorporationInventors: Evan M. Fledell, Joe F. Walczyk, Dinia P. Kitendaugh
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Patent number: 9082474Abstract: An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer.Type: GrantFiled: April 21, 2011Date of Patent: July 14, 2015Assignee: Micron Technology, Inc.Inventor: Gerald L. Cadloni
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Publication number: 20150130488Abstract: An inspection apparatus capable of reducing the effect of noises is provided. An inspection apparatus according to the present invention includes a work table 26 on which an object, a fixed body 28 disposed above the work table 26, a probe assembly that holds a probe stylus 38a, a support base member 40 supported on the fixed body 28, a suspension mechanism 46 that supports the probe assembly 38 above the work table 26, and a signal circuit substrate 54 including therein an IC chip 54a that generates an inspection signal supplied to the probe stylus 38a, the signal circuit substrate 54 being supported by the suspension mechanism 46 below the suspension mechanism 46, in which the probe assembly 38 and the support base member 40 are electrically isolated from each other.Type: ApplicationFiled: October 23, 2014Publication date: May 14, 2015Inventor: Takayoshi KUDO
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Patent number: 9013204Abstract: A test system is provided. A printed circuit board (PCB) includes a plurality of traces and at least one test point. A central processing unit (CPU) socket including a plurality of first pins and a memory module slot including a plurality of second pins are disposed on the PCB. Each of the second pins is coupled to the corresponding first pin of the CPU socket via the corresponding trace. A CPU interposer board is inserted into the CPU socket, and a memory interposer board is inserted into the memory module slot. The traces form a test loop via the CPU interposer board and the memory interposer board. When an automatic test equipment (ATE) provides a test signal to the test loop via the test point, the ATE determines whether the test loop is normal according to a reflectometry result of the test signal.Type: GrantFiled: August 3, 2012Date of Patent: April 21, 2015Assignee: Wistron Corp.Inventors: Kuan-Lin Liu, Kuo-Jung Peng
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Patent number: 8970238Abstract: A probe module for testing an electronic device comprises at least two contacts, each contact including a first end portion extending in a first direction along a first line, a second end portion extending linearly in a second direction opposite from the first direction and along a second line, and a third curved portion extending between the first end portion and the second end portion. The first line is spaced apart from and in parallel with the second line, and the at least two contacts are spaced apart from each other in a direction perpendicular to the first line and the second line. Methods for making such a probe module are also taught.Type: GrantFiled: June 17, 2011Date of Patent: March 3, 2015Assignee: Electro Scientific Industries, Inc.Inventor: Douglas J. Garcia
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Publication number: 20150048857Abstract: A universal meter socket for portable test equipment has low insertion and extraction forces. The universal meter socket is durable and light in weight, providing a long service life. The universal meter socket contains field-cleanable terminals with replaceable wear components. The universal meter socket also optimizes short current paths for the high current section of the meter, further reducing equipment weight by reducing wire weight and volt-ampere (hereinafter sometimes VA) drive requirements for test equipment. The universal meter socket complies with ANSI C12.7-2005 REQUIREMENTS FOR WATTHOUR METER SOCKETS. The universal meter socket is generally intended for use with electricity meters that comply with ANSI C12 requirements.Type: ApplicationFiled: March 15, 2013Publication date: February 19, 2015Applicant: Radian Research, Inc.Inventors: Joseph P. Joyce, Robert L. Kindschi
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Publication number: 20150008948Abstract: A prober for testing devices in a repeat structure on a substrate is provided with a probe holder plate, probe holders mounted on the plate, and a test probe associated with each holder. Each test probe is displaceable via a manipulator connected to a probe holder, and a substrate carrier fixedly supports the substrate. Testing of devices, which are situated in a repeat structure on a substrate, in sequence without a substrate movement and avoiding individual manipulation of the test probes in relation to the contact islands on the devices, is achieved in that the probe holders are fastened on a shared probe holder plate and the probe holder plate is moved in relation to the test substrate.Type: ApplicationFiled: September 19, 2014Publication date: January 8, 2015Inventors: Frank-Michael Werner, Matthias Zieger, Sebastian Giessmann
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Patent number: 8884639Abstract: In one embodiment, a method for testing a plurality of singulated semiconductor die involves 1) placing each of the singulated semiconductor die on a surface of a die carrier, 2) mating an array of electrical contactors with the plurality of singulated semiconductor die, and then 3) performing electrical tests on the plurality of singulated semiconductor die, via the array of electrical contactors.Type: GrantFiled: August 27, 2009Date of Patent: November 11, 2014Assignee: Advantest (Singapore) Pte LtdInventors: James C. Anderson, Alan D. Hart, Kenneth D. Karklin
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Patent number: 8841932Abstract: A prober for testing devices in a repeat structure on a substrate is provided with a probe holder plate, probe holders mounted on the plate, and a test probe associated with each holder. Each test probe is displaceable via a manipulator connected to a probe holder, and a substrate carrier fixedly supports the substrate. Testing of devices, which are situated in a repeat structure on a substrate, in sequence without a substrate movement and avoiding individual manipulation of the test probes in relation to the contact islands on the devices, is achieved in that the probe holders are fastened on a shared probe holder plate and the probe holder plate is moved in relation to the test substrate.Type: GrantFiled: April 26, 2011Date of Patent: September 23, 2014Assignee: Cascade Microtech, Inc.Inventors: Frank-Michael Werner, Matthias Zieger, Sebastian Giessmann
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Publication number: 20140253162Abstract: A system for testing a device under test (DUT) includes a probe card and a test module. The probe card includes probe beds electrically coupled to a circuit board and a first plurality of electrical contacts coupled to the circuit board, which are for engaging respective ones of a plurality of electrical contacts of a test equipment module. Probes are coupled to respective probe beds and are disposed to engage electrical contacts of the DUT. The probe card includes a second plurality of electrical contacts coupled to the circuit board. The first and second pluralities of contacts are mutually exclusive. The test module includes a memory, a processor, and a plurality of electrical contacts electrically coupled to respective ones of the second plurality of electrical contacts of the probe card. The circuit board includes a first electrical path for electrically coupling the test equipment module to the test module.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mill-Jer WANG, Ching-Nen PENG, Hung-Chih LIN, Wei-Hsun LIN, Hao CHEN, Chung-Han HUANG
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Patent number: 8786301Abstract: A system for testing a device under test (DUT), in which electrical coupling among a module board, a low profile connector, and, a DIB is established by applying a pressure on the module board toward the DUT, is provided. The system includes a test head bracket secured inside a test head, the test head bracket includes the module board having a first section including a plurality of connectors to couple a test analyzer to the module board, a second section including a plurality of contacts pads to electrically couple the module board to the DUT, and, a flexible board to enable the first section to be placed at an angle with respect to the second section. The test head bracket also includes a module board stiffener mechanically securing the first section and the second section to the test head and the low profile connector electrically couples the module board to the DUT.Type: GrantFiled: June 16, 2010Date of Patent: July 22, 2014Assignee: Altera CorporationInventors: Adam J. Wright, Joseph W. Foerstel, Mark Andrew Banke, Ken A. Ito
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ASSEMBLY FOR OPTICAL BACKSIDE FAILURE ANALYSIS OF PACKAGE-ON-PACKAGE (POP) DURING ELECTRICAL TESTING
Publication number: 20140159758Abstract: A method and apparatus for testing a package-on-package digital device is provided. The method includes the steps of: affixing a top device onto a wing board; affixing a bottom device onto the wing board; connecting the top side solderballs of the bottom package to the bond fingers of the wing board. The wing board is then mounted onto a flat top socket. Once the mounting has been completed, the testing begins, and may use a solid immersion lens or optical diagnostic tool. The configuration of the flat top socket and wing board allows the optical diagnostic tool full access to the bottom device for the testing process and failure analysis.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Applicant: QUALCOMM INCORPORATEDInventors: Himaja H. Bhatt, Martin E. Parley, Martin L. Villafana -
Patent number: 8749256Abstract: The invention discloses a contacting device for a thin film solar cell, comprising a positioning plane for positioning the solar cell thereon, a contact element for electrically contacting the solar cell and a suction element, wherein the solar cell is arrangeable on the top side of the positioning plane, the contact element is arranged slideably in a direction orthogonal to the positioning plane and arranged slideably through an opening of the positioning plane, and the suction element is arranged on the bottom side of the positioning plane for sucking air through the opening. The contacting device allows for obtaining improved measurement accuracy.Type: GrantFiled: September 2, 2010Date of Patent: June 10, 2014Assignee: Tel Solar AGInventors: Marco Apolloni, Jean Randhahn
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Patent number: 8624621Abstract: In an embodiment, a chuck to support a solar cell in hot spot testing is provided. This embodiment of the chuck comprises a base portion and a support portion disposed above the base portion. The support portion is configured to support the solar cell above the base portion and to define a cavity between a bottom surface of the solar cell and the base portion that thermally separates a portion of the bottom surface of the solar cell from the base portion.Type: GrantFiled: July 15, 2013Date of Patent: January 7, 2014Assignee: SunPower CorporationInventors: Jose Francisco Capulong, Emmanuel Abas
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Patent number: 8558568Abstract: A ground terminal has a cylindrical main body. A signal terminal has a terminal main body that is disposed on the inside of the cylindrical main body, and a connecting plate portion that extends from an end portion of the terminal main body. Additionally, a ground terminal has at least three connecting plate portions that are disposed so as to encompass the connecting plate portion of the ground terminal, each extending from mutually different positions on an edge of the cylindrical main body.Type: GrantFiled: May 18, 2011Date of Patent: October 15, 2013Assignees: Molex Japan Co., Ltd., Advantest CorporationInventors: Ryo Uesaka, Jun Watanabe, Akinori Mizumura, Hirotaka Wagata
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Patent number: 8531198Abstract: A substrate support unit adapted for a system for testing or processing of a substrate is provided. The substrate support unit includes a support table having at least one substrate carrier structure adapted to support a substrate, wherein the substrate carrier structure is electrically floating with respect to ground.Type: GrantFiled: June 16, 2010Date of Patent: September 10, 2013Assignee: Applied Materials, Inc.Inventor: Bernhard Gunter Mueller
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Patent number: 8519729Abstract: In an embodiment, a chuck to support a solar cell in hot spot testing is provided. This embodiment of the chuck comprises a base portion and a support portion disposed above the base portion. The support portion is configured to support the solar cell above the base portion and to define a space between a bottom surface of the solar cell and the base portion that thermally separates a portion of the bottom surface of the solar cell from the base portion.Type: GrantFiled: February 10, 2010Date of Patent: August 27, 2013Assignee: SunPower CorporationInventors: Jose Francisco Capulong, Emmanuel Abas
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Patent number: 8508247Abstract: An embodiment of an electrical connecting apparatus comprises a probe base plate and a plurality of contacts provided with tips to be pressed against electrodes of a device under test and arranged on the underside of the probe base plate. The distance dimensions from an imaginary plane parallel to the probe base plate to the tips of the contacts are made the greater toward the center of the probe base plate.Type: GrantFiled: February 1, 2010Date of Patent: August 13, 2013Assignee: Kabushiki Kaisha Nihon MicronicsInventors: Katsuji Hoshi, Akihisa Akahira, Yoshinori Kikuchi
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Patent number: 8427184Abstract: An SCR module tester facilitates rapid testing of SCR modules by a series of tests that are tailored to detect faults without applying full power to the modules. The SCR tester includes a quick clamp connector that is able to securely and easily clamp SCR modules for both the F/A-18 A/D GCU and F/A-18-E/F GCU facilitating the rapid testing of SCR modules.Type: GrantFiled: March 22, 2011Date of Patent: April 23, 2013Assignee: The United States of America as represented by the Secretary of the NavyInventor: Dexter T Kan