Abstract: In an embodiment, a brown-out protection circuit includes: a monitoring terminal; a threshold generator supplying a threshold voltage; a comparator to compare a monitoring voltage at the monitoring terminal and the threshold voltage; and a logic module supplying an enable signal having a brown-in logic value and a brown-out logic value. When the enable signal is at the brown-out logic value, the logic module checks transition conditions, relating to a number of usable transitions of the monitoring voltage from lower to greater than the threshold voltage, and time conditions, relating to permanence of the monitoring voltage above the threshold voltage after a usable transition or in an aggregated manner after a plurality of consecutive usable transitions. The logic module sets the enable signal to the brown-in logic value when the transition conditions or the time conditions are met.

Abstract: Disclosed herein is a performance monitor for a functional block of a system, the performance monitor comprising a counter circuit, wherein the counter circuit includes a programmable time window counter configured to determine an adjustable counting period, and an event counter coupled to the time window counter. The event counter is configured to count a number of occurrences of an event occurring in the functional block during the counting period, and record the number of occurrences of the event during the counting period and generate an output trigger signal when the number of occurrences of the event during the counting period is outside of a programmable threshold band, or after receiving an input trigger signal from a cross trigger network triggered by other performance monitors in electrical communication with the cross trigger network.

Abstract: A receiver is provided that receives signals from a device under test (DUT) for one or more modes of operation. For each mode, the system detects beacon transmission signals from the DUT, and counts the number of beacons for a period of time. If the count is not consistent with an expected count, e.g. a stored value, the system may preferably provide an output to indicate that there is a problem with the DUT. If the count is consistent with the expected count, the system may preferably perform further testing for other modes of operation. If the count output of the DUT is consistent with expected counts over each of the operation modes, the system may provide an indication that the DUT has passed the beacon tests.

Abstract: A method for detecting and responding to disturbances in a HVAC system using a noisy measurement signal and a signal filter is provided. The method includes detecting a deviation in the noisy measurement signal, resetting the filter in response to a detected deviation exceeding a noise threshold, filtering the noisy measurement signal using the signal filter to determine an estimated state value, and determining that a disturbance has occurred in response to the estimated state value crossing a disturbance threshold. In some embodiments, the method further includes performing one or more control actions in response to the detection of a disturbance.

Abstract: A display control apparatus is provided. Every time when the level of the signal is obtained, the peak display with respect to the level of the signal is initiated by the first peak display control unit in a predetermined display manner in the display position obtained by the peak position obtaining unit. On the other hand, the previous peak displays being displayed according to the level of the signal obtained at a previous time and a time before the previous time is continued, and the display manner of the previous peak display being displayed is changed according to the second peak display control unit. Accordingly, while one and more than one level are simultaneously displayed on one display device, the temporal sequence of the levels, which is simultaneously displayed with different display manners, can be recognized by the user.

Abstract: Provided is a measurement apparatus that measures an input signal, comprising a plurality of first comparators that each receive the input signal, have a common first reference level set therein, and compare a signal level of the input signal to the first reference level; and a level-crossing timing detecting section that detects a level-crossing timing at which the signal level crosses the first reference level, based on comparison results of the first comparators.

Abstract: A microorganism number-measuring apparatus includes: a container holder for holding container having an opening in the upper surface of the container, with the opening being positioned upward; and a rotary driver for rotating a liquid accommodated in container held by the holder, about the rotary axis in the up-and-down direction. Moreover, the apparatus includes: an electrode inserting part for inserting measurement chip to a position from above container held by the holder, via the opening, with the position being closer to the container's inner surface than to the container's center axis and being away from the container's inner surface with a predetermined distance; and a measurement unit for measuring microorganisms using measurement electrode of measurement chip inserted into container by the electrode inserting part. The electrode inserting part holds measurement chip, in a state of measurement electrode facing the container's inner-surface.

Abstract: A receiver is provided that receives signals from a device under test (DUT) for one or more modes of operation. For each mode, the system detects beacon transmission signals from the DUT, and counts the number of beacons for a period of time. If the count is not consistent with an expected count, e.g. a stored value, the system may preferably provide an output to indicate that there is a problem with the DUT. If the count is consistent with the expected count, the system may preferably perform further testing for other modes of operation. If the count output of the DUT is consistent with expected counts over each of the operation modes, the system may provide an indication that the DUT has passed the beacon tests.

Abstract: A built-in self-test (BIST) circuit for detecting power supply droops is disclosed. In one embodiment, the BIST circuit includes a transition circuit configured to launch logical signals into a delay line. The BIST circuit also includes a comparator configured to compare a logic signal based on that input into the delay line with one output from the delay line. A mismatch resulting from the comparison is indicative of a power supply droop. The BIST circuit may also include circuitry for calibrating the delay line. The calibration may be performed by enabling a feedback path between the output of the delay line and its input. Enabling the feedback path may form a ring oscillator utilizing the delay line. A counter may count the number of transitions caused by the ring oscillator in a predetermined time. The resulting count may be used to determine if the delay is in a desired range.

Abstract: An RF test and measurement device, including a front end for receiving a time-varying signal and a real-time engine for generating digital frequency domain spectrums based on the time-varying signal. The device also includes a memory subsystem containing a frequency domain bitmap which is updated through sequential receipt and storage of the digital frequency domain spectrums. The real time engine is further configured to monitor the frequency domain bitmap for occurrence of a signal characteristic, and in response to detection of the signal characteristic, cause a capture of the time-varying signal into a storage location of the RF test and measurement device.

Abstract: A device for counting oscillations of an oscillating temporal signal. The device comprises means for counting all the alternate crossings of a positive threshold value and of a negative threshold value by a monitored time signal.

Abstract: A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

Abstract: A pulse height analyzer for determination of the pulse height distribution of electronic pulses includes a set of comparators with a common input for analogue to digital conversion of the electronic pulses, a set of latches wherein the inputs of the latches are connected to the outputs of respective comparators for recording passage of the corresponding threshold voltages by the rising edge of a pulse, a priority encoder connected to the latch outputs for determination of a pulse height category consisting of pulses with a pulse height within a pulse height interval defined by respective threshold voltages, and a micro controller that is adapted to count the number of pulses within each pulse height category.

Abstract: A system and method for enhanced frequency measurement. Embodiments provide an effective mechanism for reducing error associated with frequency measurements by amplifying the frequency of the signal fed to the frequency counter, thereby increasing the number of counts and reducing the error associated with each frequency measurement. Reductions in error enable the gate time for the frequency counter to be reduced, thereby increasing efficiency and cost-savings. After accessing the counts provided for the amplified frequency, the original frequency before amplification may be determined by reducing the amplified frequency (e.g., represented by the accessed counts) by the amount by which the original frequency was amplified. Embodiments provide an effective and efficient mechanism for automatically determining the amount of amplification for a given signal based upon its frequency and a maximum frequency of at least one of the frequency amplification component and the frequency counter.

Abstract: In order to stably measure an input interval time of a pulse signal with high precision, a time interval measuring apparatus includes a reference signal generator, a phase shifter, first and second A/D converters, an error correction unit, an instantaneous phase calculation unit, and an interval time calculation unit. The phase shifter divides a reference signal of a sine wave having a predetermined frequency from the reference signal generator into a first analog signal and a second analog signal having phases shifted to each other. The first and second A/D converters perform sampling of the first analog signal and the second analog signal from the phase shifter, respectively, at an input timing of a pulse signal to be measured, and output a first and second digital sample values.

Abstract: Certain exemplary embodiments can include an arc fault detection circuit. The arc fault detection circuit can include a zero crossing analysis sub-system including a counter configured to determine, for a first waveform, a count of dips that occur between a pair of predetermined zero crossings of a second waveform. The second waveform can be obtained from an electrical circuit.

Abstract: A built-in self-test apparatus for a digital-to-analog converter uses a differentiation unit for differentiating a digital-to-analog (DA) signal to obtain the differences between pulses of the analog signal. Next, the analog signal is converted into a digital signal in the light of a threshold voltage by a Schmitt trigger unit. Then, the duty cycles of the digital signal are calculated by a duty cycle retriever, and transmitted into a signature analyzer to calculate the differential non-linearity for error analysis. For processing a high-speed DA signal, the circuit disposed before the differentiation unit may use a test pattern unit, a sample-and-hold circuit and a logic circuit to lower the speed of the DA signal.

Abstract: A capacitance detection apparatus includes a first open/close switch provided between both ends of a standard capacitor, one end of the standard capacitor being connected to a first voltage source, a second open/close switch provided between one end of a first capacitor to be measured and the other end of the standard capacitor, the other end of the first capacitor to be measured being connected to a second voltage source or free space, a third open/close switch provided between both ends of the first capacitor to be measured, a voltage measurement means for measuring voltage of the other end of the standard capacitor, a switch control means for performing a first switching control performing a first switching operation to open the first open/close switch after closing thereof, performing a second switching operation to open the second open/close switch after closing thereof, and a third switching operation to close the third open/close switch after closing thereof, wherein the second and third switching oper

Abstract: An analog signal measuring device for measuring an analog signal includes a digital controller, a waveform converter and a comparator. The digital controller includes a PWM controller for outputting a pulse signal having an adjustable pulse width to the waveform converter, which converts the pulse signal into a sawtooth wave or a triangle wave for output as a carrier signal. Next, the comparator feeds a comparison pulse signal, which is obtained by comparing the carrier signal to the analog signal, to the digital controller, which enables or disables the counter to generate a count value corresponding to the comparison pulse signal. Since the count value depends on the comparison pulse signal and the type of the comparison pulse signal is directly related to the analog signal, the digital controller may get the analog signal according to the count value.

Abstract: Sampling is performed. A strobe signal is generated from a first signal. Multiple sampled signals are sampled using the strobe signal. Each of the multiple sampled signals is synchronous with its own clock reference and each of clock references are asynchronous with respect to each other. Analog-to-digital conversion is performed on each sampled value of each of the multiple sampled signals. For each of the clock references that is not synchronous with the first signal, a phase comparison is performed between the clock reference and the first signal to produce a difference value. The difference value indicates a phase difference between the clock reference and the first signal. Analog-to-digital conversion of the difference value is performed at a frequency determined by the strobe signal.

Abstract: A digital envelope detector (consisting of both hardware and software) that provides accurate measurements of changes of peak values of an AC signal (these peak values constitute the envelope of a signal). Such accurate envelope measurements are required to optimize the accuracy and selectivity of chemical sensors. A signal of interest is compared to each of a set of accurately calibrated reference voltages provided by a digital to analog converter. A digital logic circuit and software respond each time the signal fails to exceed the current reference voltage. In that event, relevant data (time or cycle count) are digitally recorded and a new reference voltage is installed. The process is repeated until the desired range of change of signal is measured.

Abstract: According to the invention, the signal is sampled, it is digitised, it is broken up into sub-bands. In each sub-band, the signal is modelled by an auto-regressive filter the transfer function of which is of the form 1/A(z). By an adaptive method that is recursive in time and in order, all the polynomials A(z) that have a degree between 1 and a maximum value are calculated. The order of the model is estimated and the polynomial that has this order is retained. The roots of this polynomial are calculated and the components are monitored. The frequency and the amplitude of the sinusoidal components of the signal are thus obtained.

Abstract: A frequency change measuring device includes frequency divider for frequency dividing a measuring signal to produce frequency-divided signals, first counter for counting the frequency-divides signals to calculate frequency-division numbers, frequency division numbers transmitter for transmitting the frequency division numbers in synchronism with the frequency-divided signals, frequency division numbers receiver for receiving the frequency division numbers transmitted from the frequency division numbers transmitter, second counter for counting outputs of a reference clock generator synchronized with a timekeeping device that keeps the standard time, latch unit for latching a count of frequency outputs of the reference clock generator synchronous for generating reference clocks on the basis of signals synchronous with the frequency division numbers, and operations unit for determining a frequency change on the basis of the count and the frequency division numbers.

Abstract: A circuit configuration for measuring at least one operating parameter for an integrated circuit includes an analysis circuit connected to at least one external connection on the integrated circuit. The analysis circuit detects a plurality of voltage level changes on the external connection, which is used to control a method of operation for the integrated circuit, in particular, and supplies them to a counter circuit that logs at least one digitally coded value. The coded value is, then, output for analysis purposes to ascertain at least one operating parameter. This, advantageously, allows an average mode of operation for the integrated circuit to be logged during operation of the circuit in the application using parameters and allows respective operating states to be ascertained therefrom.

Abstract: Outputs of a linear RF detector and a logarithmic RF detector are multiplexed individually to a single digitizer or simultaneously to a respective digitizers. A process generates a composite waveform from the resulting digitized data, either at a later time in the former case or in real-time in the latter case. To achieve simultaneous routing, several routing relays are arranged in a specialized configuration between the outputs of the RF detectors and the inputs of the digitizers.

Abstract: A digitally controlled adaptive driver and method for sensing a capacitive load are included. The driver comprises a load sensing circuit for sensing a voltage of an output terminal of the driver connected to a load and for generating a control signal in response to the voltage of the output terminal, and a control driver for digitally determining a value of the load coupled to the output terminal in response to the control signal of the load sensing circuit and for controlling the driving current for driving an input signal in response to the value of the load.

Abstract: Measuring timing variations in a periodic signal includes producing trigger signals in an integrated circuit in response an externally-generated periodic signal. First and second oscillation signals are generated in response to the trigger signals. A first count of the number of pulses in the first oscillation signal from occurrence of the first oscillation signal until the oscillation signals are in phase and providing a second count of the number of pulses in the second oscillation signal from occurrence of the second oscillation signal until the oscillation signals are in phase.

Abstract: Measuring timing variations in a periodic signal includes producing trigger signals in an integrated circuit in response an externally-generated periodic signal. First and second oscillation signals are generated in response to the trigger signals. A first count of the number of pulses in the first oscillation signal from occurrence of the first oscillation signal until the oscillation signals are in phase and providing a second count of the number of pulses in the second oscillation signal from occurrence of the second oscillation signal until the oscillation signals are in phase.

Abstract: In an evaluation method for a particle counter, a detector generates a signal in response to the presence of particles in a measuring area in which a liquid flow is conveyed. The sensor signal is treated by a signal processing device and is converted into a display value, taking into account at least one calibration factor. The sensor signal is treated in such a way that the individual residence times of the particles in the measuring zone are determined within a given lapse of time and a summated signal is formed by summating the residence times. The signal is used to represent the display value, taking into account the at least one calibration factor. A device for carrying out this includes a signal processing unit with a comparator circuit, a clock-pulse generator and a summation device in the form of a pulse counter, for example, in order to form the summated signal.

Abstract: A monolithic sensor includes a reference channel and at least one sensing channel. Each sensing channel has an oscillator and a counter driven by the oscillator. The reference channel and the at least one sensing channel being formed integrally with a substrate and intimately nested with one another on the substrate. Thus, the oscillator and the counter have matched component values and temperature coefficients. A frequency determining component of the sensing oscillator is formed integrally with the substrate and has an impedance parameter which varies with an environmental parameter to be measured by the sensor. A gating control is responsive to an output signal generated by the reference channel, for terminating counting in the at least one sensing channel at an output count, whereby the output count is indicative of the environmental parameter, and successive ones of the output counts are indicative of changes in the environmental parameter.