Abstract: A control system includes a control unit configured to control a target controlled apparatus, and at least one communication processing unit configured to execute communication processing in communication between the target controlled apparatus and the control unit, and in the control system, the communication processing unit sequentially measures a processing time of the communication processing and sequentially outputs delay information indicating the measured processing time to the control unit, and the control unit sequentially acquires the delay information from all of a plurality of the communication processing units, and sequentially updates delay information incorporated in a control algorithm for controlling the target controlled apparatus based on the acquired delay information.

Abstract: A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare homogenous subarrays, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Configuration data is distributed using a statically reconfigurable bus system, to implement the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.

Abstract: A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.

Abstract: This invention comprises a new way to connect a control, CK, and data, D, signal into a basic cross-coupled INV pair, and into certain other basic sequential logic circuits, to control the writing in of a new data value, D, into the sequential logic circuit cell. The invention concerns logic circuit in complementary metal-oxide-semiconductor (CMOS) technology. It connects additional p-type and n-type MOSFET devices in a novel manner to accomplish the desired control functions.

Abstract: An architecture for a Field Programmable Gate Array (FPGA) that better supports the designs of finite state machines (FSMs) generated by High-Level Synthesis (HLS) tools. The architecture is based on categorizing states of a FSM into branch free path states and independent states. A memory unit stores next state information for independent states and an accumulator unit computes next state information for branch free path states. A control unit selects the next state based on either the memory unit or the accumulator unit. An input sequence encoder encodes external inputs and current state values into encoded sequence signals that are input to the memory unit. Also disclosed is a state assignment algorithm that assigns state values to states of the FSM by first identifying branch free paths that terminate on the same state and then eliminating overlap between paths. States along the same branch free path are assigned sequential values.

Abstract: A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.

Abstract: Disclosed is an interface circuit, a chip containing an interface circuit and a manufacturing method thereof. The interface circuit includes an I/O processing sub-circuit, a path selection sub-circuit, and at least two I/O ports. The I/O processing sub-circuit, the path selection sub-circuit, and the at least two I/O ports are electrically connected in sequence. The path selected by the path selection sub-circuit can enable a first and a second electrical signal to be transmitted through the I/O ports that are configured to correspond to the ports of the external device through which the first and second electrical signals are transmitted. That is, the path selection sub-circuit can customize the layout of the signal-input/output I/O ports of the interface circuit according to the layout of the ports of the external device.

Abstract: An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.

Abstract: An electronics-harmful-radiation (EHR) monitoring system includes an EHR measurement circuit. The EHR measurement circuit includes a first device, a single event upset (SEU) detector circuit configured to determine a first number of SEUs of the first device during a first period, and an EHR measurement generator configured to generate a first EHR value based on the first number of SEUs and the first period.

Abstract: A system, method, and computer readable medium for statistical application-agnostic fault detection of multi-process applications. The computer readable medium includes computer-executable instructions for execution by a processing system. A multi-process application runs on a host. Interceptors collect statistical events and sends said events to a statistical fault detector. The statistical fault detector creates one or more distributions and compares recent statistical event data to historical statistical event data and uses deviation from historical norm for fault detection. The present invention detects faults both within the application and within the environment wherein the application executes, if conditions within the environment cause impaired application performance. The invention also teaches consensus fault detection and elimination of cascading fault notifications based on a hierarchy of events and event groups.

Abstract: A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

Abstract: A back-feed protection circuit includes input circuits and a control circuit. Each input circuit includes an input for receiving an input DC voltage. The control circuit is configured to enable one of the first input circuit and the second input circuit having the highest input DC voltage, and disable the other input circuit to substantially prevent current from back feeding to the first input circuit and/or the second input circuit. Each input circuit additionally and/or alternatively includes a positive rail, a reference rail and a plurality of switching devices. A set of the switching devices are coupled in series in the positive rail of each input circuit, and another set of the switching devices are coupled in series in the reference rail of each input circuit. Other example back-feed protection circuits, and electric power supplies including back-feed protection circuits are also disclosed.

Abstract: Various implementations of a method, system, and computer program product for pattern matching using a reconfigurable array processor are disclosed. In one embodiment, a processor array manager of the reconfigurable array processor receives an input data stream for pattern matching and generates a tokenized input data stream from the input data stream. A different portion of the tokenized input data stream is provided to each of a plurality of processing elements of the reconfigurable array processor. Each processing element can compare the received portion of the tokenized input data stream against one or more reference patterns to generate an intermediate result that indicates whether the portion of the tokenized input data stream matches a reference pattern. The processor array manager can combine the intermediate results received from each processing element to yield a final result that indicates whether the input data stream includes a reference pattern.

Abstract: Various implementations of a method, system, and computer program product for pattern matching using a reconfigurable array processor are disclosed. In one embodiment, a processor array manager of the reconfigurable array processor receives an input data stream for pattern matching and generates a tokenized input data stream from the input data stream. A different portion of the tokenized input data stream is provided to each of a plurality of processing elements of the reconfigurable array processor. Each processing element can compare the received portion of the tokenized input data stream against one or more reference patterns to generate an intermediate result that indicates whether the portion of the tokenized input data stream matches a reference pattern. The processor array manager can combine the intermediate results received from each processing element to yield a final result that indicates whether the input data stream includes a reference pattern.

Abstract: Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.

Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.

Abstract: In accordance with an embodiment, an electronic circuit includes at least five redundant circuit parts, which are configured to execute the same function in order to provide redundancy. The at least five redundant circuit parts are arranged in such a way that critical nodes of fewer than half of the circuit parts lie on an imaginary straight line.

Abstract: The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs.

Abstract: A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. In an example, an apparatus includes a first chip comprising a first processing system and a first configurable NoC connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first and second configurable NoCs are connected together via an external connector. The first and second processing systems are operable to obtain first and second information from off of the first and second chip and configure the first and second configurable NoCs based on the first and second information, respectively. The first and second processing systems are communicatively coupled with each other via the first and second configurable NoCs when the first and second configurable NoCs are configured based on the first and second information, respectively.

Abstract: An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130). The processor (130) is coupled to the on-chip boot ROM (132) and to the non-volatile security identification element (140) to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element (140). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.

Abstract: Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.

Abstract: An electronic device with one or more gates that each include first circuit blocks configured for implementing a first N-type logic function and second circuit blocks configured for implementing a second N-type logic function that is a complement of the first N-type logic function. In the electronic device, a number of the of first circuit blocks and a number of the second circuit blocks are the same. Further, the first circuit blocks and the second circuit blocks each have a block feedback node, a block output node, and one or more block input logic nodes. Also, the block feedback node for each one of the first circuit blocks is singly coupled to the block output node of one of the second circuit blocks and the block output node of the one of the first circuit blocks is singly coupled to the block feedback node of another of the second circuit blocks.

Abstract: Disclosed are a latch circuit and method for preventing double node upsets (DNUs). A first, second, and third storage circuit, each comprising four inputs and an output, are electrically interconnected with a first and second three-input c-element circuit, each comprising three inputs and an output, and a two-input c-element circuit comprising two inputs and an output. The output of the first storage circuit is connected to a first input of the first three-input c-element circuit, a first input of the third storage circuit and a third input of the second storage circuit. The output of the second storage circuit is connected to a second input of the first three-input c-element circuit, a first input of the two-input c-element circuit, and a second input of the second three-input c-element circuit.

Abstract: The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs.

Abstract: Aspects extend to methods, systems, and computer program products for locally restoring functionality at acceleration components. A role can be locally restored at an acceleration component when an error is self-detected at the acceleration component (e.g., by local monitoring logic). Locally restoring a role can include resetting internal state (application logic) of the acceleration component providing the role. Self-detection of errors and local restoration of a role is less resource intensive and more efficient than using external components (e.g., high-level services) to restore functionality at an acceleration component and/or to reset an entire graph. Monitoring logic at multiple acceleration components can locally reset roles in parallel to restore legitimate behavior of a graph.

Abstract: It is detected that an error has occurred on an FPGA while the FPGA is operating in a first mode, wherein the error is not correctable by the FPGA itself. The FPGA is configurable to operate in the first mode in which a set of processing steps is to be performed by a first set of logic cells within the FPGA, or in a second mode in which at least a portion of the set of processing steps is to be performed outside the FPGA enabled by a second set of logic cells within the FPGA. An error location associated with the error is identified. In the event that the error location is deemed to have occurred in a critical subset of the first set of logic cells: the FPGA is switched to operate in the second mode; at least one of the first set of logic cells is reconfigured; and upon successful reconfiguration, the FPGA is switched to operate in the first mode.

Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections. Other apparatuses and methods are disclosed.

Abstract: A coprocessor (PL) is disclosed. The PL includes a memory router, at least one collection block that is configured to transfer data to/from the memory router, each collection block includes a collection router that is configured to i) transfer data to/from the memory router, ii) transfer data to/from at least one collection router of a neighboring collection block, and iii) transfer data to/from blocks within the collection block, and at least one programmable operator that is configured to i) transfer data to/from the collection router, and ii) perform a programmable operation on data received from the collection router.

Abstract: The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs.

Abstract: A system for data storage includes one or more non-volatile memory (NVM) devices, each device including multiple memory blocks, and a processor. The processor is configured to assign the memory blocks into groups, to apply a redundant data storage scheme in each of the groups, to identify a group of the memory blocks including at least one bad block that renders remaining memory blocks in the group orphan blocks, to select a type of data suitable for storage in the orphan blocks, and to store the data of the identified type in the orphan blocks.

Abstract: A semiconductor device includes: first to Nth input terminals (where N is an integer equal to or greater than 2); and a redundant input terminal. When a Kth input terminal (where K is an integer ranging from 1 to N?1) is defective among the first to Nth input terminals, (K+1)th to Nth input terminals receive signals of Kth to (N?1)th input terminals, respectively, and the redundant input terminal receives a signal of the Nth input terminal.

Abstract: In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.

Abstract: A semiconductor device may include: a plurality of output paths, which include a plurality of through silicon vias (TSVs), respectively, and suitable for transmission of test confirmation information; an information provider suitable for providing the test confirmation information to the plurality of TSVs; and an output controller suitable for selectively blocking one of the output paths including a failed one among the plurality of TSVs.

Abstract: A storage controller determines a presence of an indication from an Input/Output (I/O) enclosure that the I/O enclosure will perform a shutdown after a predetermined amount of time. The storage controller determines whether the I/O enclosure provides a last path to data stored in a storage device. A request is transmitted to the I/O enclosure to perform either an orderly shutdown or abort the shutdown, based on the whether the I/O enclosure provides the last path to the data stored in the storage device.

Abstract: In a device including a programmable circuit, the programmable circuit is connected to a non-volatile memory in which configuration information is stored, and another memory having a faster reading speed than the non-volatile memory, and the programmable circuit includes a configuration memory control circuit, and a signal line group for performing reading with respect to the other memory such as a volatile memory and an embedded memory from the non-volatile memory by the configuration memory control circuit, and copies a part of circuit configuration information which is required to be subjected to fast restoration from failure into the other memory.

Abstract: A CMOS (complementary metal oxide semiconductor) inverter includes a PMOS (p-channel metal oxide semiconductor) transistor configured to receive a first input signal via a first input terminal and output a first output signal via a first output terminal, an NMOS (n-channel metal oxide semiconductor) transistor configured to receive a second input signal via a second input terminal and output a second output signal via a second output terminal, and a resistor configured to provide an isolation between the first output signal and the second output signal. In an embodiment, the first input signal is of a fast high-to-low transition but a slow low-to-high transition, and the second input signal is of a fast low-to-high transition but a slow high-to-low transition. A comparative method is also provided.

Abstract: A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance.

Abstract: A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.

Abstract: The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM.

Abstract: A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

Abstract: Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic blocks that are individually controllable by the selection logic. The selectable logic blocks include respective instances of a redundant logic block, and respective instances of an interface logic block that selectively disable the redundant logic blocks in the integrated circuit.

Abstract: A circuit structure (200) for suppressing single event transients (SETs) or glitches in digital electronic circuits is provided. The circuit structure includes a first input (100) which receives an output of a digital electronic circuit (A), a second input (100?) which receives a redundant or duplicated output of the digital electronic circuit (A?), and two sub-circuits (102, 106) that each receive the inputs and have one output. One of the sub-circuits is insensitive to a change in the value of one of its inputs when the inputs are in a first logic state and the other sub-circuit is insensitive to a change in the value of one of the inputs when the inputs are in a second, inverted logic state. The sub-circuit outputs are input into a two-input multiplexer (202) which has its output (204) connected to its selection port (SEL), and the sub-circuits are arranged so that the sub-circuit which is insensitive to a change in the value of one of its inputs is selected whenever the output of the multiplexer changes.

Abstract: A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.

Abstract: A circuit structure (200) for suppressing single event transients (SETs) or glitches in digital electronic circuits is provided. The circuit structure includes a first input (100) which receives an output of a digital electronic circuit (A), a second input (100?) which receives a redundant or duplicated output of the digital electronic circuit (A?), and two sub-circuits (102, 106) that each receive the inputs and have one output. One of the sub-circuits is insensitive to a change in the value of one of its inputs when the inputs are in a first logic state and the other sub-circuit is insensitive to a change in the value of one of the inputs when the inputs are in a second, inverted logic state. The sub-circuit outputs are input into a two-input multiplexer (202) which has its output (204) connected to its selection port (SEL), and the sub-circuits are arranged so that the sub-circuit which is insensitive to a change in the value of one of its inputs is selected whenever the output of the multiplexer changes.

Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.

Abstract: Integrated circuit packages with a signal routing control through a given direction are disclosed. A disclosed integrated circuit package includes a plurality of interconnects. A first logic circuitry of a first integrated circuit may produce a first signal that may be transmitted to a second integrated circuit. The integrated circuit package further includes interconnect circuitry disposed between the first and second integrated circuits. Multiplexing circuitry may select the first signal from second logic circuitry when the first logic circuitry is defective and may direct the signal as output signal to the second integrated circuit through a given interconnect.

Abstract: Methods and a system for operating a programmable device are disclosed. In one embodiment, a method includes accessing a master summary data and loading an original configuration data to configuration registers of the programmable device. The method further includes generating a current summary data by performing a summary operation of a current configuration data of the configuration registers of the programmable device, comparing the current summary data with the master summary data, and performing an exception action if the current summary data does not match with the master summary data.

Abstract: A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.