Abstract: In an example, a configurable block for a programmable device of a plurality of programmable devices in an integrated circuit (IC) includes a first flip-flop having a data port coupled to an output of an interface block of the programmable device, a clock port coupled to a first clock input, and an output port coupled to a first output. The configurable block further includes a second flip-flop having a data port coupled to the output of the interface block, a clock port coupled to the first clock input, and an output port coupled to a second output, and a first multiplexer having a first input port coupled to the output port of the first flip-flop, and a second input port coupled to the output port of the second flip-flop. The configurable block further includes a third flip-flop having an input port coupled to an output of the first multiplexer, a clock port coupled to a second clock input, and an output port coupled to a third output.

Abstract: An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

Abstract: A multi-chip module hybrid integrated circuit (MCM-HIC) provides cold spare support to an apparatus comprising a plurality of ICs and/or other circuits that are not cold spare compliant. At least one core IC and at least one cold spare chiplet are installed on an interconnecting substrate having a plurality of power zones to which power can be applied and withdrawn as needed. When powered, the cold spare chiplets serve as mediators and interfaces between the non cold spare compliant circuits. When the cold spare chiplets are at least partly unpowered, they protect all interconnected circuits, and ensure that interconnected circuits that remain powered are not hindered by unpowered interconnected circuits. Cold spare chiplets can extend across boundaries between power zones. External circuits can be exclusively interfaced to a subset of the power zones. Separate power circuits within a power zone can be sequenced during application and withdrawal of power.

Abstract: An SEU immune flip-flop includes a master stage data latch having an input, an output, a clock input, being transparent in response to a clock signal first state and being latched in response to a clock signal second state, a slave stage data latch having an input coupled to the master stage data latch output, an output, a scan output, a slave latch clock input, a scan slave latch having an input coupled to the slave stage data latch scan output, an output, and a clock input, being transparent in response to the clock signal second state and being latched in response to the clock signal first state. The slave stage data latch includes a switched inverter disabled when the slave latch is in a transparent state and enabled when the slave latch is in a latched state having a time delay longer than an SEU time period.

Abstract: A system for limiting or diminishing current to unpowered Serializer/Deserializer (SerDes) circuitry is provided. The system comprises receiver input termination circuitry and a cold spare circuitry. The receiver input circuitry comprises a termination resistor and an N-type metal oxide silicon field effect transistor (MOSFET). The cold spare circuitry comprises a first MOSFET and a second MOSFET. When the system is powered on, an input current flows to the receiver input termination circuit to be discharged by the N-type MOSFET which is electrically connected to a ground. When the system is powered off, the input current flows to the cold spare circuitry to discharge the input current. Discharging electrons between the first MOSFET and the second MOSFET depends on the polarity of an accumulated voltage.

Abstract: A non-volatile memory having a double metal layout is provided that includes a first fuse fabricated on a first conductive layer of the integrated circuit, a second fuse fabricated on a second conductive layer of the integrated circuit, and a transistor fabricated on front-end-of-the-line (FEOL) structure of the integrated circuit. A first memory cell of the non-volatile memory is provided by a first memory circuit comprising the first fuse and the transistor, and a second memory cell of the non-volatile memory is provided by a second memory circuit comprising the second fuse and the transistor.

Abstract: A display comprises a plurality of autonomous pixels on a substrate. Each autonomous pixel comprises a display element, a sensing element and a control element. The sensing element is arranged to detect an external stimulus and the control element is arranged to generate, entirely within the autonomous pixel, a control signal to drive the display element based, at least in part, on a magnitude of the external stimulus detected by the sensing element. Additionally, the control element comprises one or more groups of transistors, each group comprising two or more transistors arranged to perform the same function and connected in parallel with each other.

Abstract: A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node, a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node, a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on, and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on.

Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.

Abstract: An analog majority voting circuit is formed of a cascade of two differential amplifiers and decouples heavily loaded nodes from a high voltage swing nodes, delivering high bandwidth while maintaining relatively high gain. A first stage's differential amplifier receives a first set of n input and a second set of n inputs and generates from these first and second intermediate outputs with a high capacitive load and low swing. These intermediate outputs are then the inputs for a second stage's differential amplifier, providing a low capacitive load, high swing output that can then be fed to an inverter for the final output of the voter.

Abstract: A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.

Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.

Abstract: Electronic apparatus and fabrication of the electronic apparatus that includes detection of the majority of values in a plurality of data bits may be used in a variety of applications. Embodiments include application of majority bit detection to process data bits in a device for further analysis in the device based on the results of the majority bit detection. In an embodiment, such further processing in a memory device after majority bit detection may include data bit inversion prior to outputting the data from the memory device.

Abstract: A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.

Abstract: This invention relates to Multiple Interlocked Cells (MICE) design as a hardening technique for CMOS logic gates consisting of two or more redundant nodes with node isolation components. This technique is used to modify existing standard CMOS logic gates or create new complex logic gates using common mask layers existing at ultra-deep sub-micron CMOS foundries. For single node upset immunity in logic or register, a primary cell and a redundant cell are used. For multi-node immunity, the primary cell is combined with two or more redundant nodes are used with physical layout spacing techniques which will insure that a single particle track cannot upset all three nodes simultaneously, and logic circuits built using this technique are immune to upsets in any environment. Circuits built using the MICE technique are also immune to single event transients without requiring the large time delays used in other hardening techniques.

Abstract: This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N?1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths.

Abstract: A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer.

Abstract: A repair circuit having a repair controller which is capable of reducing unnecessary current dissipation by interrupting a control operation to redundant cells that are unused for replacement of defective cells is presented. The repair circuit includes a repair controller and a repair signal generator. The repair controller is configured to generate a first drive voltage, a second drive voltage and a repair control signal depending on whether or not a defective cell exists. The repair signal generator driven by the first and second drive voltages in which the repair signal generator is configured to generate a repair signal, for repairing the defective cell, in response to receiving the repair control signal and an external address.

Abstract: Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components.

Abstract: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.

Abstract: The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.

Abstract: A soft error recoverable storage element suitable for use in latches, flip-flops, static ram memory cells and microprocessor pipeline stages. The storage element employs a redundant copy of the stored data value and a feedback loop. One embodiment employs an interlocking four inverter loop with gating devices that blocks the propagation of a soft error induced change of state and causes the storage element to recover its original stored data state.

Abstract: Self Restoring Logic (SRL) provides for SEU tolerance in high speed circuits. An SRL cell is designed to be stable in one of two internal states. Upon an SEU event, the SRL cell will not transition between the internal stable states and recover from an SEU. SRL circuits are realized with SRL storage cells driving succeeding SRL storage cells directly or through combinational logic such that the corruption of any one internal state variable in the driving SRL cell and it's the associated combinational output logic can affect at most one internal state variable of the succeeding SRL cell. An SRL circuit does not allow propagation of single SEU faults.

Abstract: Provided is a semiconductor device and a method of fabricating the same. The semiconductor device may include at least one logic circuit and at least one spare circuit. The at least one spare circuit may be that is a substitute for the at least one logic circuit and may not be connected to a power voltage source and/or a ground voltage source.

Abstract: Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.

Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.

Abstract: Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter.

Abstract: An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.

Abstract: The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.

Abstract: A system and method for hardening dynamic logic against single event upset is described. A precharge circuit is hardened and then connected to two pull down networks. The two pull down networks are redundant and, under normal operating conditions, provide substantially the same outputs when receiving substantially the same inputs. The two outputs are then voted to provide an output that is hardened against single event upset. Alternatively, the two outputs may be connected to a next stage of dynamic logic circuits or other circuitry for evaluation.

Abstract: A semiconductor integrated circuit, able to repair a fault and normally operate as an overall circuit even when a fault occurs in a portion of the circuit, and able to reduce a change of signal delay along with the repair of the fault, including N (larger than 2) number of circuit modules which can replace each other's functions; circuit blocks each including R (larger than 1 but smaller than N) number of I/O units for outputting at least one signal to one circuit module, and receiving at least one signal generated in the one circuit module; and a circuit module selection unit configured to select R number of circuit modules from among the N number of circuit modules in response to a control signal, connect the selected R number of circuit modules and R number of I/O units of the circuit block in a 1:1 correspondence, and connect one circuit module selected from at least two circuit modules in response to the control signal to each of the R number of I/O units, and a method of producing the same.

Abstract: The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.

Abstract: Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (3P1, 3P2; 3N1, 3N2). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (3I).

Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.

Abstract: A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitry can be a controlled pass-gate circuit and a data latch, an adjustable threshold comparator, or two controlled latches. Transient pulse suppression is achieved with less circuitry and expense than is found in TMR circuits.

Abstract: A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modules connecting the selected R number of modules and R number of I/O parts of the circuit block and connecting one module selected from among at least two modules to each of the R number of I/O parts. Each of the R number of I/O parts has a data holding part for holding a function setting data and inputting the held function setting data to the destination module, and N modules are able to replace functions of each other when the input function setting data are the same.

Abstract: To strengthen tolerance to radiation. Source and back gate of P-channel transistor P1 are connected to power supply. Gate of the P-channel transistor P1 is connected to input terminal IN. Drain of P1 is connected to output terminal OUT. Source and back gate of N-channel transistor N1 are grounded. Gate of N1 is connected to IN. Drain of N1 is connected to OUT. Cathode of diode D1 is connected to power supply, anode of D1 being connected to OUT. Cathode of diode D2 is connected to OUT, anode of D2 being grounded. When seen from a direction perpendicular to a substrate on which an inverter circuit is formed, a projection plane of a region of a p+ diffusion layer 32 of D1 includes a projection plane of a region of an n+ diffusion layer 24 of N1, and a projection plane of a region of an n+ diffusion layer 41 of the diode D2 includes a projection plane of a region of a p+ diffusion layer 14 of P1.

Abstract: A semiconductor system and method for repairing failures of a packaged integrated circuit system are provided. The method includes detecting a failure associated with a packaged integrated circuit system after the packaged integrated circuit system is packaged, and repairing the failure by activating a redundancy circuit in the packaged integrated circuit system and deactivating a defective circuit associated with the failure. The process for repairing the failure includes applying a repair voltage to a polysilicon fuse to change a conductivity state of the polysilicon fuse from a first state to a second state. In another embodiment, the polysilicon fuse is replaced by a metal fuse, an anti-fuse, or a non-volatile random access memory.

Abstract: An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes undershoot-blocking and overshoot-blocking modules that are configured to be coupled to overshoot-insensitive and undershoot-insensitive nodes of the logic circuitry, respectively. The undershoot-blocking module is operable to (i) receive from a first node of the logic circuitry a first signal event having a undershoot condition impressed thereon, and (ii) block it from passing to the overshoot-insensitive node. The overshoot-blocking module is operable to (i) receive from the first node a second signal event having an overshoot condition impressed thereon, and (ii) block it from passing to the undershoot-insensitive node. As such, further propagation of the overshoot and undershoot conditions are prevented.

Abstract: A circuit to adjust power is disclosed. The circuit comprises at least one pass gate and a power adjustor electrically coupled to each pass gate such that the power adjustor consumes power when the gate is enabled. The power adjustor consumes power or not depending upon the state of a polyfuse within the power adjustor.

Abstract: A processor includes an integer unit operable to execute integer instructions and a floating point unit operable to execute floating point instructions. The processor also includes at least one spare fill cell disposed in at least one portion of the processor that is not occupied by the integer unit and the floating point unit. The at least one spare fill cell includes at least one spare transistor configured as a capacitor and coupled to a voltage rail and a ground rail.

Abstract: A first cold spare circuit has first and second transistors, and a second cold spare circuit has third and fourth transistors. The first transistor has a gate controlled by a function of a first chip. A second transistor has its source and drain connected in series with the source and drain of the first transistor between the output and a first potential terminal. A third transistor has a gate controlled by a function of a second chip. A fourth transistor has its source and drain connected in series with the source and drain of the third transistor between the output and a second potential terminal. A first control circuit controls the gate of the second transistor and a second control circuit controls the gate of the fourth transistor so as to turn on one of the second and fourth transistors at a time.

Abstract: A collection of logic gates that provide single event upset (SEU) immunity. The family of gates include an inverter, a two-input NOR gate, a two-input NAND gate, a three-input AND-NOR gate, and a three-input OR-NAND as well as a static RAM bit cell. SEU immunity is obtained by constructing each logic element with a redundant set of inputs and using two copies of each such logic element to provide redundant outputs. The design of a logic element is such that when the redundant inputs agree (i.e., each has the same logic value), then the output of the logic element implements the logic function. However, when any pair of redundant inputs disagree, then the output of the logic element is disconnected(tri-state), which preserves the previous output value. SEU events only affect one of the logic elements in the pair, and this upset can not propagate through other logic elements because of the tri-state function.

Abstract: A collection of logic gates that provide single event upset (SEU) immunity. The family of gates include an inverter, a two-input NOR gate, a two-input NAND gate, a three-input AND-NOR gate, and a three-input OR-NAND as well as a static RAM bit cell. SEU immunity is obtained by constructing each logic element with a redundant set of inputs and using two copies of each such logic element to provide redundant outputs. The design of a logic element is such that when the redundant inputs agree (i.e., each has the same logic value), then the output of the logic element implements the logic function. However, when any pair of redundant inputs disagree, then the output of the logic element is disconnected (tri-state), which preserves the previous output value. SEU events only affect one of the logic elements in the pair, and this upset can not propagate through other logic elements because of the tri-state function.

Abstract: An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and possibly structurally equivalent, and are coupled to receive input signals spanning redundant input signal sets. A given logic structure within the first logic element may receive specified input signals within a particular input signal set, while an analogous logic structure within the second logic element may receive corresponding input signals within the counterpart input signal set. A radiation induced transient pulse that affects one input signal may affect an output signal asserted by one logic structure; however, since the transient pulse doesn't affect a corresponding input signal applied to the analogous logic structure, the dual path logic gate may output at least one correctly valued signal when a transient pulse occurs.

Abstract: A protecting unit is provided. The protecting unit can prevent accidents from occurring that become problems when data are transmitted due to for instance LVDS and for instance laser light is emitted based on the data. The protecting unit is applied in an instrument comprising an input end to which differential signal is transmitted, the input end being attachable to and detachable from an input line. Here, the voltage at the input end when the input line is not connected is set to a voltage different from that generated at the input end when the input line is connected, variation of the voltage at the input end is transmitted to an input terminal of a differential input/output circuit, and the voltage at the input end or a portion corresponding thereto is compared with a prescribed voltage to fix a state of output of the differential input/output circuit to a prescribed state based on the compared results.

Abstract: An apparatus for switching loads, based on a starting signal, having a first MOSFET output stage and a second downstream MOSFET output stage, each of the MOSFET output stages being controllable by a logic circuit, with a power supply voltage of the downstream MOSFET output stage being supplied over the first MOSFET output stage. The apparatus includes a line that is adapted to connect each logic circuit of the MOSFET output stages and to provide an input voltage to a logic circuit of the downstream MOSFET output stage. The apparatus also includes a monitoring arrangement, which is activated by the starting signal, that is adapted to monitor the power supply voltage of the downstream MOSFET output stage and prevent activation of the first MOSFET output stage when the power supply voltage is below a predetermined value.

Abstract: In a fault-tolerant integrated power circuit, a plurality of power transistors, each having a power source electrically coupled to a common source line, a power gate and a power drain electrically coupled to a common drain line, is capable of driving a power current from the source line to the drain line. A first plurality of control transistors, each having a first source, a first gate and a first drain, is disposed so that the first drain of each of the first plurality of control transistors is electrically coupled to a corresponding power gate of a different one of the power transistors. A first transistor control circuit generates a first control signal that is electrically coupled to each first gate of the first plurality of control transistors.

Abstract: CMOS circuits are made resistant to erroneous signals produced by the impact of high energy charged particles (commonly known in the literature as Single Event Upset or SEU) by the addition of upset immune transistor structures into the circuits in such a way that they block and dissipate the erroneous signal. The added transistor structures are made immune to SEU by placing them in well diffusions that are separate from the rest of the circuit and biasing those wells such that the electric fields surrounding the transistors are very low in comparison to the rest of the circuit. Signal blocking is achieved with an SEU immune transistor that is in an “off” state whenever other circuit transistors that deliver signals through it are potentially sensitive to SEU. Dissipation is achieved with either a resistor or low current drive transistor that spreads the SEU signal out over time thereby reducing its voltage change to an acceptable level.

Abstract: A redundant decoder having fuse-controlled transistor comprises as follows: a bistable circuit which outputs a pair of complementary signals; a discharging device which is turned on at an evaluating cycle to form a discharging path; a precharging device which is turned on at a precharging cycle before an evaluating cycle to provide a precharging voltage; a first pair of transistors, having first terminals coupled to the precharging voltage, first gate terminals coupled to receive pair of complementary signals whose logic values decide whether the first pair of transistors are turned on or not, and second terminals; a second pair of transistors, having third terminals coupled to the second terminals of the first pair of transistors, second gate terminals coupled to receive a pair of complementary address bit signals whose logic values decide whether the second pair of transistors are turned on or not, and fourth terminals coupled to the discharging device; and a fuse device, having a fuse which is coupled to t