Abstract: A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.

Abstract: The invention discloses a method for tuning nano-scale analog-circuit designs in order to reduce random-device mismatches and optimize said design, where nano-scale devices potentially have large-scale process variations. The method includes providing a tunable circuit topology, wherein each nano-scale device comprises a single component or comprises multiple parallel components. Each component is decomposed into multiple discrete sub-components, wherein each said sub-component either operates in parallel with other like components to effectively operate like one bigger component. The sub-components are subjected to a dynamic-programming process to adaptively select the sub-components to be kept operational, while configuring the nonselected sub-components to be nonoperational, based on the measurement of at least one operational parameter.

Abstract: A data output circuit includes a plurality of drivers configured to be turned on/off according to impedance codes to output data to an output node. The impedance codes are divided into a first group having a value to turn on the drivers, and a second group having a value to turn off the drivers, and at least some of the drivers controlled by the second group are turned on during a pre-emphasis period.

Abstract: Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit including a controlled-slew rate input circuit, a buffer that is connected to the controlled-slew rate input circuit, and an output driver that is connected to the buffer. The driver circuit is adapted to drive an output signal from the output driver based on an input signal to the controlled-slew rate input circuit. The impedance at the input of the output driver is lower than the impedance at the output of the controlled-slew rate input circuit.

Abstract: In an I/O circuit, noise reduction and power savings are achieved by providing feedback from the output of the I/O driver to control the current through the pre-driver and thereby the current through the driver transistors after a non-zero time delay following a low to high or high to low data signal change.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: An input circuit for receiving an input signal supplied to an input terminal includes a capacitor having one end connected to the input terminal and a capacitor driving circuit for converting the input signal into a signal having positive logic that is the same as logic of the input signal and supplying the converted signal to the other end of the capacitor so as to drive the capacitor.

Abstract: A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal.

Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a signal based on a signal output from the second inverter circuit as a set signal and a reset signal. Each of the first inverter circuit and the second inverter circuit includes a first-conductivity-type transistor and a second-conductivity-type transistor, the capability of one of the first-conductivity-type transistor and the second-conductivity-type transistor being lower than the capability of the other of the first-conductivity-type transistor and the second-conductivity-type transistor.

Abstract: A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.

Abstract: High voltage logic circuits that can handle digital input and output signals having a larger voltage range are described. In an exemplary design, a high voltage logic circuit includes an input stage, a second stage, and an output stage. The input stage receives at least one input signal and provides (i) at least one first intermediate signal having a first voltage range and (ii) at least one second intermediate signal having a second voltage range. The second stage receives and processes the first and second intermediate signals based on a logic function and provides (i) a first drive signal having the first voltage range and (ii) a second drive signal having the second voltage range. The output stage receives the first and second drive signals and provides an output signal having a third voltage range, which may be larger than each of the first and second voltage ranges.

Abstract: An input/output circuit, operable in an input mode and an output mode, for receiving data and an enable signal, the input/output circuit including an input/output terminal; a pull-up output transistor including a gate; a first logic circuit including an output node coupled to the gate of the pull-up output transistor; a pull-down output transistor including a gate; a second logic circuit coupled to the gate of the pull-down output transistor, and the second logic circuit inactivating the pull-down output transistor in the input mode; and a gate signal generation unit configured to generate a gate signal for inactivating the pull-up output transistor in accordance with the enable signal and an input signal provided from an external device to the input/output terminal in the input mode.

Abstract: Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost signal. Additional apparatus, systems, and methods are disclosed.

Abstract: Communications settings are managed. System characteristics are determined that affect communications on a high speed transmission link between nodes. The system characteristics includes system hardware information and physical characteristics of a cable. Tuning information is derived from the system characteristics. At least some of the tuning information is communicated between the nodes.

Abstract: An output buffer provided according to an aspect of the present invention is designed to generate an output signal with a slew rate that is substantially independent of the threshold voltage of transistors contained within. An output buffer provided according to another aspect of the present invention provides output signals with different slew rates depending on the magnitude of the load capacitance at the output node of the output buffer.

Abstract: A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal.

Abstract: Various driver circuit apparatuses and methods for driving an electrical signal are disclosed herein. For example, some embodiments provide a driver circuit including a controlled-slew rate input circuit, a buffer that is connected to the controlled-slew rate input circuit, and an output driver that is connected to the buffer. The driver circuit is adapted to drive an output signal from the output driver based on an input signal to the controlled-slew rate input circuit. The impedance at the input of the output driver is lower than the impedance at the output of the controlled-slew rate input circuit.

Abstract: An on-die termination circuit is capable of increasing a resolution without enlargement of a chip or a layout size. The on-die termination circuit includes a control means, a termination resistance supply means, a code signal generating means. The control means sequentially generates a plurality of control signals in a response to a driving signal. The termination resistance supply means supplies a termination resistance in response to a coarse code signal having a plurality of bits and a fine code signal having a plurality of bits. The code signal generating means controls the fine code signal and the coarse code signal in response to the plurality of the control signals in order that the termination resistance has a level which is correspondent to an input resistance.

Abstract: The present invention provides a precisely controlled terminator circuit of a differential amplifier, in particular, for a differential amplifier of an optical receiver. The differential circuit, which receives a differential signal by a first input for the normal phase signal and a second input for an anti-phase signal, provides a terminator circuit comprises two resistors connected in serial between two inputs and two resistive connections each including a transistor and a resistor serially connected to the transistor and connected between respective inputs and the power supply line Vcc. The control unit, by receiving a medium potential of two resistors, provides a bias to two transistors so as to equalize the medium potential with the reference potential.

Abstract: An input/output circuit operable in input and output modes and including an input/output terminal, pull-up and pull-down output transistors, and first and second logic circuits operated in accordance with data and an enable signal. A control circuit maintains the pull-up output transistor in an inactivated state regardless of the voltage applied to the input/output terminal in the input mode. A switch circuit disconnects the first logic circuit from a power supply when an input signal having voltage higher than the power supply voltage of the power supply is input to the input/output terminal in the input mode. A back gate control circuit supplies back gates of P-channel MOS transistors in the first logic circuit and the switch circuit with back gate voltage having the same voltage as the input signal when the input signal is input in the input mode.

Abstract: A pre-emphasis circuit which can improve a communication quality of a data transmission at low cost is provided. A current switch circuit, a current adder circuit, and transition detection circuits are provided in a transmitter of a data transmission system. The transition detection circuits detect transitions of transmission data signals which are a differential pair. The current switch circuit receives the transmission data signals, carries driving currents in accordance with the transmission data signals, and outputs output data signals which are a differential pair. The current adder circuit receives detection signals from the transition detection circuits, and adds driving currents in accordance with the detection signals to load resistors. By this means, output data signals in which the transitions are emphasized are inputted to a transmission line.

Abstract: A semiconductor chip comprising a reference circuit and a target circuit. The reference circuit comprises a first P-channel field effect transistor (PFET) and a first N-channel field effect transistor (NFET). A reference voltage is connected to gates of the first PFET and first NFET. A body control voltage node is formed by connecting a drain of the first PFET, a body of the first PFET, a drain of the first NFET and a body of the first NFET. A target circuit comprises a second PFET and a second NFET. The body control voltage node is connected to a body of the second PFET and the second NFET. The body control voltage improves duty cycle in the target circuit compared to a similarly designed circuit having PFET bodies connected to Vdd and NFET bodies connected to Ground.

Abstract: A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate control signal generating unit configured to generate slew rate control signals by using a code signal, and a plurality of drivers configured to output data by driving the data at a slew rate set according to the slew rate control signals.

Abstract: A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, sequentially activates the data and a first pull-up delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-up delayed signals having different delay times in the second mode of operation. A pull-up driving unit sequentially pulls a data output terminal up in response to the data and the first to third pull-up delayed signals.

Abstract: Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

Abstract: An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transistors have a common conduction terminal connected to an output terminal of the output buffer. An input terminal of the buffer is connected to control terminals of the transistors of the first stage through a first open loop driving circuit. A second feedback driving circuit is connected between the input terminal and the control terminals of the transistors of the second stage. The second feedback driving circuit includes a current detector operating to detect a maximum in the value of the current drawn by and supplied to the output buffer. A comparison block, having a threshold value, detects current in excess of the threshold value and processes information coming from the current detector to regulate an output impedance value of the output buffer.

Abstract: The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture.

Abstract: According to one exemplary embodiment, a termination circuit includes a number of drivers configured to receive source data on an input bus and to drive an output bus including a number of output lines. In the termination circuit the output lines are terminated by resistors, where one resistor is coupled between each output line and a common capacitor node. The termination circuit further includes a virtual regulator at the drivers, configured to control a termination voltage at the capacitor node by inputting compensation data into the drivers during idle cycles to achieve a net average 50% duty cycle. The virtual regulator can determine which cycles are idle by detecting an idle code in the source data.

Abstract: A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage.

Abstract: An integrated circuit device includes an output buffer having a capacitance circuit configurable in a slew rate configuration or a decoupling configuration. In the slew rate configuration, the capacitance circuit electrically couples a capacitor of the capacitance circuit in a feedback path for reducing a slew rate of a buffered output signal generated by the output buffer. In the decoupling configuration, the capacitance circuit electrically couples the capacitor between a power potential and a ground potential of the output buffer for increasing power noise immunity of the output buffer. The output buffer may have more than capacitance circuit, each of which is individually configurable into the slew rate configuration or the decoupling configuration.

Abstract: A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.

Abstract: In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

Abstract: The present invention provides a differential signaling system comprising: a driver circuit that transmits a differential signal; a receiver circuit that receives the differential signal; and two or more signal lines used for the differential signal to be transmitted by the driver circuit and received by the receiver circuit, wherein the driver circuit gives an arbitrary time lag between the two signals that form the differential signal before transmitting them.

Abstract: Methods and apparatus are provided for compensating for skew in a differential signal using non-complementary inverters. A skew attenuator is provided for a differential signal having a P rail and an N rail. The skew attenuator comprises one or more non-complementary inverters for compensating for skew between the P rail and the N rail. The non-complementary inverters attenuate a time difference of arrival of transitions for the P rail and the N rail. An exemplary skew attenuator includes a first non-complementary inverter associated with each of the P rail and the N rail. The P rail and the N rail signals are each applied to a gate of one of the first non-complementary inverters, and drains of the first non-complementary inverters provide differential output signals OUTP and OUTN. The exemplary skew attenuator also includes an additional non-complementary inverter associated with each of the first non-complementary inverters.

Abstract: An electronic device comprising at least one input/output circuit (10) in a first supply voltage domain (VDD, GND) is provided. The electronic device furthermore comprises a buffer (INV) which is coupled to the input/output circuit for driving an input of the input/output circuit (10). The buffer comprises a first and second switch (T1, T2; T4, T5). The buffer is arranged in a second supply voltage domain (VDD1, GND1). Furthermore, a control circuit is coupled to the buffer for controlling the first and second switch (T1, T2; T4, T5) such that during a transition of an input signal of the input/output circuit (10) both switches (T1, T2; T4, T5) are temporarily kept in a conducting state and a crowbar current flows through the buffer (INV).

Abstract: A semiconductor device includes: a driver that receives a power supply voltage and drives an external load with a driving capability; a measurement unit that measures a level of the power supply voltage; a code table that stores the level of the power supply voltage and code information for determining the driving capability of the driver; and a controller that reads the code information in accordance with the level of a measured power supply voltage in reference to the code table and controls the driving capability of the driver in accordance with the code information.

Abstract: A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supplement the current from buffer output, thereby facilitating transition of a signal at the load. The current boost module can shut down the boost current before the signal at the load completes its transition from one logic state to the other.

Abstract: An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop coupled to said output signal line for changing state of said output stage subsequent to a delay after a transition of said output signal. The delay is due to transmission line effects of said output signal line.

Abstract: A current limited voltage supply including a transistor and a capacitor is provided for powering digital logic cells of an integrated circuit. The transistor is connected in a current mirror configuration, such that a constant reference current is mirrored through the transistor to create a first supply current. The transistor is coupled to the digital logic cells and the capacitor. The first supply current is used to charge the capacitor while the digital logic cells are not switching. While the digital logic cells are switching, the capacitor discharges to the digital logic cells, thereby providing the digital logic cells with sufficient energy to implement high-speed switching. The capacitor minimizes voltage fluctuations within in the current limited voltage supply, such that analog circuitry can be reliably powered from a different branch of the same current mirror circuit.

Abstract: An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals.

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract: A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal and the auxiliary driver.

Abstract: A leakage efficient anti-glitch filter. In accordance with a first embodiment of the present invention, a leakage efficient anti-glitch filter with variable delay stages comprises a plurality of variable delay stages and a coincidence detector element for detecting coincidence of an input signal to the delay element and an output of the delay element. The plurality of variable delay stages may comprise stacked inverter circuits or stacked NAND circuits.

Abstract: A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.

Abstract: In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.

Abstract: Processor-based systems, memories, signal driver circuits, and methods of generating an output signal are disclosed. One such signal driver circuit includes a signal driver configured to generate an output signal at an output node in response to an input signal and a transistor coupled to the signal driver that is configured to couple and decouple the output node and the voltage supply according to a control signal. A voltage comparator circuit coupled to the output node and the transistor is configured to generate the control signal to control coupling and decoupling of the output node and the voltage supply through the transistor based on a voltage of the output signal relative to the reference voltage.

Abstract: A design structure for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.