Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

Abstract: A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode.

Abstract: In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

Abstract: Switching and repeating applications using an impedance matched source follower improve performance of high speed links such as PCI Express, HDMI, DisplayPort and DVI by reducing attenuation and other degradation of high speed signals, including those with transmit pre-emphasis, by avoiding impedance discontinuities over process, voltage and temperature variations and by driving a broader range of loads, e.g., heavily capacitive loads. A circuit for switching or repeating signals on a single-ended or differential high speed link may comprise a source follower with input and output impedances matched to input and output transmission lines on the high speed link. The source follower is biased by a constant transconductance circuit, an external calibration circuit or other circuit to provide an essentially constant output impedance over process, voltage and temperature variations.

Abstract: Method and apparatus are disclosed for implementing low noise circuits. The method includes providing a first subcircuit and a second subcircuit, where the first subcircuit and the second subcircuit include substantially same circuit elements and have substantially same configuration and layout, providing one or more coupling capacitors configured to couple between a circuit power and a circuit ground that power the first subcircuit and the second subcircuit, providing one or more pairs of differential input signals to the first subcircuit and the second subcircuit, where the first subcircuit receives a differential signal and the second subcircuit receives a complement of the differential signal, operating the first subcircuit and the second subcircuit to generate one or more pairs of differential output signals using the one or more pairs of differential input signals.

Abstract: An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device feedback control controls the output stage gate drive.

Abstract: A semiconductor device includes a pre-buffer for transferring a data signal on the basis of a first power supply voltage, a main buffer for amplifying and outputting the data signal transferred by the pre-buffer on the basis of a second power supply voltage different from the first power supply voltage, a switch unit for controlling a conductive state between the pre-buffer and the main buffer on the basis of a switch control signal, and a control circuit for generating the switch control signal for controlling the pre-buffer to set an output level of the pre-buffer to ground potential in accordance with transition of logical level of the switch control signal.

Abstract: An output circuit including an input terminal; an output terminal; a PMOS transistor connected with a positive side of a power voltage and the output terminal; a NMOS transistor connected with a negative side of the power supply voltage and the output terminal; a first inverter, to which a gate voltage of the PMOS transistor is input and which exhibits hysteresis in threshold voltage; and a second inverter, to which a gate voltage of the NMOS transistor is input and which exhibits hysteresis in threshold voltage, wherein an OR logic signal of the input signal and a signal obtained by inverting an output signal from the second inverter is input to a gate of the PMOS transistor, and an AND logic signal of the input signal and a signal obtained by inverting an output signal from the first inverter is input to a gate of the NMOS transistor.

Abstract: An electronic device with a CMOS circuit (CC) comprises a first driver circuit (10) having a first and second PMOS transistor (P1, P2) and a first and second NMOS transistor (N1, N2). The electronic device furthermore comprise a second driver circuit (20) with a third and fourth PMOS transistor (P3, P4) and a third and fourth NMOS transistor (N3, N4). The second driver circuit (20) is complementary to the first driver circuit (10) and switches in the opposite direction to the first driver circuit (10). A gate of the second and fourth PMOS transistor (P2, P4) is coupled to a first bias voltage (REPp) and a gate of the second and fourth NMOS transistor (N2, N4) is coupled to a second bias voltage (REFn). A first capacitance (C3) is coupled between the gate and the drain of the fourth PMOS transistor (P4) and a second capacitance (C4) is coupled between the gate and the drain source of the fourth NMOS transistor (N4).

Abstract: A transmission device including: a driver unit which generates an output signal having an amplitude by a resistance division of a power-supply voltage; and an output-amplitude correction unit which generates current according to variation in the power-supply voltage, and corrects the amplitude by using the current.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and then turn off. The first transistor drives the output to a high state to assist in the rising transition. The circuit also includes a second subcircuit that causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and then turn off. The second transistor drives the output to a low state to assist in the falling transition.

Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: Circuit with enhanced mode and normal mode is provided and described. In one embodiment, switches are set to a first switch position to operate the circuit in the enhanced mode. In another embodiment, switches are set to a second switch position to operate the circuit in the normal mode.

Abstract: A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node.

Abstract: An output circuit allows the slew rate of its output signal to be selectively adjusted. The output driver circuit includes an output driver and pre-driver circuits. The output driver includes an output transistor coupled between a first supply voltage and the output terminal. The pre-driver circuit selectively adjusts a series resistance between the output transistor's gate and a second supply voltage in response to mode control signals.

Abstract: A semiconductor device includes a current-driven differential driver and a control circuit. The current-driven differential driver is configured to generate a pair of signals having levels relative to each other from a serial signal input therein and output a current from a current source included therein through an output node according to each of the signals. The control circuit controls the current-driven differential driver to pass the current from the current source as a throwaway current therein during a second predetermined time after an input of the serial signal stops and to block the throwaway current after the second predetermined time passes.

Abstract: Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal.

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract: An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor; a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit; and a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit.

Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor selectively discharges the output node toward a second reference voltage when the output node is to transition from the first state to a second state, the second state a logical complement of the first state. An output of a source-follower circuit, having a current source, is coupled to the output node. A third MOS transistor selectively couples the current source of the source-follower circuit to the second reference voltage when the output node is to be in the second state.

Abstract: In one embodiment, an output driver buffer circuit for a logic device includes an output driver transistor adapted to adjust an output voltage of an output pad; a capacitor adapted to be connected to the transistor gate and further adapted when charged and connected to the gate to turn the transistor on; and a reference voltage source adapted to be connected to the transistor gate and further adapted when connected to the gate to maintain the transistor on. The reference voltage source is further adapted to be connected to the transistor gate after the capacitor has turned the transistor on and independent of the level of the output voltage of the output pad.

Abstract: A signal driver having a selectable aggregate slew rate, a method of driving a signal driver and a signal driver incorporating the driver or the method. The driver includes plural partial drivers configured to output signals based on time constants established by corresponding plural time-delay networks associated therewith. The signal driver further includes a slew rate selector coupled to the plural time-delay networks and configured to provide a common signal thereto to cause the plural time-delay networks to achieve target time constants, the target time constants causing the output signals to be generated such that the signal driver achieves the selectable aggregate slew rate.

Abstract: A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second subcircuit causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and drive the output to a low state to assist in the falling transition. A third subcircuit resets elements of the first subcircuit. The first subcircuit operates above a first voltage threshold and the third subcircuit operates below the first voltage threshold. A fourth subcircuit resets elements of the second subcircuit. The second subcircuit operates below a second voltage threshold and the fourth subcircuit operates above the second voltage threshold.

Abstract: An interface circuit includes a driver circuit (12) made up of a combination of a plurality of transistors, a calibration circuit (14) for performing selection of on and off of one or more of the plurality of transistors for adjusting on-resistance thereof, and a terminating resistor (13) that is connected to an output side of the driver circuit (12). One or more of the transistors are turned on based on an output of the calibration circuit (14), so that a combination resistance value of the on-resistance and the terminating resistor matches characteristic impedance of the transmission line. The driver circuit (12), the calibration circuit (14) and the terminating resistor (13) are formed on the same semiconductor integrated circuit SK, and the calibration circuit (14) detects process variation and temperature variation of the transistor and the resistor formed on the semiconductor integrated circuit (SK).

Abstract: Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal.

Abstract: Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability, is provided and described. In one embodiment, switches are set to a first switch position to operate the repeater circuit in the high performance repeater mode. In another embodiment, switches are set to a second switch position to operate the repeater circuit in the normal repeater mode.

Abstract: A self-adaptive output buffer for an output terminal of an electronic circuit suitable to be connected to a load is proposed. The self-adaptive output buffer includes means for sensing an indication of the capacitance of the load and means for driving the load according to the sensing, wherein the means for sensing includes capacitive means with a preset capacitance, means for charging the capacitive means to a preset voltage, means for coupling the charged capacitive means with the load, and means for measuring a measuring voltage at the capacitive means due to a charge sharing between the capacitive means and the load.

Abstract: A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.

Abstract: An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

Abstract: A data output driver device includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal.

Abstract: A data input/output driver for use in a semiconductor memory device includes a data transmitting block for transmitting a data between an inside and an outside of the semiconductor memory device and generating a data driving signal in order to indicate a timing of outputting the data. A reference data generating block generates a reference data. A switching block outputs the reference data in response to the data driving signal. The data and the reference data are combined as an output signal.

Abstract: A semiconductor memory device is able to inactivate an on-die termination circuit without an additional pin. The semiconductor memory device includes a control signal generator, a resistance control unit, and a resistance supply unit. The control signal generator generates an initializing signal and driving clocks in response to a plurality of control signals. The resistance control unit, initialized by the initializing signal, generates a termination-off signal in response to the driving clocks. The resistance supply unit supplies termination resistance in response to the termination-off signal and a mode register setting value. The plurality of control signals are inputted through input pins not connected to the resistance supply unit.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: Systems and methods for current management for digital logic devices are provided. In one embodiment, a method of current management for a digital logic circuit comprises drawing power to drive a digital logic integrated circuit; determining a priori information about an impending current need of the digital logic integrated circuit; and controlling a bypass current in parallel with the digital logic integrated circuit based on the a priori information, wherein the bypass current is controlled to reduce discontinuities in the current supplied by a power supply.

Abstract: A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate control signal generating unit configured to generate slew rate control signals by using a code signal, and a plurality of drivers configured to output data by driving the data at a slew rate set according to the slew rate control signals.

Abstract: An output driver controls impedance using a mode register set. The output driver includes a main driving circuit that outputs and drives a main signal based on a data signal to a predetermined transmission line, an auxiliary driving circuit that outputs and drives an auxiliary signal to the transmission line, and a mode register set. The mode register set generates an impedance control signal group, a driving width control signal group and a delay control signal group. The amount of an auxiliary impedance (SIM), and the driving width and driving time point of an auxiliary signal (XSDR) can be controlled using the impedance control signal group, the driving width control signal group and the delay control signal group. Therefore, in accordance with the output driver of the present invention, the amount of output impedance (OIM), a pre-emphasis width and a pre-emphasis time point can be readily controlled, and the efficiency of the transmission of an output signal to a reception system is improved.

Abstract: A semiconductor device including an AND-NOR composite gate of which AND unit is supplied with input signals IN and VDD and NOR unit is supplied with an inverted signal EB of an enable signal E, and an AND-NOR composite gate of which AND unit is supplied with an input signal INB and an enable signal E and NOR unit is supplied with VSS. These gates are inserted into a path to which the input signals IN and INB are supplied. Thereby, a symmetric property of a complimentary signal can be retained. Further, outputs of the AND-NOR composite gates are fixed irrespective of a logical level of the enable signal E. Thus, a sub-threshold current also is inhibited.

Abstract: Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis for a period of time. The output drive may include a first transistor and a second transistor coupled to an output of the off-chip driver to provide additional initial drive emphasis strength when both transistors are energized for an initial period of time. The time period may be set by an inverted delay circuit.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.

Abstract: A drive circuit for driving a power device has a level shift circuit which level-shifts an ON signal and an OFF signal for controlling the power device in ON and OFF states, respectively, and which outputs the level-shifted ON and OFF signals, a mask circuit which stops transmission of the ON and OFF signals when both the ON and OFF signals are lower than a first threshold level, and a short circuit which is provided in a stage before the mask circuit, and which short-circuits a path for transmission of the ON signal and a path for transmission of the OFF signal when both the ON and OFF signals are lower than a second threshold level. The second threshold level is higher than the first threshold level.

Abstract: An IO driver utilizes a slew rate boost circuit coupled to an IO driver circuit to improve the slew rate of the driver during transitions on the output of the driver. One or more additional output stages are coupled in parallel with a primary output stage of the driver, and are temporarily activated responsive to a transition in an input signal to the driver to effectively decrease the output impedance and boost the pull-up and pull-down time response characteristics of the driver during the transition of the output. The additional output stages are active only for a small part of a cycle, so the slew rate is thereby increased while the effective output impedance during most of the cycle is essentially unaffected.

Abstract: When the operation frequency is high, in order to cause the rate of change of outputs from an output terminal (OUT) to be abrupt, a selection control signal is caused to be in a low state, thereby causing MOS transistors (T5b, T6b) to be in ON states, thereby causing the combined resistance of the ON-resistances of the MOS resistors in a NOR gate (NOx) to be small. On the other hand, when the operation frequency is low, in order to cause the rate of change of outputs from the output terminal (OUT) to be gentle, the selection control signal is caused to be in a high state, thereby causing the MOS transistors (T5b, T6b) to be in OFF states, thereby causing the combined resistance of the ON-resistances of the MOS transistors in the NOR gate (NOx) to be large.

Abstract: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry regulates the body bias voltage on the body bias path using a p-channel control transistor. An isolation transistor is coupled between the p-channel control transistor and the body bias path. During potential latch-up conditions, the isolation transistor is turned off to isolate the body bias path from ground. Control circuitry adjusts a body bias voltage that is applied to body terminals in the p-channel control transistor and isolation transistor.

Abstract: A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.

Abstract: A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.

Abstract: A technique for terminating a differential signal line substantially matches the output impedances of a first node and a second node of a differential node. The power dissipation is substantially less than twice the power delivered to a load impedance coupled to the differential signal line. The technique provides a peak-to-peak, single-ended output voltage on the differential output node that is substantially independent of integrated circuit manufacturing process tolerances. An apparatus includes a differential node coupled to provide a differential signal. The differential node includes a first node and a second node. A first single-ended termination circuit is coupled to the first node and responsive to a first reference voltage. The apparatus includes a second single-ended termination circuit coupled to the second node and responsive to a second reference voltage.

Abstract: In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs.

Abstract: An on-die termination circuit is capable of increasing a resolution without enlargement of a chip or a layout size. The on-die termination circuit includes a control means, a termination resistance supply means, a code signal generating means. The control means sequentially generates a plurality of control signals in a response to a driving signal. The termination resistance supply means supplies a termination resistance in response to a coarse code signal having a plurality of bits and a fine code signal having a plurality of bits. The code signal generating means controls the fine code signal and the coarse code signal in response to the plurality of the control signals in order that the termination resistance has a level which is correspondent to an input resistance.

Abstract: A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.