Abstract: A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.

Abstract: A semiconductor device includes: a GaAs chip; and a resin sealing the GaAs chip. The GaAs chip includes: a p-type GaAs layer; an n-type GaAs layer on the p-type GaAs layer; a metal electrode located on the n-type GaAs layer along an edge of the GaAs chip and to which a positive voltage is applied; a device region located in a central portion of the GaAs chip; a semi-insulating region located between the metal electrode and the device region and extending in the p-type GaAs layer and the n-type GaAs layer; and a connecting portion disposed outside the semi-insulating region and electrically connecting the p-type GaAs layer to the metal electrode.

Abstract: A packaged PLD solution includes a first die having a masked-Read Only Memory (ROM) that is programmed during its fabrication to store configuration data, and includes a second die having a PLD including a number of configurable resources collectively configured to implement a circuit design embodied by the configuration data. The first die is electrically connected to the second die, and both the first die and second die are stacked and encapsulated together to form the packaged PLD solution. The configuration data is programmed into the masked-ROM by a manufacturer of both the masked-ROM and the PLD.

Abstract: A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal (100), a plurality of circuit elements (322, 326, 330), and a plurality of transistors (320, 324, 328). Each transistor has a control terminal (314, 316, 318) and a current path coupled between the output terminal and a respective circuit element of the plurality of circuit elements. A control circuit (300) has a plurality of output terminals (314, 316, 318). Each output terminal is coupled to the control terminal of a respective transistor of the plurality of transistors. The control circuit produces control signals at respective output terminals to selectively turn off at least one transistor and turn on at least other transistors of the plurality of transistors at a first time.

Abstract: A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O circuits and the I/O circuits within the remaining blocks. Each I/O circuit associates with a pin such that each block has a set of pins. A SERDES and a FIFO buffer associate with each block. Each block's SERDES couples between the block's I/O circuits and the block's set of pins. Each FIFO buffer couples between the SERDES and its block's I/O circuits.

Abstract: An output driver of a semiconductor integrated circuit having low power consumption and reduced layout area transmits internally generated data of the circuit to pads responsive to clock signals, and is controlled by control signals indicative of changes of process, voltage, and temperature. The output driver includes a data selector, an output driver enabler, a first driver that transmits an output of the output driver enabler to the pads, and a second driver that includes a data delay having a plurality of inverters connected in series to an output of the output driver enabler and being activated responsive to the control signals. The second driver transmits an output of the data delay to the pads. The output driver reduces a load on the clock signal line, so that power consumption and a layout area can be reduced.

Abstract: The present invention is a technique for dynamic element matching used in digital-to-analog converters (DAC's). An analog-to-digital converter (ADC) converts an analog signal into a digital code. A current-mode randomizer randomizes the digital code based on a control word provided by a pseudo random number generator. A digital-to-analog converter (DAC) converts the randomized digital code into an analog signal.

Abstract: A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.

Abstract: A method and an apparatus provided to calculate and control the elongation in a running web (16), e.g. in connection with a preparation of a web in a printing machine. In connection with at least an increase or decrease in the web tension, the length change in a reference length of the web material is measured, and by means of web tension meters the web tension before and after the web tension change (.sigma..sub.1 -.sigma..sub.2) or each one of the web tension alterations is determined. The tension-free length (n.sub.o) of the reference length is also calculated and if it is needed, the elongation of the web is corrected through an increase or a decrease in the web tension depending on said measurements.

Abstract: An electronic circuit comprises a programmable cell that comprises a cell input, an output, a programmable component, programming means for selectively changing a state of the component, and coupling means for providing a signal path from the cell input to the output dependent on the component's state. The programmable component, e.g., a fuse, is located outside the signal path. Capacitances that limit the speed of operation in the read mode are considerably lower than in the prior art.