Abstract: An electronic device includes a die stack having a plurality of die. The die stack includes a die parity path spanning the plurality of die and configured to alternatingly identify each die as a first type or a second type. The die stack further includes an inter-die signal path spanning the plurality of die and configured to propagate an inter-die signal through the plurality of die, wherein the inter-die signal path is configured to invert a logic state of the inter-die signal between each die. Each die of the plurality of die includes signal formatting logic configured to selectively invert a logic state of the inter-die signal before providing it to other circuitry of the die responsive to whether the die is designated as the first type or the second type.

Abstract: There are several approaches to encrypting circuits: combination logic encryption, encrypted gate topologies, transmission gate topologies, and key expansion of gate topologies. One of the approaches provides a circuit having a gate topology comprising a logic gate with integrated key transistors, where the key transistors comprise at least a PMOS stack and an NMOS stack. The PMOS stack comprises a first PMOS switch and a second PMOS switch, where the first and the second PMOS switches have sources to a voltage source and drains that serve as a source to a third PMOS switch. The NMOS stack comprises a first NMOS switch and a second NMOS switch, where the first and the second NMOS switches have sources to ground and drains that serve as a source to a third NMOS switch. Each of the above approaches may encrypt a circuit with certain advantages in delay and power consumption.

Abstract: A device is disclosed for testing a memory, in which the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response in responses of the first memory circuit, and the first memory circuit is configured to store a second response of responses of the second memory circuit. The device includes a comparing circuit and a maximum hamming distance generating circuit. The comparing circuit is configured to compare the first response with the responses of the first memory circuit, and configured to compare the second response with the responses of the second memory circuit, to generate comparing results. The maximum hamming distance generating circuit is configured to generate a maximum hamming distance according to the comparing results.

Abstract: An inversion signal generation circuit may include a transition detection signal generation circuit suitable for generating first to fourth transition detection signals, a first XOR gate suitable for receiving a fourth inversion signal and the first transition detection signal, and generating a first pre-inversion signal, a second XOR gate suitable for receiving the first pre-inversion signal and the second transition detection signal, and generating a second pre-inversion signal, a third XOR gate suitable for receiving the second transition detection signal and the third transition detection signal, a fourth XOR gate suitable for receiving the first pre-inversion signal and an output signal of the third XOR gate, and generating a third pre-inversion signal, a fifth XOR gate suitable for receiving the third pre-inversion signal and the fourth transition detection signal, and generating a fourth pre-inversion signal, and a first alignment circuit suitable for generating first to fourth inversion signals.

Abstract: Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.

Abstract: A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

Abstract: A semiconductor memory apparatus may include a data control circuit, an input/output circuit block, and a data line repeater block. The data control circuit may generate a data control flag signal based on an operation control signal and data. The input/output circuit block may perform a data bus inversion operation for the data, based on the data control flag signal. The data line repeater block may perform a data masking operation for the data based on the data control flag signal.

Abstract: A device is disclosed for testing a memory, and the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response of the first memory circuit. The device includes a comparing circuit and a calculating circuit. The comparing circuit is configured to compare the first response stored in the second memory circuit with a plurality of responses of the first memory circuit operated in conditions that are different from each other, to generate a plurality of first comparing results. The calculating circuit is configured to output, according to the plurality of first comparing results, a maximum hamming distance between two of the first responses and the plurality of responses of the first memory circuit.

Abstract: A device is disclosed that includes a memory array, a comparing circuit, and a calculating circuit. The memory array is configured to store a first response of an under-test device. The comparing circuit is configured to compare the first response with a plurality of responses of the under-test device operated in conditions that are different from each other to generate comparing results. The calculating circuit is configured to output a maximum hamming distance between two of the first response and the plurality of responses according to the comparing results.

Abstract: A phase actuator for a continuously adjustable phase displacement at a first frequency is provided. The phase actuator has a first inductance with tapping point, a first continuously variable capacitor, and a transformation network. A signal input and a signal output of the phase shifter are connected by the first inductance. The first continuously adjustable capacitor is connected in parallel to the first inductance. The tapping point is connected via a transformation network to a reference mass, where an impedance value of the transformation network corresponds to a quarter wave transform of a capacitance value of the first continuously variable capacitance at the first frequency.

Abstract: A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Abstract: A semiconductor device includes a semiconductor chip, a lead frame and one bonding wire and the other bonding wire which couple together the semiconductor chip and the lead frame. The semiconductor chip includes one pad which is coupled to one bonding wire and to which an output signal which has been generated in the semiconductor chip is supplied, the other pad which is coupled to the other bonding wire and to which a feedback signal is supplied from the lead frame and a fault detection circuit which compares the output signal which is supplied to one pad with the feedback signal which is supplied to the other pad.

Abstract: A semiconductor device of one embodiment includes semiconductor chips. While the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.

Abstract: A semiconductor device includes: an inversion circuit suitable for inverting a first data clock in response to an inversion signal; a first phase detection unit suitable for comparing a phase of the first data clock transferred from the inversion circuit with a phase of a system clock and generating a first detection result; a second phase detection unit suitable for comparing a phase of a second data clock with the phase of the system clock and generating a second detection result; an inversion signal generation unit suitable for generating the inversion signal that is enabled when the first detection result and the second detection result are different from each other; a first transferring unit suitable for transferring the first detection result; and a second transferring unit suitable for transferring the second detection result.

Abstract: A latch circuit providing isolated input current paths includes a pair of input transistors that receive a differential input signal. A plurality of steering transistors receive a portion of a differential clock signal. The latch circuit includes a positive output node and a negative output node. A first bypass input current path is associated with the first input transistor and is electrically isolated from the positive output node and the negative output node. A second bypass input current path associated with the second input transistor is also electrically isolated from the positive output node and the negative output node. In a latched state, the clock signal is operative to selectively bias the plurality of steering transistors such that current is steered to one of the first input current path or the second input current path, thereby being isolated from the output nodes.

Abstract: A Cooperative Multi-point transmitting and receiving apparatuses using base station modulation method in a wireless system are provided.

Abstract: A semiconductor device may include a data output circuit and control signal output circuit. The data output circuit may convert a first input signal and a second input signal sequentially inputted thereto into output data and may compare the first and second input signals with a storage datum to generate a first comparison signal and a second comparison signal. The control signal output circuit may detect logic levels of bits included in the first and second comparison signals to generate a first detection signal and a second detection signal, may generate a first flag signal and a second flag signal from the first and second detection signals in response to a storage flag signal, and may sequentially output the first and second flag signals as transmission control signals.

Abstract: A method for processing a bitstream starts by shifting a bitstream of a first sample of a signal into a buffer. The buffer also holds bits of one or more additional bitstreams for one or more additional samples of the signal. Bits of a first half of the buffer are incrementally compared to corresponding bits of a second half of the buffer. Each bit of the first half of the buffer is compared to a corresponding bit of the second half of the buffer. A computation is performed on each bit of the first half of the buffer that is equal to a corresponding bit of the second half of the buffer. The results of the computations are summed to determine an output value for the first sample of the signal.

Abstract: A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.

Abstract: A computer determines a threshold signal voltage of a semiconductor device. The computer determines a first expected signal propagation time for a signal travelling through a first test path of the semiconductor device. The computer transmits a first signal through the first test path. The computer measures a signal voltage and signal propagation time of the first signal. The computer determines that the signal voltage of the first signal does not reach or exceed the threshold signal voltage within the first expected signal propagation time. The computer determines that the first test path contains a defect.

Abstract: A phase detector, arranged for comparing a phase of a first clock with a phase of a second clock. The phase detector includes a phase detection stage and a metastable prevention stage. The phase detection stage is arranged to receive the first clock and the second clock, and to output a phase comparison result in accordance with the phase of the first clock and the phase of the second clock. The metastable prevention stage is arranged to receive the phase comparison result, and to output a stable phase comparison result in accordance with the phase comparison result.

Abstract: According to an example embodiment of inventive concepts, an operating method of a non-volatile memory device includes: performing a first hard decision read operation that includes applying a first voltage if a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch.

Abstract: A fractional frequency divider circuit includes: a frequency divider circuit configured to frequency-divide an input clock at 1/CTSquo, wherein the CTSquo is a quotient of CTS/N; a clock addition circuit configured to add one clock to an output of the frequency divider circuit; a counter that counts the number of cycles of the output of the frequency divider circuit by a carry of the frequency divider circuit or an output of the clock addition circuit; a match detection circuit that determines whether an integer multiple of N/CTSrem matches a value of the counter, wherein the CTSrem is a remainder of CTS/N; and a selector circuit that outputs the output of the clock addition circuit as an output clock when the match is detected by the match detection circuit, and outputs the output of the frequency divider circuit as an output clock when the match is not detected.

Abstract: Certain aspects of the present disclosure support a technique for utilizing a memory in probabilistic manner to store information about weights of synapses of a neural network.

Abstract: A non-volatile logic operation device includes an operation unit that is connected to a first input terminal, a second input terminal, and an output terminal, includes an operation layer, a first non-magnetic layer, and a reference layer, and outputs from the output terminal a result of a logic operation on signals applied at the first input terminal and the second input terminal, and a control unit that is connected to a third input terminal, and includes a control layer. The control unit is arranged in the vicinity of the operation unit.

Abstract: A semiconductor device includes a first pad and a second pad. A first conductivity type transistor is coupled between a first potential and the second pad, and a second conductivity type transistor is coupled between a second potential and the second pad. A comparator includes a first input node coupled to the first pad and a second input node coupled to the second pad. A circuit receives a signal from the first pad or outputs a signal to the first pad, wherein the first pad is coupled to gate electrodes of the first and second conductivity type transistors.

Abstract: A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction

Abstract: A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator is configured to oscillate if the first and the second inputs are high, and wherein the connection between the second oscillator and the first oscillator is configured to suppress oscillation of the first oscillator if the second oscillator is oscillating.

Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.

Abstract: A control circuit of a light-emitting element comprises a rectifying unit which full-wave rectifies an alternating current power supply, a clock generator which generates and outputs a clock signal (CLK), a first comparator which compares a comparison voltage (CS) corresponding to a current flowing to the light-emitting element and a reference voltage (REF), and a switching element which is set to an ON state in synchronization with the clock signal (CLK) and which is set to an OFF state when the comparison voltage (CS) becomes greater than the reference voltage (REF) at the first comparator, to switch the current flowing to the light-emitting element. In this structure, a period of the clock signal (CLK) generated in the clock generator is varied, to reduce or inhibit noise.

Abstract: Disclosed herein is a logic circuit that includes a transistor T1 coupled between VPERI and a node n1, a transistor T2 coupled between VPERI and a node n2, a transistor T3 coupled between VSS and a node n3, a transistor T4 coupled between VSS and a node n4, transistors T5 and T7 coupled in series between the nodes n1 and n3, transistors T9 and T11 coupled in series between the nodes n1 and n3, transistors T6 and T8 coupled in series between the nodes n2 and n4, and transistors T10 and T12 coupled in series between the nodes n2 and n4. An output signal Y is output from a connection point of the transistors T5 and T7 and a connection point of the transistors T6 and T8.

Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.

Abstract: Systems and methods for preventing saturation of analog integrator outputs are provided. Applications of the systems and methods in hybrid analog-digital integrators are also provided. Exemplary systems include two switches, one operational amplifier, one capacitor C, four gain blocks, three comparators, one XOR gate, one OR gate, one T flip-flop, and one digital counter.

Abstract: A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction

Abstract: Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.

Abstract: An input buffer system with a dual-input buffer switching function includes a first input buffer, a second input buffer, and a multiplexer. The first input buffer is used for outputting a first signal when an input signal is at a logic-high voltage, and the first input buffer is turned off when the input signal is at a logic-low voltage. The second input buffer is used for outputting a second signal when the input signal is at the logic-low voltage. The multiplexer is coupled to the first input buffer and the second input buffer for outputting the first signal or the second signal according to a self refresh signal.

Abstract: One embodiment provides a system for generating a reference waveform. The system can include a first pulse-width modulation (PWM) channel configured to provide a first PWM waveform having a first duty cycle and a first frequency. A second PWM channel is configured to provide a second PWM waveform having a second duty cycle and the first frequency. Combinational logic is configured to combine the first PWM waveform and the second PWM waveform to generate a phase-shifted reference PWM waveform having the first frequency and a phase shift that is based on the first duty cycle and the second duty cycle.

Abstract: A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output.

Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.

Abstract: A circuit implementing a soft logical processing network includes an interconnection of analog processing elements, which can include soft logic gates, for instance soft Equals gates and soft XOR gates. In some examples, each of the soft logic gates include multiple circuit parts, with each part including an input configured to accept a voltage signal representation of a soft logical quantity, and a conversion section configured to use the accepted voltage representation to form a corresponding current signal. The current signals are combined to form a signal representation of the output of the gate.

Abstract: A semiconductor integrated circuit includes a bypass circuit that forms a bypass path under a low voltage condition, and the bypass circuit includes first and second bypass MOS transistors respectively placed between drains of first and second PMOS transistors and a ground voltage terminal, each transistor having a gate to which a second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with an input signal and a voltage condition.

Abstract: A novel logic circuit in which data is held even after power is turned off is provided. Further, a novel logic circuit whose power consumption can be reduced is provided. In the logic circuit, a comparator comparing two output nodes, a charge holding portion, and an output-node-potential determining portion are electrically connected to each other. Such a structure enables data to be held in the logic circuit even after power is turned off. Further, the total number of transistors in the logic circuit can be reduced. Furthermore, the area of the logic circuit can be reduced by stacking a transistor including an oxide semiconductor and a transistor including silicon.

Abstract: A system is provided for generating an output clock used for N.5 modulus division. An edge-slip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edge-slip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusive-or (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to supply the output clock signal. The output clock signal has a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels. Alternatively, the output clock signal frequency is equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.

Abstract: An exclusive OR circuit includes, inter alia: a low pass unit configured to apply a second data to an output node when a first data is at a low level and to apply the first data to the output node when the second data is at a low level, and a discharge unit configured to discharge a voltage level of the output node when the first and second data are at a high level.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced.

Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.

Abstract: A digital signal generator includes an input unit configured to receive signal information of a target data signal, a controller configured to calculate at least two delay values and at least two data values, the at least two delay values and the at least two data values being used to generate a data signal corresponding to the signal information input through the input unit, a multi-phase clock generator configured to delay a reference clock signal based on the at least two delay values to generate at least two clock signals having different phases, a signal generator configured to generate at least two data signals by assigning the at least two data values to the at least two clock signals, and a logic gate unit configured to generate the data signal corresponding to the signal information input through the input unit based on the at least two data signals.

Abstract: A semiconductor device includes a chip, a plurality of pads that is formed along the perimeter of the chip, and that includes a first pad and a second pad placed next to the first pad, and a circuit that is formed on the chip, and that is coupled to the first and second pads. The circuit includes first and second conductivity type transistors that are coupled between first and second reference potentials and a comparator that includes a first input node coupled to the first pad and a second input node coupled to the second pad, and that compares a potential of the first input node with a potential of the second input node. The first pad is coupled to gate electrodes of the first and second conductivity type transistors, and the second pad is coupled to drain electrodes of the first and second conductivity type transistors.

Abstract: A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.