Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

Abstract: A method includes receiving, by a memory sub-system, host data to be written to a plurality of blocks of a memory device associated with a memory sub-system, where each of the plurality of blocks are coupled to one of a plurality of word lines of the memory device. The method can further include generating parity data for each word line of the block; dividing the parity data into one of either a first word line parity set or a second word line parity set; generating a reduced parity data set with exclusive or parity values for the first word line parity set and for the second word line parity set; and writing the reduced parity data set in the memory sub-system.

Abstract: A logic circuit includes a first pull-up driving circuit configured to drive a first inverted input signal to a supply voltage based on a first input signal, and configured to pull up an output signal based on the first input signal, a second input signal, and a third inverted input signal. The logic circuit also includes a first pull-down driving circuit configured to drive the third inverted input signal to a ground voltage based on the third input signal, and configured to pull down the output signal based on the first inverted input signal, the second input signal, and the third input signal.

Abstract: A positive feedback XOR/XNOR gate and a low-delay hybrid logic adder are provided. The low-delay hybrid logic adder comprises the positive feedback XOR/XNOR gate and an output circuit. The positive feedback XOR/XNOR gate comprises a first PMOS transistor and a second PMOS transistor used as pass transistors, a first NMOS transistor and a second NMOS transistor constituting a pull-down network, and a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor constituting a positive feedback loop. When an XOR logic output terminal of the positive feedback XOR/XNOR gate is pulled down below a switching threshold of an inverter formed by the third PMOS transistor and the fourth NMOS transistor, the positive feedback loop starts to operate to enable the XOR logic output terminal of the positive feedback XOR/XNOR gate to enter a pull-down phase to be pulled down to a low level to avoid threshold voltage losses.

Abstract: An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.

Abstract: A two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit including: N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines.

Abstract: Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.

Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

Abstract: Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit that supplies a signal to the gate electrode (e.g., word line driver) is provided with a selection circuit formed of an OR gate, an XOR gate, or the like, whereby potentials of word lines can be simultaneously set higher than potentials of bit lines.

Abstract: Disclosed herein is a logic circuit that includes a transistor T1 coupled between VPERI and a node n1, a transistor T2 coupled between VPERI and a node n2, a transistor T3 coupled between VSS and a node n3, a transistor T4 coupled between VSS and a node n4, transistors T5 and T7 coupled in series between the nodes n1 and n3, transistors T9 and T11 coupled in series between the nodes n1 and n3, transistors T6 and T8 coupled in series between the nodes n2 and n4, and transistors T10 and T12 coupled in series between the nodes n2 and n4. An output signal Y is output from a connection point of the transistors T5 and T7 and a connection point of the transistors T6 and T8.

Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

Abstract: Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.

Abstract: A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell.

Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.

Abstract: In some embodiments, new clock gating approaches, referred hereafter as State Transition Gating (STG) methods and circuits are provided. In areas of circuit designs including sequential elements, the use of STG may be used to reduce dynamic power consumption.

Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.

Abstract: A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region.

Abstract: A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal.

Abstract: A magnitude comparator for comparing magnitude of a first data and a second data is disclosed. The first data and the second data are both binary data. The magnitude comparator includes many non-least comparator cells and a P-channel transistor. Each of the non-least comparator cells includes a first transistor, a second transistor, a third transistor and a fourth transistor. The drain of the second transistor is electrically connected to the source of the first transistor, and the source of the second transistor is electrically connected to a ground terminal. The third transistor electrically connects the first transistor, and the fourth transistor electrically connects the first transistor and the third transistor. The source of the P-channel transistor electrically connects a supply terminal, the gate of the P-channel transistor electrically connects the ground terminal, and the drain of the P-channel transistor electrically connects the third transistor of the first comparator cell.

Abstract: A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops.

Abstract: A non-volatile logic gate, including a magnetic material having a shape induced magnetic anisotropy, wherein a shape of the magnetic material has a first vertex, a second vertex, and a third vertex and supports a single magnetic domain; regions of the magnetic material including a first input region adjacent the first vertex, a second input region adjacent the second vertex, and an output region adjacent a third vertex; the first input region for receiving a first logic input to the logic gate, the second input region for receiving a second logic input to the logic gate, and the output region for outputting at least one logic output of the logic gate; and the shape induced magnetic anisotropy determining at least part of a truth table for the logic gate, so that the logic gate produces the at least one logic output from the logic inputs using the shape.

Abstract: A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal.

Abstract: A high speed flip-flop circuit and a configuration method thereof are provided. A small number of transistors may be used to configure a flip-flop circuit, so that the flip-flop circuit may be operated at a high-speed. Additionally, an area occupied by the flip-flop circuit may be reduced, and power consumption may be reduced. Accordingly, the flip-flop circuit may be integrated together with a microwave frequency integrated circuit using a Gallium Arsenide (GaAs) compound semiconductor process.

Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.

Abstract: Systems and methods for implementing and using optoelectronic gates are disclosed. One such method includes superimposing an electrical data bit onto a first optical input to produce a pair of first-stage optical outputs. The first one of the pair of first-stage optical outputs carries the electrical data bit and the second carries the complement of the electrical data bit. The method further includes comparing an electrical target bit with the electrical data bit conveyed by the first first-stage optical outputs and with the complement of the electrical data bit conveyed by the second first-stage optical outputs, to determine whether the electrical target bit and the electrical data bit are same or different.

Abstract: An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.

Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

Abstract: An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.

Abstract: A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

Abstract: A data transition minimization method includes exclusive-NORing inputted nth image data (where n is a natural number) and (n?m)th image data (where m is a natural number smaller than n) expressing the same color as that of the nth image data to generate transition information data; generating inversion data indicative of inversion information by inverting all bits included in the transition information data and adding a unit bit having the logic value ‘1’ to the inverted transition information data when the number of unit bits having a logic value ‘1’ in the transition information data is larger than the number of unit bits having a logic value ‘0’ in the transition information data, and adding a unit bit having the logic value ‘0’ to the transition information data when the number of unit bits having the logic value ‘1’ in the transition information data is equal to or smaller than the number of unit bits having the logic value ‘0’ in the transition information data; exclusive-NORing the transition informati

Abstract: A mobile device that incorporates the MIPI D-PHY specification has data lanes for carrying data between electronic modules within the device. The data lanes may incorporate a spaced-one-hot approach for asynchronously receiving a data signal over a two-wire interface. A two-wire receive interface is provided that uses an exclusive-NOR to capture a timing signal along with a set-reset flip-flop which holds the state of the data line so that a D flip-flop that is clocked on the falling edge of the timing signal received from the exclusive-NOR gate can sample the data and provide an accurate asynchronous data output.

Abstract: In one embodiment, an exclusive-OR (XOR) calculation circuit configured to XOR a plurality of N input signals ranging from a first signal to an Nth signal is provided.

Abstract: A method for configuring a n-way XOR/XNOR circuit comprises providing a plurality of top stacks of PFETs each including at least three PFETs electrically connected between a high logic level and an output logic connection, providing a plurality of bottom stacks of NFETs each including at least three NFETs electrically connected between a low logic level and the output logic connection, connecting a source or a drain of the outermost PFET in each top stack to a source or a drain of a corresponding NFET in each bottom stack to generate inverted logic signals, inputting at least three input logic states to the stacks of PFETs to selectively connect or disconnect the output logic connection to the high logic level, inputting at least three input logic states to the stacks of NFETs to selectively connect or disconnect the output logic connection to the low logic level, and outputting a logic signal from the output logic connection.

Abstract: It is configured by plurality of NAND circuits connected in series through a plurality of inverters, and a plurality of NOR circuits connected in series through the plurality of inverters. Each of a plurality of source signal lines provided in a pixel portion is connected to one input terminal of a NAND circuit and a NOR circuit, and an output of an inspection is obtained from final lines of the NAND circuit and the NOR circuit connected in series. In this manner, an inspecting circuit which is capable of determining a defect simply and accurately by using a small-scale circuit, and a method thereof are provided.

Abstract: In one embodiment, an exclusive-OR (XOR) calculation circuit configured to XOR a plurality of N input signals ranging from a first signal to an Nth signal is provided.

Abstract: A logic circuit combining an exclusive OR gate and an exclusive NOR gate is provided. The logic circuit includes an NMOS transistor, a PMOS transistor, and first and second inverters. The NMOS transistor has a source connected to a first input signal, a drain connected to a first output signal, and a gate connected to a second input signal. The PMOS transistor has a source connected to the first input signal, a drain connected to a second output signal, and a gate connected to the second input signal. The first inverter receives the first output signal and outputs the second output signal. The second inverter receives the second output signal and outputs the first output signal.

Abstract: The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed.

Abstract: An exclusive-OR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-OR circuit may also include a switch configured to couple an output signal of the NAND gate to an output node when an output signal of the NOR gate is “LOW”, and a pull-down circuit configured to pull down the output node when the output signal of the NOR gate is “HIGH”. An exclusive-NOR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-NOR circuit may also include a switch configured to couple an output signal of the NOR gate to an output node when an output signal of the NAND gate is “HIGH”, and a pull-up circuit configured to pull up the output node when the output signal of the NAND gate is “LOW”.

Abstract: A 2-bit binary comparator, including: a comparison unit for receiving a first bit and a second bit to thereby compare the first bit with the second bit; and an enable unit for outputting a comparison result of the comparison unit as an output of the 2-bit binary comparator according to an enable signal.

Abstract: A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a given set of input signals, a pull-up path exists through the cross-couple circuit for one of the output node and the inverted output node, and wherein a pull-down path exists through the cross-couple circuit for the other one of the output node and the inverted output node.

Abstract: It is configured by plurality of NAND circuits connected in series through a plurality of inverters, and a plurality of NOR circuits connected in series through the plurality of inverters. Each of a plurality of source signal lines provided in a pixel portion is connected to one input terminal of a NAND circuit and a NOR circuit, and an output of an inspection is obtained from final lines of the NAND circuit and the NOR circuit connected in series. In this manner, an inspecting circuit which is capable of determining a defect simply and accurately by using a small-scale circuit, and a method thereof are provided.

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract: A filter network designed for providing high frequency selectivity with a high degree of reliability and availability. The filter network comprises a superconducting filter and a non-superconducting filter, or a combination thereof to form multiplexers. A receive side of the non-superconducting filter pre-filters received RF signals before inputting them to the superconducting filter. The non-superconducting filter is constructed and arranged to pass RF signals having a frequency within a first pass band to the superconducting filter. The superconducting device is constructed and arranged to exhibit a high-degree of frequency selectivity in further narrowing the received RF signals. Other aspects are directed to the arrangement, construction, and uses of the same structures to accomplish different but similar goals.

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract: Described are methods and circuits for aligning data and clock signals. Methods in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract: A logic circuit capable of suppressing occurrence of wraparound of signals, capable of reducing power consumption, and in addition achieving a reduction of a circuit scale and an improvement of an operating speed and a full adder using the same, wherein provision is made of an exclusive-OR generation circuit 12 for receiving a first logic signal A and a second logic signal B taking a logic “1” or “0” and generating the exclusive-OR of the first logic signal A and the second logic signal B, a dual signal generation circuit 11 for receiving the first logic signal A and the second logic signal B and generating the dual signal of the exclusive-OR of the first logic signal A and the second logic signal B, and an interpolation circuit 13 for compulsorily setting the output level of the dual signal at the level of the logic “1” when the output level of the exclusive-OR is the logic “0”, while compulsorily setting the output level of the exclusive-OR at the level of the

Abstract: A coincidence determining circuit determines whether first and second digital data each consisting of a plurality of bits coincide with one another. The coincidence determining circuit includes a wiring and a plurality of bit comparison circuits corresponding in number to the bits. Each bit comparison circuit includes first and second transistors connected in series between the wiring and a power supply line and third and fourth transistors connected in series between the wiring and the power supply line. The first and second transistors receive a first logical signal of an associated bit of the first digital data and an inverted signal of a second logical signal of an associated bit of the second digital data. The third and fourth transistors receive an inverted signal of the first logical signal and the second logical signal. The four transistors of each bit comparison circuit suppress an increase in circuit area.