Abstract: The present invention provides a semiconductor integrated circuit comprising a plurality of logic circuits, each of which has at least a first field effect transistor with a first gate connected to a high voltage line and at least a second field effect transistor with a second gate connected to a ground line, wherein said first gates of said plurality of logic circuits are commonly connected through a first interconnection structure to a first resistance which is connected to said high voltage line and wherein said second gates of said plurality of logic circuits are also commonly connected through a second interconnection structure to a second resistance which is connected to said ground line. The first and second interconnection structures enable the single first resistance and the single second resistance to prevent the gate breakdown of the gates in the plurality of the logic circuits.

Abstract: The first store unit (R1) for receiving and storing the first input (AI), the second store unit (R2) for receiving and storing the second input (BI), a selection unit (SEL) for selecting one of outputs from the first inverter (IV1) and the second inverter (IV2) in the second store unit (R2) in response to an output of the first store unit (R1) are provided in an operation circuit. This constitution, which has a function of storing the first input (AI) and the second input (BI) and a function of performing an exclusive-OR operation between the first input (AI) and the second input (BI), allows reduction in circuit scale.

Abstract: An exclusive OR circuit (10) includes an input stage (11) and a control arrangement (12,13) for controlling an exclusive OR logical evaluation. The control arrangement includes a pre-charge stage (12) which responds to a first level clock signal to enable the desired exclusive OR logical evaluation. The input stage (11) is connected to receive a first input signal and a second input signal and is also connected to an evaluation node (23). When the logic state of one input signal is unequal to the logic state of the other input signal, the input stage (11) couples the evaluation node (23) to ground. An output stage (13) of the control arrangement inverts the signal at an internal node (24) to produce the output from the exclusive OR circuit. A pre-charge stage (12) couples the internal node (24) to the evaluation node (23) only in response to a "high" clock signal.

Abstract: An integrated XNOR flip-flop is provided which is faster than conventional XNOR flip-flop combinations. The integrated XNOR flip-flop is faster and uses less area than conventional XNOR flip-flop combinations. The integrated circuit has few gates along the critical path and takes advantage of the set up times inherent in the flip-flop. Accordingly, the integrated XNOR flip-flop is able to perform the same function in an expedient manner. In one illustrative embodiment, a plurality of the integrated XNOR flip-flops are used to compare a tag of a cache memory with an address to determine whether the desired address is available in the cache.

Abstract: An N-bit comparator compares two numbers A and B each consisting of N bits to each other and includes: N one-bit comparing circuits for generating a second output of a first level and a first output of a second level which is complementary to the first level if a bit ai (0.ltoreq.i.ltoreq.N-1) of the number A is equal to a bit bi (0.ltoreq.i.ltoreq.N-1) of the number B, for generating the second output of the second level and the first output of the first level if bit ai is greater than bit bi, and for generating the first output of the second level and the second output of the second level if bit ai is less than bit bi; and a final comparing circuit for receiving the first and second outputs of the one-bit comparing circuits and for generating a final comparative result of the two numbers by a comparative result of lower places when upper places of the two numbers are equal to each other.

Abstract: An exclusive-OR circuit is for use in a delay device outputting a signal delayed from an input signal. The exclusive-OR circuit comprises an odd number of inverters, an even number of inverters, and a two-input selector. In the two-input selector, an inversion control signal for determining whether to invert a signal to be output, is input to one of input terminals via the odd number of inverters, and input to the other of the input terminals via the even number of inverters, and the input signal is supplied to a control terminal as a control signal for determining which of two signals input to the input terminals is output.

Abstract: A high speed logic module is formed to include a differential input formed as a pair of inductive transmission lines and a differential output also formed as a pair of inductive transmission lines. A pair of logic devices are included in the module, with the gate terminals of the devices coupled to separate ones of the input inductive transmission lines. The output terminals of the logic devices are coupled to separate ones of the pair of output inductive transmission lines. The effects of the intrinsic gate-to-drain capacitance C.sub.gd inherent in each logic device is compensated for by including a pair of cross-coupled neutralizing capacitors between the drain and gate terminals of the logic devices. Various logic circuits, such as oscillators, latches, delay lines, etc. can be formed using the differential, neutralized structure of the invention.

Abstract: Logic devices of the present invention have one or more MOSFETs that are configured to operate in logic circuits, where voltages applied to the source and drain of each MOSFET are treated as logic inputs to the circuit and the resulting substrate current is treated as the logic output of the circuit. In one implementation, a MOSFET is configured in a circuit to operate as an XOR gate where a load resistor between the substrate and ground converts the substrate current into an output voltage. A sample-and-hold circuit samples and holds the output voltage to isolate the XOR gate thereby allowing DC power dissipation to be reduced. In another implementation, three MOSFETs are configured to operate as an "ORNAND" logic device that performs the logical addition of the OR function and the NAND function.

Abstract: A three-input exclusive NOR circuit having three signal paths provided between three input terminals and three-input exclusive OR node, each of the signal paths having two first conduction type transistors connected in series, said two first conduction type transistors being in conductive state when a low level signal is applied to the gate terminal of the transistor; and three signal paths provided between three input terminal and three-input exclusive OR node, each of the signal paths having two second type transistors being in conductive state when a high level signal is applied to the gate terminal of the transistors, wherein two input signals other than the input signal to a signal path is respectively supplied to the gate terminals of two of the first and second conduction type transistors.

Abstract: A four transistor XOR or XNOR gate includes an inverting stage and a non-inverting stage. The transistors in each stage are coupled so as to enable changing inputs and existing inputs to drive the output in the same direction. The XOR gate and XNOR gate take advantage of a known order or inputs to reduce the delay of the gate.

Abstract: A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states.

Abstract: Tri-state devices having exclusive gate output control include a tri-state device having first and second inputs and a tri-state output, a normally-off transistor connected in series between the tri-state output and a first reference potential (e.g., VCC or VSS) and an exclusive gate (e.g., NOR, OR) having first and second inputs coupled to the first and second inputs of said tri-state device, respectively, and an output electrically coupled to a control electrode of said normally-off transistor so that the tri-state output becomes electrically connected through the normally-off transistor to the first reference potential whenever the first and second inputs of said tri-state device are at different logic potentials. However, the normally-off transistor is maintained in a nonconductive state to reduce power consumption whenever the output of the tri-state device is switched to VCC or VSS.

Abstract: An exclusive OR/NOR gate circuit which is capable of achieving a low power consumption, a reliable operation, and a fast operation speed, and of being operated irrespective of any kind of process and in accordance with any value of two input signals, that is, being full-swung at a low power, having no necessity of an inverter circuit for an input signal and an additional output circuit by using NOR/NAND gates, and consequently of being adapted to any field requiring a low power and a high efficiency operation.

Abstract: A new type exclusive-OR gate and an inverted type selector are composed using a cascaded connection of two p-type MOSFETs between a positive terminal of a power supply and an signal output terminal, and a cascaded connection of two n-type MOSFETs between a grounded terminal of the power supply and the signal output terminal. Power consumption in the new type exclusive-OR gate and the inverted type selector is reduced by reducing number of conventional inverters used in these circuits. A full-adder and a 4-2 compressor are designed using these new type exclusive-OR gates and inverted selectors or an inverted type selector.

Abstract: The gates (11) of the exclusive OR type having two inputs (A, B) are disposed in tree structure in successive layers of an integrated circuit beginning with an input layer which receives the input signals of the tree. The output of each gate is connected to an input of a gate in the adjacent layer. Each gate includes two cells (11a, 11b) that switch substantially simultaneously in response to two respective complementary signals (A, NA; B, NB) from one of the two inputs and that supply respective output signals that are representative of the complementary functions (XOR, NXOR) of the exclusive OR type. This makes it possible to obtain propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagated may be.

Abstract: An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input.

Abstract: A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration.

Abstract: A static XOR gate is provided with circuit speeds necessary to meet the increasing demand of higher computer clock frequencies. The XOR of the present invention takes up less area and consumes less power than prior art XOR circuits. Furthermore, time XOR gate of the present invention is fully static and imposes less constraints on the circuit designer, e.g. no reset logic, input synchronization, or the like. The circuit utilizes only NMOS transistors in the functional logic portion with two output inverters. The circuit elements are symmetrical and have identical input loading, output drive and propagation paths. The XOR of the present invention allows multiple gates to be connected in stages as a "tree" configuration by providing a "push-pull" XOR/EQV (equivalent, i.e. time complement of the XOR output or XNOR) function which is buffered by output inverters to "push" the output to a next stage.

Abstract: A logic circuit including a pair of FETs connected in parallel and including first and second common current terminals, each of the FETs further having a control terminal connected to receive a logic signal thereon. A negative differential resistance device affixed to one of the first and second common current terminals and having a conductance characteristic such that the device operates at a peak current when one of the FETs is turned ON and at a valley current when both of the FETs are simultaneously turned ON. A load resistance coupled to the other of the first and second common current terminals and providing an output for the logic circuit.

Abstract: A logic circuit includes a differential amplifier circuit to which a first input signal and a second input signal both of which are complementary are to be supplied, having a circuit for outputting a first output signal and a second output signal both of which are complementary, the first and second output signals depending on a difference between the first and second input signals, an output terminal, and a switching circuit for, based on a first switching signal and a second switching signal which are complementary, performing a switching operation so that either the first output signal or the second output signal is selected as a signal supplied to the output terminal, wherein the signal supplied to the output terminal is a result of an logical operation of the first input signal and the first switching signal. A current sense amplifier may be substituted for the differential amplifier.