Abstract: A method in one embodiment creates a model of an authentic IC for use in comparisons with counterfeit ICs. The model can be created by determining a first or initial set of points of interest (POIs) on the simulated physical (e.g., gate level) layout and simulating side channel leakage from each POI and then expanding the size of the POI and repeating the simulation and comparing successive simulation results (between successive sizes of POIs for a given POI) to determine if a solution for the size of the POI has converged. The final POIs are then processed in a simulation that can use multiple payloads (e.g., cryptographic data) over the entire set of final POIs, and the resulting data set can be used to create the model.

Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; a power circuit providing a supply voltage to the target circuit under test, the supply voltage maintaining at a first voltage level in the first period and deviating from the first voltage level, and maintaining at the first voltage level in the second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.

Abstract: A circuit screening system includes a target circuit under test, a power circuit, and a clock generating circuit. The target circuit under test receives a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal. The power circuit provides a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period. The clock generating circuit provides a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period.

Abstract: To provide a miniaturized data holding circuit. First and second MOS transistors respectively transmit a data signal and an inverted data signal to inputs of first and second inverting gates that constitute a state holding circuit when a clock signal is at a first level. Fifth and sixth MOS transistors are respectively inserted in a feedback path from an output of the second inverting gate to the input of the first inverting gate and a feedback path from an output of the first inverting gate to the input of the second inverting gate, and respectively transmit the outputs of the second and first inverting gates when the clock signal is at a second signal level.

Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.

Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

Abstract: A method and system are provided for reading a non-transitory memory array. When a default read operation is performed and has failed, a dynamic sensing bit line voltage (VBLC) enhanced read or a dynamic sense time read is performed. According to the dynamic VBLC enhanced read or the dynamic sense time enhanced read, the VBLC or the sense time is increased, and a read is performed with the increased VBLC or increased sense time. If this enhanced read is unsuccessful, and if a maximum VBLC or a maximum sense time has not yet been reached, the VBLC or the sense time is increased again, and another read is performed. Once the maximum VBLC or a maximum sense time has been reached, if the read is still not successful, a read failure is reported.

Abstract: Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type TFETs; a first clock node coupled to a source terminal of the first TFET, the first clock node is to provide a first clock; and a second clock node coupled to a source terminal of the second TFET, the second clock node is to provide a second clock.

Abstract: A circuit for storing data in an integrated circuit is described. The circuit comprises an input adapted to receive the data; a memory element coupled to the input, the memory element comprising a storage node for storing the data; at least one node that is separate from the storage node for storing the data; and at least a portion of a dummy transistor coupled to the at least one node that is separate from the storage node for storing the data. A method of storing data in an integrated circuit is also described.

Abstract: Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Abstract: Systems, methods, and devices are provided for increasing uniformity of wear in semiconductor devices due to, for example, negative-bias temperature instability (NBTI). The method may include receiving a first NBTI control signal. The method may involve receiving a second NBTI control signal based at least in part on the first NBTI control signal. The method may also involve asserting the first NBTI control signal at a clock input pin of a latch. Further, the method may include asserting the second NBTI control signal at a data input pin of the latch. The method may additionally involve toggling electrical elements downstream of the latch based at least in part on an output of the latch based on the first and second NBTI control signals to increase uniformity of wear on the electrical elements in a default low-power state during NBTI toggling mode.

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits preventing hold violations in clock synchronized circuits. In an example implementation, a circuit includes a logic circuit having a set of inputs. Signal propagation time on a signal path to at least one of the set of inputs presents a hold violation. The circuit includes first and second level-sensitive latches. The first level-sensitive latch has an output connected to the one of the plurality of inputs. The second level-sensitive latch has an input connected to an output of the logic circuit. A latch control circuit is configured to remove the hold violation on the input by providing a pulsed clock signal to a clock input of the second level-sensitive latch and an inversion of the pulsed clock signal to a clock input of the first level-sensitive latch.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: According to one embodiment, a method for manufacturing a digital circuit is described comprising forming a modified RS master latch with an output for outputting an output signal comprising forming two field effect transistors which are virtually identical wherein the two formed field effect transistors are connected to each other in an RS latch type configuration and the respective threshold voltages of the two field effect transistors are set to be different from each other so that the output signal of the modified RS master latch in response to an RS latch forbidden input transition has a predetermined defined logic state, forming an RS slave latch having a set input and a reset input and connecting the set input or the reset input of the RS-slave latch to the output of the modified RS master latch.

Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

Abstract: Aspects of the disclosure provide a circuit having a pulse latch circuit and an enable circuit. The latch circuit is configured to receive a first signal at an input lead and drive the first signal to an output lead in response to an enable signal. The enable circuit is configured to be active to generate the enable signal to enable the latch circuit to receive the first signal when the first signal is different from a second signal on the output lead and is configured to default the enable signal to suppress the first signal so as not to be received at the latch circuit when the first signal is the same as the second signal.

Abstract: An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

Abstract: A voltage providing circuit includes a first circuit configured to receive a first input signal and a second input signal and to generate an output signal. The first circuit includes a first transistor configured to switchably couple the second input signal to a first node responsive to the first input signal, a second transistor having a gate terminal coupled with the first node, and a third transistor having a source terminal coupled with a source terminal of the second transistor. The third transistor is configured to set a reference voltage value at the source terminal of the second transistor if the first input signal indicates that the second input signal is pulled from a first voltage value toward a second voltage value and if the second input signal reaches a predetermined voltage value. A second circuit is configured to receive the output signal and to generate an output voltage.

Abstract: A retention flip-flop is provided. The flip-flop includes a clock generation circuit, a master latch circuit, and a salve latch circuit. The clock generation circuit generates first and second clock signals in a first mode. The master latch circuit performs a first latch operation on an input signal from the input terminal according to the first and second clock signals to generate a first latched signal at a first node in the first mode. The salve latch circuit performs a second latch operation on the first latched signal according to the first and second clock signals to generate a second latched signal at a second node in the first mode. In a sleep or power-down mode, the total number of transistors in the clock generation circuit and the salve latch circuit is equal to or less than eight.

Abstract: A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.

Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

Abstract: Aspects include a computer-implemented method for scanning data into a shift register. The method includes receiving, by a circuit, a data signal, wherein the data signal propagates in a first direction; and receiving, by the circuit, a clock signal, wherein the clock signal propagates in a second direction, wherein the second direction is in a reverse direction of the first direction.

Abstract: Aspects disclosed herein describe a keeper circuit that adapts to variations in the fabrication process used to manufacture a dynamic circuit. The different characteristics of the circuit elements may cause a keeper circuit to behave in an unintended manner. In one example, a logical state of the dynamic circuit may be erroneously changed because of a strong (i.e., leaky) NMOS transistor in a pull down or discharge path. An adaptive keeper circuit, however, is designed to prevent such unintended behavior regardless of any change in the characteristics of the circuit elements in the dynamic circuit. The adaptive keeper circuit matches the behavior of the pull down path and prevents the pull down path from erroneously changing the logical state stored by the dynamic circuit.

Abstract: Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage 6 where it is used to control generation of a second stage state signal. The pulse amplifying circuitry 8 comprises a chain of serially connected skewed inverters 20, 22. The action of the pulse amplifying circuitry 8 is to reduce the probability of metastability in the output of the second dynamic stage 6.

Abstract: An oscillator circuit includes a voltage-controlled oscillator configured to output an AC output signal having a predetermined frequency, which changes due to temperature and fabrication process variations and a control voltage generating circuit configured to provide a voltage signal to the voltage-controlled oscillator to maintain the predetermined frequency by compensating for the temperature and fabrication process variations.

Abstract: The present disclosure relates to a computer-implemented method for transient simulation of an input/output buffer model. The method may include generating an input/output buffer data file associated with a first model of an electrical circuit. The method may also include determining at least one of a node voltage and a branch current associated with the electrical circuit using, at least in part, a latency insertion method, the method may further include performing one or more simulations on a second model of an electrical circuit, the one or more simulations incorporating, at least in part, the input/output buffer data file and the latency insertion method.

Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

Abstract: A leakage current detection circuit detects a switch current flowing in a switch which is targeted for leakage monitoring, and generates a detection signal to prohibit operation of a control target circuit which is targeted for control when the switch current does not reach a predetermined threshold value.

Abstract: A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates.

Abstract: A dynamic logic gate includes a nano-electro-mechanical-switch, preferably a four-terminal-nano-electro-mechanical-switch. The invention further refers to dynamic logic cascade circuits comprising such a dynamic logic gate. In particular, embodiments of the invention concern dynamic logic cascade circuits comprising single or dual rail dynamic logic gates.

Abstract: A scan flip-flop, which performs a normal operation latching a data input and a scan operation latching a scan input, includes a first circuit, a second circuit and a latch. The first circuit determines a voltage of an intermediate node based on a clock signal, one of the data input and the scan input, and data of a latch input node. The second circuit determines the data based on the clock signal, the voltage of the intermediate node and the data input during the normal operation, and determines the data based on the clock signal and the voltage of the intermediate node during the scan operation. The latch latches the data based on the clock signal.

Abstract: An integrated circuit includes a first pipeline with multiple stages of asynchronous circuits. Note that a stage in the first pipeline communicates with a stage in a corresponding second pipeline with multiple stages of asynchronous circuits on another integrated circuit via connectors. Furthermore, a first state wire preceding the stage in the first pipeline provides advanced notice to a first state wire preceding the stage in the second pipeline of subsequent communication between the stage in the first pipeline and the stage in the second pipeline so that the stage in the second pipeline has time to amplify a signal received from the stage in the first pipeline, thereby facilitating approximately synchronous operation of the stages in the first and second pipelines.

Abstract: An output driver circuit may include a electrically conductive medium, an output logic inverter having a first switch adapted to couple a first positive supply voltage to the electrically conductive medium and a second switch adapted to couple a ground supply voltage to the conductive medium. A first biasing network includes a first input that is coupled to the conductive medium, a second input that receives a clock signal, and a first output that is adapted to couple a second positive supply voltage to each input of the first and the second switch. Based on the second switch coupling the conductive medium to the ground supply voltage and the received clock signal generating a logic low, the biasing network reverse biases the first switch by coupling the second positive supply voltage to the respective input of the first switch causing a leakage current reduction in the first switch.

Abstract: A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p-channel metal-oxide-silicon (PMOS) transistor.

Abstract: A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit.

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

Abstract: A timing margin circuit of a local clock buffer circuit may include an inverter logic gate having an inverter input and an inverter output, whereby the inverter input receives an input clock signal. A NAND logic gate includes a first NAND input coupled to the inverter output, a second NAND input, and a NAND output. The circuit also includes a logic device having a first logic device input that is coupled to the inverter output, a second logic device input that receives a mode selection signal, and a logic device output that couples to the second NAND input, whereby the NAND logic gate generates a first time delayed input clock signal and a second time delayed input clock signal, such that the first and the second time delayed input clock signal control a falling edge transition of a local clock signal derived from the input clock signal.

Abstract: An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.

Abstract: A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.

Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.

Abstract: Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a first inverter configured to receive first and second clock signals and further includes a second inverter configured to receive the first and second clock signals. The first inverter is configured to provide to an output node an inverted first clock signal as controlled by the second clock signal. The second inverter is configured to provide to the output node an inverted second clock signal as controlled by the first clock signal. Another example apparatus includes a clock generator circuit to provide first and second clock signals responsive to an input clock signal, and further includes a duty phase interpolator circuit, a duty cycle adjuster and a duty cycle detector.

Abstract: A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.

Abstract: A clock-delayed domino logic circuit includes a first pre-charge circuit configured to pre-charge a first dynamic node with a pre-charge voltage in response to a first clock signal received via a first control terminal during a pre-charge operation; a first logic network configured to determine a logic level of the first dynamic node in response to first input data signals during an evaluation operation; and a first storage circuit which is connected between the first control terminal and the first dynamic node.

Abstract: The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved.

Abstract: A dual-mode logic gate, for selectable operation in either of static and dynamic modes, includes: a static gate which includes at least one logic input and a logic output; a mode selector, configured for outputting a turn-off signal to select static mode operation and for outputting a dynamic clock signal to select dynamic mode operation; and a switching element associated with the mode selector static gate, comprising a first input connected to a constant voltage, a second input for inputting the mode selection signal from the mode selector, and an output connected to a logic output of the static gate. The switching elements switches the logic gate operation from static to dynamic mode, by applying the appropriate signal to the switching element.

Abstract: Embodiments of the present disclosure enable low swing dynamic circuits with reduced dynamic power and leakage power. In an embodiment, a level detector circuit monitors the pre-charge voltage level of the dynamic node of a dynamic circuit and discontinues the charging of the dynamic node when the pre-charge voltage exceeds a logic high reference voltage. The logic high reference voltage is selected below a supply voltage of the dynamic circuit, resulting in a low swing dynamic circuit. In another embodiment, the pull-down logic circuitry is disconnected from the dynamic node when the dynamic node voltage falls below a logic low reference voltage, above a ground voltage. In another embodiment, a DC keeper circuit of the dynamic circuit is configured based on the pre-charge level of the dynamic node.

Abstract: When a semiconductor device is provided with an inverter comprising a transistor having a first gate and a second gate, the semiconductor device does not require a circuit for generating a potential to be input to the second gate of the transistor and has a small number of wirings. Moreover, a semiconductor device having high reliability is provided. The semiconductor device includes a plurality of stages of circuits each provided with two inverter circuits in parallel. Two inverter circuits in a given stage output respective signals of opposite polarities, which is utilized for interchanging signals output from inverter circuits in the previous stage. Thus, an inverted signal is input to the second gate of the transistor included in each of two inverter circuits in the subsequent stage.

Abstract: A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.

Abstract: A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate.