Field-effect Transistor Patents (Class 326/95)
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Publication number: 20140292371Abstract: A Multi-Threshold Dual-spacer Dual-rail Delay-insensitive Logic (MTD3L) circuit architecture. The architecture includes a first th22 circuit, a second th22 circuit, and an XNOR gate. The first th22 circuit is configured to receive a first rail input, a completion detection signal, and a reset signal, and to produce a first rail output. The second th22 circuit is configured to receive a second rail input, the completion detection signal, and the reset signal, and to produce a first rail output. The XNOR gate is configured to receive the first rail input and the second rail input and to produce a completion detection signal output.Type: ApplicationFiled: April 10, 2013Publication date: October 2, 2014Inventor: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS
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Patent number: 8847627Abstract: A semiconductor device includes a first transistor, a second transistor, a first transistor group, and a second transistor group. The first transistor group includes a third transistor, a fourth transistor, and four terminals. The second transistor group includes fifth to eighth transistors and four terminals. The first transistor, the third transistor, the sixth transistor, and the eighth transistor are n-channel transistors, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are p-channel transistors.Type: GrantFiled: May 16, 2012Date of Patent: September 30, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Patent number: 8836402Abstract: A phase splitter includes: a first signal path; and a second signal path, wherein the phase splitter outputs an internal signal of the first signal path as a first phase signal, and mixes an output signal of the first signal path with an output signal of the second signal path, thereby outputting a second phase signal having a predetermined phase difference from the first phase signal.Type: GrantFiled: March 18, 2013Date of Patent: September 16, 2014Assignee: SK Hynix Inc.Inventor: Min Sik Han
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Patent number: 8836371Abstract: Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations.Type: GrantFiled: January 22, 2013Date of Patent: September 16, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Perry H. Pelley, James D. Burnett
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Patent number: 8797065Abstract: A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.Type: GrantFiled: December 20, 2012Date of Patent: August 5, 2014Assignee: Fujitsu LimitedInventor: Tomohiro Tanaka
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Patent number: 8786309Abstract: A multi-path power switch scheme for functional block wakeup is disclosed. The scheme may be applied to functional blocks of an integrated circuit. When a power on procedure is initiated within a given functional block, a first group of power switches in a functional block may be powered on, while a second group of power switches is inhibited from powering on. After a predetermined time has elapsed, activation of the second group of power switches is initiated. After initiation of a power up procedure for a given functional block, the powering up of a second functional block to be powered on may initially be inhibited. After a predetermined time has elapsed, the powering on of the second functional block may be initiated. Overlap between times when the first and second groups of switches are active may depend on process, voltage, and temperature variations.Type: GrantFiled: October 31, 2011Date of Patent: July 22, 2014Assignee: Apple Inc.Inventors: Toshinari Takayanagi, Shingo Suzuki
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Patent number: 8786345Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.Type: GrantFiled: March 28, 2013Date of Patent: July 22, 2014Assignee: NVIDIA CorporationInventors: Jonah M. Alben, William J. Dally
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Patent number: 8779798Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.Type: GrantFiled: May 15, 2012Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kiyoshi Kato
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Patent number: 8760208Abstract: An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the first terminal. The feedback circuit may include electronic logic elements to determine if the storage circuit is in a metastable state. The feedback circuit may couple at least one of the first and second terminals to one of a voltage reference and a voltage source if determined that the storage circuit is in a metastable state.Type: GrantFiled: March 30, 2012Date of Patent: June 24, 2014Assignee: Intel CorporationInventors: Charles E. Dike, Mark E. Schuelein
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Patent number: 8729942Abstract: Some of the embodiments of the present disclosure provide a D-type flip-flop, comprising a first latch configured to generate a sample enable signal, based on logical states of an input signal, and generate a sampled signal, based on logical states of the input signal and the sample enable signal; and a second latch configured to generate an output signal responsively to the sampled signal. Other embodiments are also described and claimed.Type: GrantFiled: November 20, 2013Date of Patent: May 20, 2014Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventor: Mel Bazes
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Patent number: 8692579Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.Type: GrantFiled: May 15, 2012Date of Patent: April 8, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kiyoshi Kato
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Patent number: 8669800Abstract: A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.Type: GrantFiled: February 24, 2012Date of Patent: March 11, 2014Assignee: International Business Machines CorporationInventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
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Patent number: 8659320Abstract: A digital logic gate suitable for a high-speed operation of a central processing unit. The digital logic gate comprises the first dynamic logic gate configured to logically gate a plurality of first input data in response to the first clock signal, a second dynamic logic gate configured to logically gate a gating output of the first dynamic logic gate and a plurality of second input data, and a latching device configured to latch a gating output of the second dynamic logic gate. The digital logic circuit need not adopt a keeper circuit, and thus a gate delay is reduced and the digital logic circuit performs a high-speed gating operation with robust characteristic against a current leakage or an input noise.Type: GrantFiled: October 21, 2011Date of Patent: February 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Hyoungwook Lee
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Patent number: 8653852Abstract: In a particular embodiment, an apparatus includes a a dynamic circuit structure that includes a dynamic node coupling a precharge circuit, a discharge circuit, and a gated keeper circuit. The gated keeper circuit is enabled by a signal from a discharge delay tracking circuit.Type: GrantFiled: March 14, 2011Date of Patent: February 18, 2014Assignee: QUALCOMM IncorporatedInventors: Jentsung Lin, Paul Douglas Bassett
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Patent number: 8604855Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.Type: GrantFiled: June 18, 2013Date of Patent: December 10, 2013Assignee: NVIDIA CorporationInventors: William J. Dally, Jonah M. Alben, John W. Poulton, Ge Yang
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Patent number: 8593194Abstract: Some of the embodiments of the present disclosure provide a D-type flip-flop, comprising a first latch configured to generate a sample enable signal, based on logical states of an input signal, and generate a sampled signal, based on logical states of the input signal and the sample enable signal; and a second latch configured to generate an output signal responsively to the sampled signal. Other embodiments are also described and claimed.Type: GrantFiled: November 18, 2011Date of Patent: November 26, 2013Assignee: Marvell Israel (M.I.S.L) Ltd.Inventor: Mel Bazes
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Publication number: 20130307585Abstract: A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal.Type: ApplicationFiled: July 23, 2013Publication date: November 21, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Chen kong Teh, Hiroyuki Hara
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Patent number: 8581629Abstract: An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.Type: GrantFiled: May 17, 2012Date of Patent: November 12, 2013Assignee: Texas Instruments IncorporatedInventors: Gary F. Chard, Scott A. Morrison, Susan A. Curtis, Daniel A. King
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Patent number: 8570069Abstract: A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output.Type: GrantFiled: April 19, 2012Date of Patent: October 29, 2013Assignees: STMicroelectronics S.A., STMicroelectronics S.r.l.Inventors: Mounir Zid, Alberto Scandurra
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Patent number: 8564331Abstract: A semiconductor device in which an input terminal is electrically connected to a first terminal of a first transmission gate; a second terminal of the first transmission gate is electrically connected to a first terminal of a first inverter and a second terminal of a functional circuit; a second terminal of the first inverter and a first terminal of the functional circuit are electrically connected to a first terminal of a second transmission gate; a second terminal of the second transmission gate is electrically connected to a first terminal of a second inverter and a second terminal of a clocked inverter; a second terminal of the second inverter and a first terminal of the clocked inverter are electrically connected to an output terminal; and the functional circuit includes a data holding portion between a transistor with small off-state current and a capacitor.Type: GrantFiled: May 2, 2012Date of Patent: October 22, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Seiichi Yoneda
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Patent number: 8552762Abstract: A wire-OR matching circuit with low power consumption can be enabled by inputting an input-enabling signal representing “enabled.” The wire-OR matching circuit generates an output-enabling signal according to a control signal and a periodic pulse signal. When the periodic pulse signal represents “turn on”, if the input-enabling signal represents “enabled” and the control signal represents “not disabled”, the output-enabling signal represents “enabled;” if the input-enabling signal represents “enabled” and the control signal represents “disabled”, the output-enabling signal represents “not enabled.” The wire- or matching circuit can promptly break the connection between the high voltage source and the low voltage source by controlling the pulse width of the periodic pulse signal. In this way, large current is avoided, saving power consumption.Type: GrantFiled: October 20, 2011Date of Patent: October 8, 2013Assignee: Etron Technology, Inc.Inventors: Chia-Wei Chang, Feng-Chia Chang
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Patent number: 8552761Abstract: A flip-flop includes a transmission circuit configured to transmit data to a transmission line in response to a clock signal and a complementary clock signal. The flip-flop further includes a keeper circuit configured to latch data of the transmission line in response to the clock signal and the complementary clock signal to maintain the data of the transmission line constant.Type: GrantFiled: September 21, 2011Date of Patent: October 8, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventor: Min Su Kim
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Patent number: 8542033Abstract: A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node.Type: GrantFiled: September 16, 2011Date of Patent: September 24, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyoung-Wook Lee, Gun-Ok Jung, Suhwan Kim, Ah-Reum Kim, Rahul Singh
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Patent number: 8531208Abstract: A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.Type: GrantFiled: March 2, 2012Date of Patent: September 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Gun Ok Jung, Min Su Kim, Uk Rae Cho, Dae Young Moon, Hyoung Wook Lee
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Patent number: 8519743Abstract: A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal.Type: GrantFiled: March 12, 2010Date of Patent: August 27, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Chen kong Teh, Hiroyuki Hara
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Patent number: 8487681Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.Type: GrantFiled: February 23, 2011Date of Patent: July 16, 2013Assignee: NVIDIA CorporationInventors: William J. Dally, Jonah M. Alben, John W. Poulton, G E (Francis) Yang
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Patent number: 8482316Abstract: Circuits, methods, and systems are presented for managing current leakage in an electronic circuit. One circuit includes a keeper circuit, and a controller. The keeper circuit supplies current to a leaker circuit, which is experiencing current leakage, to compensate for the current leakage. Further, the controller provides to the keeper circuit a control signal that is based on the current leakage. The control signal has a cycle equal to the cycle of a clock signal, and the control signal is a pulse having a first value during a first period, and a second value during a second period of the pulse. The keeper circuit provides a current to the leaker circuit during the first period and the keeper circuit withholds the current to the leaker circuit during the second period, where the durations of the first period and the second period are based on the current leakage.Type: GrantFiled: March 2, 2012Date of Patent: July 9, 2013Assignee: Oracle International CorporationInventors: Zhen Wu Liu, Shree Kant, Heechoul Park
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Patent number: 8482315Abstract: A one-of-n storage cell for use in an N-nary dynamic logic (NDL) circuit. The storage cell may accept an input value and provide a complemented output value that corresponds to the input value. However, if an input value that corresponds to a precharge input value is received, the output value remains the previous output value. The storage cell may be implemented to accept either inverted or non-inverted one-of-n NDL signals and to provide as an output either non-inverted or inverted one-of-N NDL signals, respectively, where N is greater than two.Type: GrantFiled: August 23, 2011Date of Patent: July 9, 2013Assignee: Apple Inc.Inventors: Michael R. Seningen, Raymond C. Yeung
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Patent number: 8451040Abstract: A flip-flop circuit includes an input portion that receives a first external input signal through a first external input terminal, a storage portion that stores a signal transmitted from the input portion, and an output portion that outputs the signal stored in the storage portion through an external output terminal as a logic operation result with respect to a second external input signal received through a second external input terminal of the input portion. The output portion includes a logic gate directly connected to the external output terminal and an input terminal of the logic gate receives the signal stored in the storage portion.Type: GrantFiled: December 8, 2010Date of Patent: May 28, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hoijin Lee, Gunok Jung
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Patent number: 8436669Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.Type: GrantFiled: April 27, 2011Date of Patent: May 7, 2013Assignee: NVIDIA CorporationInventors: Jonah M. Alben, William J. Dally
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Patent number: 8436668Abstract: A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value. A transfer circuit is coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level. The transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit.Type: GrantFiled: January 4, 2011Date of Patent: May 7, 2013Assignee: Oracle International CorporationInventors: Robert P. Masleid, Jason M. Hart
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Patent number: 8421503Abstract: A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit.Type: GrantFiled: March 2, 2010Date of Patent: April 16, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Taiki Uemura, Yoshiharu Tosaka
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Patent number: 8421499Abstract: In an embodiment, an integrated circuit includes a power gated block and a power manager circuit. The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block. The power manager may generate the select signal responsive to various parameters that affect the speed of the integrated circuit, such as power supply voltage magnitude, operating temperature, and/or process corner. The power gated block may control the rate at which power switches are enabled based on the select signal or signals. For example, the power switches may be enabled in a more parallel or more serial fashion and/or the drive strength of block enable buffering to the power switches may be varied. In another embodiment, the power manager circuit may assert multiple block enables to the power gated block (which are connected to separate sets of power switches), and may control the timing of assertion of the enables to control the rate at which power switches are enabled.Type: GrantFiled: February 15, 2010Date of Patent: April 16, 2013Assignee: Apple Inc.Inventors: Toshinari Takayanagi, Shingo Suzuki, Jung-Cheng Yeh, Conrad H. Ziesler
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Patent number: 8406080Abstract: A semiconductor memory device using system clock with a high frequency can maintain a constant operation margin even in the change of operation environments including voltage level, temperature, and process. The semiconductor memory device includes an output control signal generator configured to be responsive to a read pulse that is activated in response to a read command, to generate an odd number of first output source signals corresponding to a rising edge of a system clock and a even number of second output source signals corresponding to a falling edge of the system clock, and an output enable signal generator configured to generate a first rising enable signal and a falling enable signal on the basis of the first output source signal and generate a second rising enable signal on the basis of the second output source signal, according to column address strobe (CAS) latencies, the first rising enable signal being activated earlier than the second rising enable signal by a half cycle of the system clock.Type: GrantFiled: November 5, 2010Date of Patent: March 26, 2013Assignee: Hynix Semiconductor Inc.Inventor: Hee-Jin Byun
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Patent number: 8405441Abstract: A latch circuit includes an output driver electrically coupled with a circuit. The circuit is electrically coupled with the output driver through a first path and a second path. The circuit is configured to receive a data signal. The circuit is configured to divert a signal of the output driver through the first path at a falling edge of the data signal. The circuit is configured to divert the signal of the output driver through the second path at a rising edge of the data signal.Type: GrantFiled: March 24, 2011Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Kuo Su, Yi-Tzu Chen, Chung-Cheng Chou
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Patent number: 8378728Abstract: A level shifting flip-flop for generating a level-shifted output signal based on an input signal includes a master stage and a slave stage. The slave stage has an integrated level shifting circuit. The slave stage level shifts a signal as it passes through the flip-flop, which eliminates the need of level shifting the signal after it is output from the flip-flop.Type: GrantFiled: June 3, 2012Date of Patent: February 19, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Gaurav Goyal, Abhishek Mahajan, Bipin B. Malhan
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Patent number: 8373442Abstract: A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.Type: GrantFiled: September 21, 2011Date of Patent: February 12, 2013Assignee: Fujitsu LimitedInventor: Tomohiro Tanaka
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Patent number: 8362805Abstract: In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.Type: GrantFiled: February 15, 2010Date of Patent: January 29, 2013Assignee: Apple Inc.Inventors: Shingo Suzuki, Vincent R. von Kaenel, Toshinari Takayanagi, Conrad H. Ziesler, Daniel C. Murray
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Patent number: 8362806Abstract: Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.Type: GrantFiled: June 26, 2009Date of Patent: January 29, 2013Assignee: Intel CorporationInventors: Sapumal B. Wijeratne, Clifford L. Ong, Hans J. Greub, Anandraj Devarajan
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Patent number: 8358152Abstract: An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.Type: GrantFiled: April 29, 2011Date of Patent: January 22, 2013Assignee: Apple Inc.Inventor: Edward M. McCombs
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Publication number: 20130002297Abstract: A Bias Temperature Instability- (BTI-) resistance circuit is arranged to propagate a received clock signal through a clock tree. The state of the clock signal is inverted at a midpoint of the clock tree that is about the halfway point of the path of the propagated clock signal through the clock tree. The inversion of the clock signal at the midpoint mitigates BTI-aging effects of the BTI-resistant circuit when the clock signal is blocked by a clock gating signal, for example. The clock tree can be used to latch a data signal at an input latch of a logic block using the received clock signal, and to latch a data signal at an output latch of a logic block using a propagated clock signal that is output from the endpoint of the clock tree.Type: ApplicationFiled: June 8, 2012Publication date: January 3, 2013Applicant: TEXAS INSTRUMENTS, INCORPORATEDInventors: Palkesh Jain, Francisco Adolfo Cano
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Patent number: 8330487Abstract: The semiconductor device may include, but is not limited to, a first switching circuit, a second switching circuit, and a control circuit. The first switching circuit switches between first and second states. The second switching circuit switches between the first and second states. The second switching circuit reduces a first power impedance across the first switching circuit. The control circuit is coupled to the first and second switching circuits. The control circuit keeps the first switching circuit in the first state. The control circuit switches the second switching circuit from the second state to the first state.Type: GrantFiled: September 9, 2009Date of Patent: December 11, 2012Assignee: Elpida Memory, Inc.Inventor: Hiromasa Noda
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Patent number: 8314634Abstract: Techniques are provided to reduce glitches at an output signal node when a device is switched to and from a low power operation mode. In one example, a method of operating a device includes providing power to operate a signal source of the device during a normal operation mode of the device. The method also includes passing an output signal from the signal source through a signal path to an output node during the normal operation mode. The method also includes receiving an operation mode signal to switch the device from the normal operation mode to a low power operation mode. The method also includes disabling the signal path to prevent glitches from appearing at the output node during the switch from the normal operation mode to the low power operation mode. The method also includes continuing providing power to the signal source until after the signal path is disabled.Type: GrantFiled: April 4, 2011Date of Patent: November 20, 2012Assignee: Lattice Semiconductor CorporationInventors: Barry Britton, Richard Booth, Yang Xu, Tawei David Li
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Patent number: 8305112Abstract: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.Type: GrantFiled: July 30, 2010Date of Patent: November 6, 2012Assignee: Intel CorporationInventors: Hon Shing Lau, Scott Siers, Ruchira Liyanage
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Patent number: 8294491Abstract: A high speed flip-flop circuit and a configuration method thereof are provided. A small number of transistors may be used to configure a flip-flop circuit, so that the flip-flop circuit may be operated at a high-speed. Additionally, an area occupied by the flip-flop circuit may be reduced, and power consumption may be reduced. Accordingly, the flip-flop circuit may be integrated together with a microwave frequency integrated circuit using a Gallium Arsenide (GaAs) compound semiconductor process.Type: GrantFiled: October 28, 2010Date of Patent: October 23, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: In Kwon Ju, In Bok Yom
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Publication number: 20120249181Abstract: A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit.Type: ApplicationFiled: June 12, 2012Publication date: October 4, 2012Inventor: Katsunao KANARI
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Patent number: 8258815Abstract: The present invention relates to a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V1, a first current generator to generate a first mirror current during a first half cycle based on the reference current, a first capacitor including a first end, and a first transistor having a first threshold voltage VTH1. The first transistor includes a gate to receive the first voltage V1, a drain coupled to the first current generator and a source coupled to the first end of the first capacitor so as to allow the first mirror current to charge the first capacitor during the first half cycle, wherein the period of the first half cycle is a function of the first bias voltage V1 minus the first threshold voltage VTH1.Type: GrantFiled: March 3, 2010Date of Patent: September 4, 2012Assignee: Macronix International Co., Ltd.Inventors: Chia Ching Li, Hsin Yi Ho, Chun Hsiung Hung
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Patent number: 8258814Abstract: A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit.Type: GrantFiled: June 28, 2011Date of Patent: September 4, 2012Assignee: Renesas Electronics CorporationInventor: Toshiaki Nakahashi
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Patent number: 8188761Abstract: A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and to the observing circuit. For the latch, the clocking defines a window in time during which the latch is prevented from receiving data, and in a synchronized manner the clocking is enabling a response in the observing circuit. The clocking is synchronized in such a manner that the circuit is enabled for its response only inside the window when the latch is prevented from receiving data. The system may also have additional circuits that are respectively coupled to latches, with each the additional circuit and its respective latch receiving the synchronized clocking Responses of a plurality of circuits may be coupled in a configuration corresponding to a logical OR.Type: GrantFiled: February 14, 2011Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Bruce M. Fleischer, Michael K. Gschwind
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Patent number: 8188765Abstract: Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time.Type: GrantFiled: September 15, 2010Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Michael R. Ouellette, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone