Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.

Abstract: A current sensing line fault detector includes a unity gain buffer coupling a reference voltage to an IC pin, a current controlled current source coupled to the buffer, a current mode A/D converter developing a digital signal representative of the IC pin current, and logic for determining the state of a transmission line coupled to the IC pin. An alternative current sensing line fault detector includes an OPAMP having a first input coupled to an input node and to a reference current source and having a second input coupled to a reference voltage source. A voltage controlled current source (VCCS) is coupled between the first input of the OPAMP and ground and is controlled by an output of the OPAMP. An A/D converter is coupled to the output of the OPAMP to develop a digital output signal representative of the current flowing through the current sensor.

Abstract: Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

Abstract: An optical sensor of the present invention changes a light-emitting period of a light-emitting element and a period of a reference clock that is used by a time difference extracting circuit, depending on whether or not a digital value that is output from a first digital calculating portion exceeds a reference value in a determination period. With this, there is achieved an optical sensor capable of maintaining both of measurement accuracy at short distance and measurement accuracy at long distance when a housing panel is present between the optical sensor and a detection target.

Abstract: A blood oxygen detection chip with a capability of fast tracking light intensity. A photocurrent buffer receives light and generates an output photocurrent iph that is not affected by a leakage current as much as possible, a bandgap voltage reference and a linear voltage regulator are mainly used to obtain an accurate adjustable reference voltage Vref, an integrator integrates the photocurrent iph to obtain a voltage signal in a linear relation with a photocurrent value, a pulse generator converts the voltage signal to a frequency signal, and finally an output buffer performs wave shaping to obtain a final output frequency signal Freq in a linear relation with a light intensity value.

Abstract: A first transistor (2a), a second transistor (2b), a third transistor (2c) and a fourth transistor (2d) are provided. A first transistor (2a) amplifies a first I signal VIP inputted from a first input terminal (1a). A second transistor (2b) amplifies a first Q signal VQP inputted from a second input terminal (1b). A third transistor (2c) amplifies a second I signal VIN when the second I signal VIN is inputted from a third input terminal (1c), the second I signal VIN forming a differential signal with the first I signal VIP. A fourth transistor (2d) amplifies a second Q signal VQN when the second Q signal VQN is inputted from a fourth input terminal (1d), the second Q signal VQN forming a differential signal with the first Q signal VQP.

Abstract: A voltage monitoring framework is proposed to predict, report, and correct actions for performance impacting voltage droop due to power supplies in a system-on-a-chip. Both the amplitude and duration of the voltage droop are monitored. By predicting serious voltage droops early, power supplies cross check against each other to avoid catastrophic error, thus ensuring that integrated circuits making up the system-on-a-chip will maintain functional reliability.

Abstract: Automated power conversion device operation and status data is received in a local terminal device. The operation and status data is forwarded from the local device to a remote device via a communications network. The remote device receives the operation and status data, and compares the received automated power conversion device operation and status data with automated power conversion device history data stored in a memory. Based on the comparing, the remote device generates a service recommendation for the automated power conversion device, Based on the generating, the remote device transmits the service recommendation to the local device via the communications network. The service recommendation is received in the local device. The local device displays the received service recommendation in to the user of the local device.

Abstract: A coherent optical receiver in which the channel equalizer and the clock-recovery circuit are connected in a nested-loop configuration, wherein the channel estimate generated by the equalizer is used to adjust the phase of the clock signal generated by the clock-recovery circuit. The channel equalizer can be implemented using a bank of time-domain or frequency-domain FIR filters. In an example embodiment, the clock-recovery circuit is configured to track the phase rotation corresponding to the equalized signals in a frequency-dependent manner; track the phase rotation in the channel equalizer either in a frequency-dependent manner or based on the mean signal delay therein; and adjust the phase of the clock signal based on an effective difference between these two phase rotations. The clock-recovery circuit enhances the clock tone by applying a Fourier transform to the squared absolute values of the equalized signals outputted by the channel equalizer.

Abstract: Apparatuses and Methods for dynamic adjustment of operating conditions of integrated circuits are provided. The method includes receiving, from a voltage reference module, an operating voltage of the integrated circuit, receiving a reference clock to be used as an operating frequency of the integrated circuit and is distributed to by the plurality of circuit blocks in the integrated circuit, measuring feedback path timing information of one or more circuit blocks in the plurality of circuit blocks, comparing the feedback path timing information of the one or more circuit blocks to the reference clock, determining timing margins of corresponding one or more feedback paths of the one or more circuit blocks based on the comparison, and generating a feedback for adjusting the operating voltage or the operating frequency of the integrated circuit based on the timing margins of the one or more feedback paths of the one or more circuit blocks.

Abstract: An example circuit includes: an inverter-based filter; a voltage regulator having an input and an output, the output of the voltage regulator providing a supply voltage to bias the inverter-based filter; a ring oscillator having a supply input and an output, the supply input of the ring oscillator coupled to the output of the voltage regulator; a control circuit coupled to the output of the ring oscillator and the input of the voltage regulator, the control circuit configured detect an oscillation frequency of the ring oscillator and to adjust the voltage regulator in response to the oscillator frequency.

Abstract: A power module including first and second switching elements connected in a half-bridge configuration, an integrated circuit including high-side and low-side circuits that respectively drive the first and second switching elements, high-side and low-side programmable circuits that are respectively configured to implement first and second logic functions or parameters to be used by the high-side and low-side circuits. The integrated circuit includes a write port that receives data to be written to the high-side and low-side programmable circuits, internal wiring that connects the high-side and low-side programmable circuits in a daisy chain configuration, and a level shifter that is provided in the internal wiring connecting the low-side programmable circuit to the high-side programmable circuit, and that connects a low-side signal system and a high-side signal system.

Abstract: A small-sized frequency-variable terahertz oscillator has a successive and large frequency-sweeping width even at a room temperature. The frequency-variable terahertz oscillator includes a slot antenna, a resonant tunneling diode and a varactor diode arranged parallel to each other along the slot antenna. The frequency-variable terahertz oscillator oscillates in a terahertz frequency range when the resonant tunneling diode and the varactor diode are separately applied with a direct voltage.

Abstract: In one embodiment, an apparatus includes a clock control circuit to generate a clock signal for communication on an interconnect. The clock control circuit may be configured to receive an indication of a next device of a plurality of devices to be accessed and to dynamically update a control signal to cause the communication of the clock signal to be dynamically switched between a fixed clock frequency and a spread spectrum clock frequency based at least in part on the indication of communication to the next device. Other embodiments are described and claimed.

Abstract: A lock time measurement system to determine a lock time includes a measurement device, a serializer-deserializer (SERDES), a pattern generator, and a splitter. In a first mode, the SERDES receives first data from the pattern generator by way of the splitter. A receiver of the SERDES outputs a recovered clock signal based on the first data to a transmitter. The transmitter includes a serializer and a multiplexer. The serializer receives the recovered clock signal by way of the multiplexer and modifies second data based on the recovered clock signal and outputs serial data. A measurement device, connected to the transmitter and the splitter determines the lock time. In a second mode, the SERDES functions as a transmitter for transmitting data and a receiver for receiving data in a communication link. The system has a better accuracy and utilizes existing receiver and driver circuits.

Abstract: An adaptive demapper adaptively demaps an input symbol. An input symbol is received and demapped in a hard-output demapper to generate a current detected symbol corresponding to a constellation point on a current constellation closest to the input symbol. A corrected inverse of a current noise power estimate is determined by updating a previous noise power estimate based on a difference between the input symbol and the current detected symbol. In a soft-output demapper, a log likelihood ratio corresponding to the current detected symbol is determined based on the corrected inverse of the current noise power estimate. The constellation point in the current constellation corresponding to the current detected symbol is then updated to generate an updated constellation based on a difference between the constellation point and the received input symbol.

Abstract: A relaxation oscillator circuit includes a current mirror configured to receive the input current from the and generate a plurality of starved currents, a Schmitt trigger configured to be current starved by a first starved current of the plurality of starved currents and a plurality of inverters configured to receive a Schmitt trigger output signal and generate an output clock signal, the inverters including a plurality of current starved inverters that are current starved by a second starved current of the plurality of starved currents, the plurality of current starved inverters receiving the Schmitt trigger output signal and generating a first inverter output signal, upon which an output clock signal is based. The relaxation includes a capacitor configured to charge or discharge in response to the output clock signal and a switching module configured to provide current from the current source based on the output clock signal.

Abstract: A voltage comparing circuit comprising: a comparator,; a time interval computing unit; a switch module,; a first current source, comprising a first charging terminal; a first capacitor, coupled to the first current source at the first charging terminal; and a capacitance adjusting unit, coupled to the first capacitor. In a first calibration mode, the first comparing terminal receives a reference voltage.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for dynamic strobe timing. A controller is configured to generate a strobe signal to facilitate data transfer. A controller is configured to receive a feedback signal in response to initiation of a strobe signal. A controller is configured to control a duration of a strobe signal based on a feedback signal.

Abstract: A process for automated contact wetting in a sensor circuit includes generating a first current through a contact by sequencing a first circuit on, the first current exceeding a wetting threshold of the contact, and reducing current through the contact to a second current by sequencing a second circuit on, the second current being below the wetting threshold.

Abstract: Aspects include a power supply system. The system includes an oscillator system configured to generate a clock signal at a clock node. The oscillator system includes a comparator configured to compare a first variable voltage at a first comparator node and a second variable voltage at a second comparator node. The first and second variable voltages can have respective magnitudes that are based on a state of the clock signal. The system also includes a pulse-width modulation (PWM) generator configured to generate a PWM signal based on an error voltage and the clock signal. The system further includes a power stage configured to generate an output voltage based on the PWM signal.

Abstract: An oscillator includes: an oscillation circuit whose oscillation frequency changes based on a voltage that is applied to a variable capacitance element; and a voltage generation unit that generates the voltage which is applied to the variable capacitance element based on a control signal, in which the voltage that is generated by the voltage generation unit changes nonlinearly with respect to a change in the control signal such that a change in the oscillation frequency with respect to the change in the control signal is adjusted to come close to be linear.

Abstract: An integrated temperature sensor device has a temperature sensor configured to provide an analog signal corresponding to an ambient temperature, an analog-to-digital converter receiving the analog signal and a programmable digital filter coupled to the analog-to-digital converter.

Abstract: A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

Abstract: A method for regulating an output voltage of a converter is provided in which a switching frequency of a switching device is limited in response to a signal that is representative of a magnitude of a current from an input of the converter and to a sense signal generated in response to an input voltage signal.

Abstract: Electric-power management system, an area controller transmits, to each of section controllers, information about a target voltage and information about the present voltage, each of the section controllers calculating a difference between the target voltage and the present voltage, received from the area controller, and calculating a power's demand-supply-adjustment request amount based on difference between the information about the voltages, each of facility-equipment controllers transmitting power-reception/power-release capable equipment information to each section controller, being information about a power-reception/power-release capable equipment in a facility into which the facility-equipment controller is installed, the section controller, based on the power-reception/power-release capable equipment information about the equipment, transmitting the equipment's demand-supply-adjustment request amount and the facility-equipment controller transmitting a control signal to the equipment based on the equi

Abstract: In accordance with an embodiment, a method for controlling a circuit includes controlling pulse width modulation on a primary side of a quasi-resonant controller to achieve continuous current mode operation from a synchronous rectification controller on a secondary side.

Abstract: A apparatus including a clock source and a comparison circuit is presented. The clock source may be configured to generate a clock signal. The comparison circuit may be configured select a first frequency of the clock signal and to receive a plurality of voltage signal inputs for comparison. The comparison circuit may be further configured to compare a voltage level of a first voltage signal input of the plurality of voltage signal inputs to a voltage level of a second voltage signal input of the plurality of voltage signal inputs responsive to an active edge of the clock signal. The comparison circuit may also be configured to determine a comparison value corresponding to the comparison of the voltage levels and to select a second frequency of the clock signal dependent upon the comparison value, in which the second frequency is different than the first frequency.

Abstract: A method for operating a charge pump that supplies switching current for a plurality of transistors includes a capacitor generating a pumped voltage. A comparator generates a pump control signal for turning on and off charging of the pump capacitor based on a difference between a comparison voltage and a reference voltage. A direct voltage sensor receives a feedback signal reflecting the pumped voltage and generates the comparison voltage in response to the feedback signal. The sensor includes a sensor resistor, a current source configured to drive a sensor current through the sensor resistor, and a differential op-amp that drives the sensor current to cause the voltage drop across the sensor resistor to remain constant as the pumped voltage experiences the voltage drop. The charge pump may include two similar direct voltage sensor controlling positive and negative pumped voltages.

Abstract: A strobe lighting unit including a detecting circuit can reliably detect degradations of a xenon light source, which can flash as a light source for devices having a shooting with camera such as a smart phone, etc. The strobe lighting unit can include at least one xenon discharge tube as the xenon light source and at least one lighting circuit to flash the xenon discharge tube. The strobe lighting unit can also include at least one light-detecting circuit to detect degradations of the xenon discharge tube without a photo detector by monitoring an anode electrode of the xenon discharge tube at a flash thereof, and can be configured to output the monitoring result into the devices. Thus, the strobe lighting unit can result in an increase in the possible range of the devices, and can be employed for various devices including a thin mobile phone, a thin smart phone, etc.

Abstract: A multi-input voltage-to-frequency conversion circuit, includes: a multi-input operational amplifier amplifying one of multiple voltage signals in response to multiple control signals to generate an amplified voltage; a voltage-to-current converter converting the amplified voltage into a sensed current, and generating an oscillation current based on the sensed current and on an offset voltage that is associated with a predetermined frequency range corresponding to the one of the voltage signals; and a current-controlled oscillator generating, based on the oscillation current, a periodic pulse signal that has a frequency linearly proportional to the magnitude of the one of the voltage signals.

Abstract: A semiconductor device includes a reference current generator suitable for generating a reference current, a current-voltage converter suitable for generating a first reference voltage and a second reference voltage in response to the reference current, and an analog-digital converter suitable for generating a digital code value based on a voltage difference between the first and second reference voltages, wherein the reference current generator includes a current control unit for controlling the reference current in response to the digital code value.

Abstract: A multi-input voltage-to-frequency conversion circuit includes: a multi-input operational amplifier amplifying one of multiple voltage signals in response to multiple control signals to generate an amplified voltage; a voltage-to-current converter converting the amplified voltage into a sensed current, and generating an oscillation current based on the sensed current and on an offset voltage that is associated with a predetermined frequency range corresponding to the one of the voltage signals; and a current-controlled oscillator generating, based on the oscillation current, a periodic pulse signal that has a frequency linearly proportional to the magnitude of the one of the voltage signals.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: An electrical to audible signal measurement apparatus comprises an absolute value converter, a voltage to frequency converter, a polarity detector, and a waveform changer. The absolute value converter is capable of converting a bipolar input signal into a unipolar signal. The voltage to frequency converter is connected to the absolute value converter and is capable of generating a frequency signal proportional to the unipolar signal. The polarity detector is capable of identifying a polarity of the bipolar input signal to form an identified polarity. The waveform changer is connected to the voltage to frequency converter and polarity detector and is capable of generating a number of different waveforms in an audio frequency range in response to receiving the frequency signal from the voltage to frequency converter and in response to the identified polarity.

Abstract: A frequency-voltage converting circuit 13 is composed of a switch unit including switches SW1 and SW2, electrostatic capacitive elements C and C10 to C13, and switches CSW0 to CSW3. The electrostatic capacitive elements C10 to C13 are composed of elements having mutually different absolute values of capacitance and are provided so as to cover a frequency range intended by a designer. The electrostatic capacitance values are weighted by, for example, 2. The electrostatic capacitive elements C11 to C13 are selected by, for example, the switches CSW0 to CSW3 based on 4-bit frequency adjustment control signals SELC0 to SELC3, thereby carrying out frequency switching.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A capacitance to frequency converter includes a switching capacitor circuit, a charge dissipation circuit, a comparator, and a signal generator. The switching capacitor circuit charges a sensing capacitor and transfers charge from the sensing capacitor to a circuit node of the charge dissipation circuit. The comparator is coupled to the charge dissipation circuit to compare a potential at the circuit node to a reference voltage. The signal generator is coupled to an output of the comparator and to the charge dissipation circuit. The signal generator is responsive to the output of the comparator to generate a signal fed back to control the charge dissipation circuit. A frequency of the signal is proportional to a capacitance of the sensing capacitor.

Abstract: The present document relates to a method and system for determining the voltage level of an input signal compared to a reference voltage, providing a plurality of level indications regarding an input voltage with respect to a reference voltage. The multi-level comparator comprises an input stage converting the input voltage into a first current and converting the reference voltage into a second current; and a plurality of comparator stages, each comprising a first current amplification unit amplifying the first current with a first gain, a second current amplification unit amplifying the second current with a second gain, and an output port providing an indication whether the first comparator current is smaller or larger than the second comparator current; wherein respective ratios of the first gain and the second gain of the plurality of comparator stages are different.

Abstract: Techniques are disclosed relating to radio frequency (RF) power detection. In one embodiment, a power detection unit is disclosed that includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The first multiplier is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. In some embodiments, sources of the first transistor pair are coupled to sources of the second transistor pair, and the sources of the second transistor pair are coupled together. In some embodiments, the power detection unit is configured to compensate for mismatched transistors by applying offset voltages to bodies of transistors in the first and second transistor pairs.

Abstract: A control circuit for a sensing electrode array is described. The control circuit for the sensing electrode array includes a down-conversion circuit, an intensity-to-phase frequency converter, and a phase frequency analyzing unit. The down-conversion circuit down-converts a sensing signal of each sensing line of the sensing electrode array to obtain a corresponding down-converted signal. Each down-converted signal is substantially a direct-current signal. The intensity-to-phase frequency converter generates a corresponding phase frequency signal for each down-converted signal. At least the phase or the frequency of the phase frequency signal is related to the level of the corresponding down-converted signal. The phase frequency analyzing unit obtains signal magnitude of the corresponding sensing lines based on the phase frequency signal.

Abstract: A control circuit for a sensing electrode array is described. The control circuit for the sensing electrode array includes a signal intensity analyzer, an intensity-to-phase frequency converter, and a phase frequency analyzing unit. The signal intensity analyzer obtains an intensity signal corresponding to a sensing signal of each sensing line of the sensing electrode array, wherein each intensity signal is a direct-current signal. The intensity-to-phase frequency converter generates a phase frequency signal based on the intensity signal. At least the phase or the frequency of the phase frequency signal is related to the level of the corresponding intensity signal. The phase frequency analyzing unit obtains a signal magnitude of the corresponding sensing line according to each phase frequency signal. The control circuit for the sensing electrode array enhances the operating speed and the signal-to-noise ratio of the touch control sensing system without increasing the manufacturing cost.

Abstract: A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material formed on the terminal electrodes, and a control gate formed on the second insulating material. The channels have different polarity and a charge storage layer is formed inside the second insulating material. The control gate is applied with a forward bias or a reverse bias and then the bias is cut off. The voltage-current characteristics of the semiconductor device are changed according to an electrical charge created in the charge storage layer.

Abstract: An apparatus comprising an analog-to-digital converter (ADC); a frequency-domain equalizer (FDEQ); a time-domain interpolator positioned between the ADC and the FDEQ, wherein the time domain interpolator is coupled to the ADC and the FDEQ and configured to perform a time-domain interpolation to compensate a signal sample for a plurality of ADC induced changes.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A capacitance to frequency converter includes a switching capacitor circuit, a charge dissipation circuit, a comparator, and a signal generator. The switching capacitor circuit charges a sensing capacitor and transfers charge from the sensing capacitor to a circuit node of the charge dissipation circuit. The comparator is coupled to the charge dissipation circuit to compare a potential at the circuit node to a reference voltage. The signal generator is coupled to an output of the comparator and to the charge dissipation circuit. The signal generator is responsive to the output of the comparator to generate a signal fed back to control the charge dissipation circuit. A frequency of the signal is proportional to a capacitance of the sensing capacitor.

Abstract: An analog-to-digital converter (ADC) suitable for measuring on-die DC or low frequency analog voltages may include a ring oscillator having a group of circuit cells successively and circularly coupled. Under certain circumstances, the ring oscillator may produce an output frequency that corresponds substantially linear to the input voltage. Other embodiments may be disclosed or claimed.

Abstract: A voltage droop monitoring and correcting circuit for a microprocessor includes: a monitor circuit configured to monitor voltage droops of the microprocessor and perform a temporary clock-skipping technique to compensate for the voltage droops. A method for monitoring and correcting voltage droops of a microprocessor includes: monitoring voltage droops of the microprocessor; and performing a temporary clock-skipping technique to compensate for the voltage droops. A computer system includes memory; a processor operatively connected to the memory; and computer-readable instructions stored in the memory for causing the processor to: monitor voltage droops of the microprocessor; and perform a temporary clock-skipping technique to compensate for the voltage droops.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A semiconductor apparatus includes a signal source 7 that outputs a signal of predetermined frequency, a frequency divider 15 that receives the output signal of the signal source and is capable of switching the output signal to two or more frequency division ratios, a delta-sigma modulator 16 that controls the frequency division ratio of the frequency divider, and a bandpass filter 17 that receives an output of the frequency divider. The frequency of the input signal of the frequency divider is divided by the frequency division ratio controlled by the delta-sigma modulator, and quantization noise appearing in the output of the frequency divider generated by the delta-sigma modulator is attenuated with the bandpass filter. The semiconductor apparatus easily can convert a signal output by a single signal source to a signal of predetermined frequency and supply a plurality of signals of predetermined frequency using a simple configuration with reduced chip size.