Abstract: A trigonometric function calculating device includes: an address generator that generates an address signal that is formed from plural bit strings and corresponds to a phase; a trigonometric function table that stores first sines and first cosines that respectively correspond to phases expressed by upper bits of the address signals, and second sines and a second cosines that respectively correspond to phases expressed by lower bits of the address signals; a calculation circuit that outputs, as a calculated value, a sine that corresponds to the address signal by calculating processing using the first sine, the first cosine, the second sine and the second cosine that correspond to the address signal and have been extracted by referring to the trigonometric function table; and a correcting section that corrects the calculated value on the basis of a correction value corresponding to the address signal.

Abstract: A time-interleaved digital-to-analog converter (DAC) includes a digital processing circuit, a time-domain dynamic element matching (TDEM) circuit, a plurality of DACs, and a combining circuit. The digital processing circuit generates data sequences according to the digital signal. The data sequences include a first data sequence and a second data sequence. The TDEM circuit swaps a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. The DACs include a first DAC and a second DAC. The first DAC has a first DAC cell that operates in response to the first adjusted data sequence. The second DAC has a second DAC cell that operates in response to the second adjusted data sequence. The combining circuit generates the analog signal by combining analog outputs of the DACs.

Abstract: A device includes a plurality of phase accumulators, a multiplexer, and an oscillator. The plurality of phase accumulators is configured to receive a plurality of frequencies and generate a plurality of ramp signals. The multiplexer is configured to receive the plurality of ramp signals from the plurality of phase accumulators and to select one ramp signal from the plurality of ramp signals. The oscillator is configured to receive the one selected ramp signal and to generate one amplitude signal associated therewith. The plurality of phase accumulators continues generating their respective ramp signal. The multiplexer subsequent to selecting the one ramp signal is configured to select another ramp signal associated with another one phase accumulator of the plurality of phase accumulators. The oscillator is further configured to receive the selected another ramp signal and to generate another amplitude signal associated therewith.

Abstract: A ranging code correlation function detection system for use in a global navigation satellite system (GNSS) receiver includes a correlation block to correlate a digitized GNSS signal (e.g. at or above a critical sampling rate) with a corresponding ranging code at each of a plurality of different offsets from a current estimate of a code delay to generate a plurality of correlation data points; an interpolation filter configured to generate at least one estimated correlation data point that lies between two of the correlation data points based on the current estimate of the code delay. In some cases the ranging code correlation function detection system may also include a discriminator block configured to generate an updated estimate of the code delay based on the at least one estimated correlation data point.

Abstract: A memory optimization method includes identifying, within a circuit design, a memory having an arithmetic operator at an output side and/or an input side of the memory. The memory may include a read-only memory (ROM). In some examples, an input of the arithmetic operator includes a constant value. In some embodiments, the memory optimization method further includes absorbing a function of the arithmetic operator into the memory. By way of example, the absorbing the function includes modifying contents of the memory based on the function of the arithmetic operator to provide an updated memory and removing the arithmetic operator from the circuit design.

Abstract: An accumulation-mode MOS varactor is formed with a standard CMOS process and having an anti-symmetric-CV curve. The asymmetric varactor (ASVAR) can efficiently generate even-order harmonics while simultaneously suppressing odd-order harmonics over broad bandwidths. This is achieved without degradation of dynamic cut-off frequency. The improved cut-off frequency of the asymmetric varactor results in efficient even-harmonic generation well into sub-millimeter or terahertz frequencies. This and the inherent adaptive-CV features of the asymmetric varactor result in even-harmonic generation with process variation resilience and can also be utilized for frequency response shaping and for optimizing performance at various driving conditions.

Abstract: A variable delay circuit, which includes a digital-to-time converter (DTC) circuit and a controller, is disclosed. The DTC circuit includes a plurality of capacitors and a plurality of MOS switches that are turned on and off according to a control code. The DTC circuit receives an input pulse, applies a delay corresponding to the control code to the edge to be delayed, and outputs a delay pulse. The controller supplies a valid code indicating a delay amount as a control code during a period beginning from a predetermined time TCONST before the edge (positive edge) to be delayed of an input pulse REF up to the edge to be delayed. Further, the controller supplies, as the control code, a dummy code for turning on all of the plurality of MOS switches inside the DTC circuit immediately before the period.

Abstract: A frequency synthesis system includes a memory to store first and second digital control word pairs that each include a first and second control word. A first DAC system generates an analog sampling signal having a first sampling frequency based on a fixed clock signal and the first control word of the first pair during a first time duration having a second sampling frequency based on the first control word of the second pair during a second time duration. A second DAC system generates an analog output signal based on the second control word of the first pair and the first sampling frequency at the first time duration and based on the second control word of the second pair and the second sampling frequency at the second time duration. The analog output signal has a same predetermined output frequency at both the first and second time durations.

Abstract: A bandwidth allocation and monitoring method may divide available bandwidth on a shared communication medium into a plurality of discrete tones that can be individually allocated to modems on an as-needed basis. The effective modulation rate that a particular modem can use for each discrete tone can be monitored over time using a schedule of pilot tones transmitted from the modems on different tones at different times. The schedule may define representative pilot tones, in which case effective modulation rates for neighboring tones may be inferred from a determined effective modulation rate of a pilot tone.

Abstract: A system for beamforming, in a phased array antenna. Subtraction of a sinusoidal signal from a received signal, or from a signal to be transmitted, is used to shift the phase of the received signal, or from a signal to be transmitted. A separate sinusoidal signal may be generated for each antenna array element, making it possible to shift the phase on a per-element basis, to perform beamforming.

Abstract: A time-interleaved digital-to-analog converter (DAC) uses M DAC cores to convert a digital input signal whose digital input words are spread to different DAC cores to produce a final analog outputs. The M DAC cores, operating in a time-interleaved fashion, can increase the sampling rate several times compared to the sampling rate of just one DAC. However, sequential time-interleaving DAC cores often exhibit undesirable spurs at the output. To spread those spurs to the noise floor, the time-interleaving DAC cores can be selected at a pseudo randomized manner or in a specific manner which can break up the sequential or periodic manner of selecting the DAC cores.

Abstract: A phase locked loop may be operable to generate, utilizing a frequency multiplier, a reference clock signal whose frequency is an integer M times a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.

Abstract: An amplification circuit includes: an input stage including a driver; a transformer that includes a primary winding and a secondary winding, the primary winding being coupled to an output of the driver; and an output stage including: an output configured to be coupled to a load; and a plurality of paths coupled to the output and coupled to respective taps of the secondary winding; where at least one of the plurality of paths comprises a power amplifier.

Abstract: A method of compensating for integral nonlinear interpolation (INL) distortion in a clock synthesizer driven by a system clock running at a frequency fsys, involves introducing a selected nominal analog delay I*dt with an actual delay of I*dt+? at the output of the a first path with a digital controlled oscillator (DCO) and a digital-to-time converter (DTC) and a nominal digital delay I*D with an actual delay of I*D+? at the input of a second path with a DCO and a DTC that offsets the actual analog delay in the first path, adjusting the contents x(k) of a compensation module in the second path to align the output pulses of the first and second paths for different values of k, where k represents an interpolation point, iteratively repeating the two preceding steps for all N values of I, and averaging the contents x(k) of the compensation module to derive the compensation values to be applied to a one of the DTCs to correct for INL distortion.

Abstract: Provided is an apparatus for processing a video. The apparatus for processing a video includes an image receiving module that is configured to receive encoded data, a filtering module that is configured to filter an image frame reconstructed from the encoded image, a block dividing module to divide the filtered image frame into a predetermined block dividing unit, a compression module to compress each of the plurality of blocks, to package the compressed plurality of blocks into a predetermined packaging unit, and to generate lookup table information corresponding to each of the packaged block, a frame buffer memory that is configured to record the packaged data, and a decompression module that is configured to obtain and decompress at least one of the packaged blocks by using the lookup table information.

Abstract: A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.

Abstract: An apparatus includes a sleep clock circuit that generates a sleep clock signal and an accurate clock circuit that, when on, generates an accurate clock signal. The apparatus is configured to enter a sleep mode, generate sleep clock measurements by measuring the sleep clock signal using the accurate clock signal during an initial sleep interval, estimate a cumulative error using the sleep clock measurements, and determine a final sleep interval using the cumulative error. A method includes determining a duration of an initial sleep interval and generating measurements of a sleep clock signal using an accurate clock signal. The measurements of the sleep clock signal correspond to sampling intervals within the initial sleep interval. A cumulative error value is generated according to the measurements, and a duration of a final sleep interval is determined according to the cumulative error value.

Abstract: An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

Abstract: A method, an apparatus, and a computer program product for inductive communication are provided in connection with providing mechanisms for detecting a remote NFC device without excessive power consumption. In one example, a communications device is equipped to monitor frequency oscillations associated with a NFC antenna using a calibrated LPO, determine that a number of occurrences of the frequency oscillations from a reference frequency is greater than a frequency deviation threshold, and perform a NFC polling procedure in response to the determination.

Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range.

Abstract: System and method for controlling power factor correction (PFC) for three-phase AC power conveyed via a three-phase AC power grid. Currents and voltages on the grid are monitored and used to generate waveform data enabling dynamic control of switching circuitry used in controlling one or more phase offsets between the currents and voltages.

Abstract: Optimal resilience to errors in packetized streaming 3-D wireframe animation is achieved by partitioning the stream into layers and applying unequal error correction coding to each layer independently to maintain the same overall bitrate. The unequal error protection scheme for each of the layers combined with error concealment at the receiver achieves graceful degradation of streamed animation at higher packet loss rates than approaches that do not account for subjective parameters such as visual smoothness.

Abstract: A numerical controlled oscillator generating an output signal with a digital clock signal having a variable frequency is disclosed. The numerical oscillator is controlled by a programmable numerical value being subject to a transfer function and comprises a comparator configured to compare an output of the transfer function with a duty cycle register to generate the output signal.

Abstract: A low power frequency synthesizer circuit for a radio transceiver, the synthesizer circuit comprising: a digital controlled oscillator configured to generate an output signal (Fo) having a frequency controlled by an input digital control word (DCW); a feedback loop connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).

Abstract: Devices and methods are provided for implementing a shared radio frequency spectrum allocation system. Access points and end user devices in an Authorized Shared Access System are allowed to access a channel of the shared radio frequency spectrum managed by an Authorized Shared Access System controller. Access points provide a communication, or frequency, channel over which similarly configured end user devices obtain access to data networks for client devices. Secure access to the allocated channel of the shared radio frequency spectrum is provided, thereby preventing rogue devices from gaining uncontrolled, or unauthorized, access to a channel of the shared radio frequency spectrum that may result in interference with other users of the channel including higher priority users. A secure synthesizer and secure encrypted tuning control words uniquely and securely control local channel usage.

Abstract: A wireless sensor with digital detector for monitoring the environment surrounding the sensor. The wireless sensor with digital detector comprises a configurable wireless transceiver with quadrature down and up converters, memory to store the real time received in phase and quadrature phase samples, a bank of phase rotators to phase rotate the received stored samples and a bank of in phase and quadrature phase constellation level slicers to detect the received bits. A control processor utilizes the received information, received signal strength and timing information to estimate and calculate various environmental parameters which can be used to activate different devices.

Abstract: A waveform acquiring unit acquires a time waveform of an electromagnetic wave. The time waveform is decomposed into wavelet expansion coefficients by wavelet transform. Influence levels of the respective wavelet expansion coefficients to a spectrum are calculated. The wavelet expansion coefficients are weighted based on at least the influence levels of the wavelet expansion coefficients to the spectrum. The weighted wavelet expansion coefficients are converted into time waveforms by inverse wavelet transform. Thus, the time waveforms that holds spectrum information needed for spectroscopic analysis and has a reduced noise is provided.

Abstract: This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise.

Abstract: A phase coherent signal generator apparatus is disclosed that has fast frequency shifting and numerous phase memory points, outputting a coherent continuous phase signal that includes fast switched multiple different frequency bursts.

Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, an apparatus includes an invertible sine shaping filter configured to receive an in-phase clock signal, a quadrature-phase clock signal, and an inversion control signal. The invertible sine-shaping filter is further configured to filter the in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals. The invertible sine-shaping filter is further configured to selectively invert one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal. The apparatus further includes a phase interpolator configured to generate an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal. The in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.

Abstract: A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms.

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract: A frequency synthesizer for generating a low noise and low jitter timebase of a reference signal generates first and second output signals a difference frequency that is low enough for use in sub-scanning is implemented with a first incrementer, having a preset increment and a preset end value E1 controlling a first fractional divider and a second incrementer having a preset increment and a present end value E2 controlling a second fractional divider, wherein each of the incrementers is clocked from the output signal of each fractional divider so that, when the end value E1, E2 is reached, an end signal is output and the incrementers are reset to a carryover value as a new starting value and the end signal is switched between the division factors of the fractional dividers so that the switching sequence of the end signal is periodic with the output signals of the fractional dividers.

Abstract: High accuracy sin-cos wave and frequency generators, and related systems and methods. In non-limiting embodiments disclosed herein, the sin-cos wave generators can provide highly accurate sin-cos values for sin-cos wave generation with low hardware costs and small lookup table requirements. The embodiments disclosed herein may include a circuit to conduct an arithmetic approximation of a sin-cos curve based on a phase input. The circuit may be in communication with a point lookup table and a correction lookup table. The tables may receive the phase input and match the phase input to main sin-cos endpoints associated with the phase, and to a correction value for the phase. These values which are selected based on the phase input, may be communicated to a converter circuit where the arithmetic functions are applied to the values resulting in a sin-cos curve value.

Abstract: A semiconductor device includes: a frequency setting information storage unit that stores sets of frequency information indicating setting of a frequency supplied by an oscillation unit and frequency identification information identifying the frequency information and outputs one of a plurality of pieces of the frequency information to the oscillation unit based on frequency identification information inputted thereinto; a speed setting information storage unit that stores speed identification information indicating a speed of the semiconductor device and frequency identification information corresponding to the speed identification information; a frequency identification information count unit that holds a value of the frequency identification information inputted into the frequency setting information storage unit; and a control unit that causes the frequency identification information count unit to increment or decrement the held value of the frequency identification information to approach a value of the

Abstract: A clock generator and generating method, and a mobile communication device using the clock generator. A clock generator comprises a first accumulator, an oscillating signal generating circuit and a frequency adjustment circuit. The oscillating signal generating circuit generates a first oscillating signal and adjusts a frequency of the first oscillating signal according to a first overflow output signal of the first accumulator. The frequency adjustment circuit generates a frequency control value according to the first oscillating signal and a reference oscillating signal. The first accumulator accumulates the frequency control value according to the first oscillating signal to generate the first overflow output signal.

Abstract: An electrical waveform generating circuit has a programmable current source-driver. A digital switched current source is coupled to the programmable current source-driver and controlled by waveforms stored in the programmable current source-driver. A plurality of MOSFETs is coupled to the programmable current source driver. A first coupled inductor is connected to the plurality of high voltage MOSFETs. A transducer is coupled to the first coupled inductor.

Abstract: An output signal is generated from a received input data stream representing a sequence of digital data values. For each group of successive data values in the sequence of data values, a respective waveform pattern is assigned in dependence of the data content of the respective group of successive data values. The output signal is generated by generating the assigned respective waveform patterns corresponding to the input data stream.

Abstract: Systems, methods, and circuits provide a digital frequency synthesizer where the output of the frequency synthesizer is a fractional factor of an input signal frequency. The digital frequency synthesizer may comprise a time to digital converter. A ramp offset signal may be added to the output of the time to digital converter. The ramp offset signal may be added to the output of a TDC until a reference dock signal reaches a value of pi. At such a point, the reference clock signal may be switched and the ramp offset signal may be restarted. As such, a frequency offset may be introduced at the input of the time to digital converter where the frequency offset may be modified by changing the slope of the ramp offset signal.

Abstract: A waveform acquiring unit acquires a time waveform of an electromagnetic wave. The time waveform is decomposed into wavelet expansion coefficients by wavelet transform. Influence levels of the respective wavelet expansion coefficients to a spectrum are calculated. The wavelet expansion coefficients are weighted based on at least the influence levels of the wavelet expansion coefficients to the spectrum. The weighted wavelet expansion coefficients are converted into time waveforms by inverse wavelet transform. Thus, the time waveforms that holds spectrum information needed for spectroscopic analysis and has a reduced noise is provided.

Abstract: An output circuit of a charge mode sensor includes a second resistor and an operational amplifier. The second resistor connects an output portion of the charge mode sensor and a ground. The operational amplifier is configured to output a detection signal that varies in accordance with an amount of charge kept in the charge mode sensor. The operational amplifier includes an inverting input portion, a non-inverting input portion, and an output portion. The inverting input portion is connected to the output portion of the charge mode sensor via a sensor cable. The non-inverting input portion is connected to a reference voltage. The output portion is connected to the inverting input portion via a first resistor.

Abstract: A phase-locked loop frequency synthesizer includes an L-state pulse width modulator configured to receive a reference frequency signal and at least one entry from a frequency table, and to output at least one N/N+1 modulus signals corresponding to the at least one entry from the frequency table. The synthesizer includes a divide by N/N+1 controllable modulus divider configured to receive the at least one N/N+1 modulus signals and to divide the output frequency signal by the at least one N/N+1 modulus signals to generate a second reference frequency signal. The synthesizer includes a phase frequency detector configured to receive the reference frequency signal and the second reference frequency signal and to generate an error signal. The synthesizer also includes a filter network configured to receive the error signal and to output a voltage; and a voltage controlled oscillator configured to receive the voltage and to generate the output frequency signal.

Abstract: A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal.

Abstract: A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q<1 (decimal). The numerator (p) and the denominator (q) are supplied to a flexible accumulator module, and a divisor is generated as a result. N is summed with a k-bit quotient to create the divisor. In a phase-locked loop (PLL), the divisor and the reference signal are used to generate a synthesized signal having a frequency equal to the synthesized frequency value.

Abstract: An apparatus and method for operating a frequency synthesizer wherein a value of an first control signal associated with a fine frequency feedback loop connected to a signal generator is monitored, and a second control signal associated with a medium or coarse frequency feedback loop connected to the signal generator is adjusted based on the monitoring. The first and second control signals are then output to control the frequency synthesizer.

Abstract: A digital waveform synthesizer (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesizer (10) which produces a synthesized output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: Clocking systems and methods are provided below that accurately clock per-pin data transfers of input/output (IO) circuits of integrated circuit devices. These multiplexer-based clock selection systems use a dedicated multiplexer to receive clock signals from multiple mixer circuits and in turn to provide a selected reference clock signal for use by an interface circuit in transferring data to other integrated circuit devices. The timing of the selected reference clock signal is synchronized with the data signals to provide optimal sampling of the data signals. The multiplexer-based clock selection system is for use in memory interfaces of high-speed signaling systems for example.

Abstract: A synthesizer includes: a synthesizer unit that outputs an oscillation signal based on a reference oscillation signal; a temperature detecting unit that detects a temperature; a time variation detecting unit that detects a time variation in frequency of the reference oscillation signal based on a result of temperature detection by the temperature detecting unit; and a control unit that adjusts a frequency of the oscillation signal outputted from the synthesizer unit based on a result of detection by the time variation detecting unit. With such a configuration, frequency compensation control is performed on a transducer having a large temperature coefficient.

Abstract: An apparatus for generating sine/cosine values of an input phase is disclosed. The apparatus includes a phase projector, an LUT-arithmetic unit, a temp sine/cosine generator and a sine/cosine value generator. The phase projector maps the input phase angle into an octant phase and determines an octant index indicating which octant the input phase angle actually locates and a flag indicating whether or not the input phase happens to be pi/4, 3*pi/4, 5*pi/4 or 7*pi/4. The LUT-arithmetic unit receives the octant phase for provision of its corresponding sine/cosine values. The temp sine/cosine generator receives the corresponding sine/cosine values of the octant phase for provision of temp sine/cosine values based on the flag. The sine/cosine value generator selectively swaps and inverts the temp sine/cosine values as the sine/cosine values of the input phase based on a swap index derived from the octant index.

Abstract: A digital broadcasting system and a method of processing data are disclosed, which are robust to error when mobile service data are transmitted. To this end, additional encoding is performed for the mobile service data, whereby it is possible to strongly cope with fast channel change while giving robustness to the mobile service data.