Abstract: Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current.

Abstract: Charging and discharging circuits for assisting charge pumps are disclosed. In certain embodiments, a radio frequency (RF) switch system includes an RF switch that receives an RF signal and is controlled by a switch control signal received at an input, a first charge pump configured to generate a first charge pump voltage, a level shifter powered by the first charge pump voltage and that generates the switch control signal based on a switch enable signal, and a charge pump assistance switch coupled to the input of the radio frequency switch and that activates to assist the first charge pump in response to a transition of the switch enable signal from a first state to a second state.

Abstract: An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.

Abstract: A power semiconductor module includes a semiconductor switching element, a gate control pattern to which a gate electrode of the semiconductor switching element is connected, a source control pattern to which a source electrode of the semiconductor switching element is connected, a capacitor to form a low-pass filter, a capacitor arrangement pattern to which one end of the capacitor is connected, and a wire. The other end of the capacitor is connected to the source control pattern. The wire electrically connects the capacitor arrangement pattern and the gate control pattern.

Abstract: A display device includes a plurality of pixels and a control circuit configured to control brightness of the plurality of pixels. Each of the plurality of pixels includes a light-emitting element and a pixel circuit configured to control light emission of the light-emitting element. The pixel circuit includes a driving transistor configured to supply electric current to the light-emitting element, and a storage capacitor configured to store voltage to control the electric current to be supplied by the driving transistor to the light-emitting element. The control circuit is configured to determine a statistic of brightness of pixels specified by one or more video frames with a predetermined method, determine a length of a threshold compensation period for which the storage capacitor applies threshold compensation to the driving transistor based on the statistic, and control the pixel circuit based on the threshold compensation period.

Abstract: A drive circuit for a switch drives an upper-arm switch and a lower-arm switch that include body diodes. Of the body diodes in upper- and lower-arm switches, the diode through which a feedback current flows during a dead time is a target diode. Of the upper- and lower-arm switches, the switch that includes the target diode is a target switch. The remaining switch is an opposing arm switch. The drive circuit maintains an electric potential of a control terminal relative to a second terminal of the target switch at a negative voltage over a period from a timing subsequent to a start timing of a dead time immediately after the target switch is switched to an off-state until a point within a period over which the opposing arm switch is set to an on-state, and subsequently maintains the electric potential at an off-voltage until a next dead time is ended.

Abstract: This application provides a power supply system for a motor control module and a vehicle. The power supply system includes a first current limiting unit and an isolation unit. An output end of a first direct current power supply is coupled to a first input end of the isolation unit to form a first power supply loop with the isolation unit. A first output end of a second direct current power supply is coupled to one end of the first current limiting unit. Another end of the first current limiting unit is coupled to a second input end of the isolation unit to form a second power supply loop with the isolation unit. The second power supply loop is connected in parallel to the first power supply loop.

Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.

Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.

Abstract: A device includes an interface circuit connected between a pad and an internal circuit. The interface circuit comprises a pull-up driver including first and second PMOS transistors and a first impedance controller. The first PMOS transistor is connected between a power terminal provided to a power voltage and a first connection node and controlled by a first control bias. The second PMOS transistor connected between the first connection node and the pad and normally turned-on, and the first impedance controller is connected to the first connection node to control an impedance thereof based on the first control bias. The interface circuit further includes a pull-down driver including first and second NMOS transistors. The first NMOS transistor is connected between the pad and a second connection node and controlled by a driving voltage, and the second NMOS transistor is connected between the second connection node and a ground voltage terminal.

Abstract: A control method of a switching circuit, a control circuit of the switching circuit and the switching circuit are provided. The control circuit includes a slope buffer and a first operational amplifier. The slope buffer receives a first voltage reference, and controls slopes of a rising edge and a falling edge to generate a second voltage reference. The first operational amplifier receives an output feedback voltage and a reference voltage, and performs an operational amplification to obtain a compensation voltage. When the first voltage reference has the falling edge, the reference voltage is coupled to the first voltage reference through a first switch, and the second voltage reference is coupled to an output voltage through a second switch. When the first voltage reference has the rising edge, the reference voltage is coupled to the second voltage reference through a third switch.

Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

Abstract: Described herein are apparatuses and methods for applying high voltage, sub-microsecond (e.g., nanosecond range) pulsed output to a biological material, e.g., tissues, cells, etc., using a high voltage (e.g., MOSFET) gate driver circuit having a high voltage isolation and a low inductance. In particular, described herein are multi-core pulse transformers comprising independent transformer cores arranged in parallel on opposite sides of a substrate. The transformer cores may have coaxial primary and secondary windings. Also describe are pulse generators including multi-core pulse transformers arranged in parallel (e.g., on opposite sides of a PCB) to reduce MOSFET driver gate inductance.

Abstract: Electrical installation comprising a monitoring module positioned between a sensor connected to a measurement cable and first and second power supply cables for the sensor. The monitoring module comprises a first transistor comprising a first and a second power electrode and a control electrode, the first and the second power electrodes of the first transistor being electrically connected to the second power supply cable and to the measurement cable, respectively, so that, when the first transistor is in the closed state thereof, a first fault value is generated on the measurement cable. The control electrode of the first transistor is connected to the first power supply cable so that the loss of first potential on the first power supply cable, caused by the interruption thereof, automatically triggers the switching of the first transistor to the closed state thereof.

Abstract: A gate driver includes at least one stage, which includes: a first output circuit configured to supply a voltage of a first power source or a voltage of a second power source to a first output terminal and including a fourth capacitor connected between a second node and the first output terminal; a second output circuit configured to supply a signal supplied to a fourth input terminal or the voltage of the second power source to a second output terminal; an input circuit configured to control a voltage of the second node and a voltage of a third node; a first signal processor configured to control a voltage of a first node; a second signal processor configured to control the voltage of the second node; and a third signal processor connected between the first node and the third node, and configured to control the voltage of the first node.

Abstract: A gate driver on array (GOA) circuit and a display panel are provided. The GOA circuit provides a pull-up maintaining module including transistors T11, T12, and T13. In a pre-charge sub-phase t1 and an output sub-phase t2, a node Qb is at a high level to pull down a node P and turn off the transistor T13. A node K changes to the high level under control of the transistor T11. The transistor T12 is turned on, and the node Qb is keeping at the high level. A node Qa is keeping at the high level in the pre-charge sub-phase, and keeping at a bootstrap electrical level in the output sub-phase.

Abstract: The disclosure relates to a switched capacitor converter (SCC) with gate driving circuits for limiting currents provided by switching field effect transistors. Embodiments disclosed include an SCC with gate driver curcuits providing gate voltage signals to power FETs, each gate driver circuit comprising first and second gate driver modules and configured to operate in: a first mode in which the first gate driver module provides a gate voltage signal to a power FET that switches between first and second voltage rails by operation of first and second switches connected between the pair of voltage rails; and a second mode in which, in reponse to enabling of a current limit switching signal, the first gate driver module disables switching of one of the first and second switches and the second gate driver module operates to limit a current provided to the power FET.

Abstract: A gate driver includes active stages that output gate signals to a display part and pre-stages connected to the active stages to output carry signals to the active stages. The pre-stages include a first pre-stage and a second pre-stage. The second pre-stage includes a Q node compensator that receives a clock signal from the first pre-stage and compensates for a voltage of a Q node based on the clock signal of the first pre-stage. The Q node compensator includes a feedback transistor that diode-connects a feedback input terminal, which receives the clock signal of the first pre-stage, to a feedback node of the second pre-stage. The feedback transistor includes a first electrode, a second electrode, and a third electrode, where the first electrode is connected to the feedback input terminal, the second electrode is connected to the first electrode, and the third electrode is connected to the feedback node.

Abstract: A shift device mounted on a vehicle includes a motor configured to drive, by electric power supplied from a power supply mounted on the vehicle, a shift switching member configured to switch shift positions, a cut-off unit configured to cut off conduction of a power supply line through which the electric power is supplied to the motor, and a drive circuit unit configured to output the electric power to the motor and including a driving switching element configured to execute a switching operation. The shift device is configured to determine an abnormality of the power supply line when a voltage of the power supply line is smaller than a predetermined threshold value, turn off the driving switching element, and cut off the conduction of the power supply line by the cut-off unit.

Abstract: A system includes a level shifter coupled to a voltage source, a first transistor, and a second transistor. The system also includes a first current source coupled to the first transistor and the second transistor and configured to bias the first transistor and the second transistor. The system includes a slew detector coupled to the voltage source and to the first current source, where the slew detector is configured to detect a change in voltage of the voltage source, and further configured to provide current to the first current source responsive to detecting the change. The system also includes a second current source coupled in parallel to the first current source, where the second current source is configured to provide current to the first current source responsive to a control signal.

Abstract: Examples of contactor controllers, systems and methods time-modulate levels of high-side (HS) and low-side (LS) clamp voltages in a contactor controller to switch a path through which current flows during quick-turn-off (QTO) of the contactor controller. One of the clamp voltages is at a high level and the other is at a low level. The output voltage of the contactor controller is held at the low level. The path switching may be a function of one or more parameters. In a configuration, the level of a supply voltage of the contactor controller is monitored and used to control the path switching. In a configuration, temperatures of HS and LS transistors of the contactor controller are monitored and used to control the path switching. Control of the path switching may be performed to dissipate power in a larger area to increase thermal performance of the contactor controller. Both clamps may remain active throughout the QTO process, providing redundancy and safety.

Abstract: In one example, an apparatus comprises: a voltage sensing circuit having a voltage sensing terminal and a voltage sensing output, the voltage sensing circuit configured to generate a first voltage at the voltage sensing output representing a second voltage at the voltage sensing terminal; a control circuit having a control circuit input and a control circuit output, the control circuit input coupled to the voltage sensing output, the control circuit configured to: determine a state of a transistor based on the first voltage; and generate a driver signal at the control circuit output based on the state; and a driver circuit having a driver input and a switch control output, the driver input coupled to the control circuit output, the driver circuit configured to provide a current at the switch control output responsive to the driver signal.

Abstract: A method of controlling a switch, including: a) applying a control signal to a control terminal of the switch, said control signal exhibiting at least one first switching between a switch turn-on control state and a switch turn-off control state; and b) applying a switch turn-off potential on said control terminal after a first delay starting at said first switching, the first delay being greater than the turn-off time.

Abstract: A control device for a converter including a one-phase or multiple-phase converter circuit includes: a magnetic coupling determination unit configured to determine whether the converter circuit is a magnetically coupled circuit in which a reactor of the converter circuit is in a magnetically coupled state; and a control unit configured to change a control method for the converter according to a determination result of the magnetic coupling determination unit.

Abstract: A gate driving circuit and a display panel are provided. The gate driving circuit reduces the number of transistors through the inverter in the pull-down maintaining circuit such that the number of the signal output ends connected to the inverter is reduced. In this way, the number of the other transistors in the pull-down maintaining circuit is also reduced. Therefore, the number of the transistors and the number of the signal output ends of the pull-down maintaining circuit are both reduced. This means that the number of the transistors and the number of the signal output ends of the gate driving circuit are both reduced.

Abstract: A current sensing circuit and a minimum operating frequency for a wireless power transmission system is presented. A method of measuring current through a wireless power transmit coil, includes receiving a signal from a switching circuit into a sampling circuit; filtering the sampled signal from the sampling circuit; biasing the filtered sampled signal, wherein the biasing occurs only when the sampling circuit is active; and amplifying the biased signal to provide a transmit coil current signal. A method of measuring current through a wireless power transmit coil, includes receiving a signal from a switching circuit into a sampling circuit; filtering the sampled signal from the sampling circuit; biasing the filtered sampled signal, wherein the biasing occurs only when the sampling circuit is active; and amplifying the biased signal to provide a transmit coil current signal.

Abstract: A display system includes a first memory and a display driver. The display system is configured to control the first memory to receive compensation information from the first memory with a first slew rate and generate data signals for image data to be displayed on a display panel. The generation of the data signals comprises performing a compensation for the data signals based on the compensation information received from the first memory. The display driver is further configured to update pixels of the display panel with the data signals during an active display state. The display driver is further configured to generate updated compensation information based at least in part on the image data and the compensation information received from the first memory and transmit the updated compensation information to the first memory during the active display state with a second slew rate lower than the first slew rate.

Abstract: A pre-charge control circuit includes a control unit, a conversion unit, and a pre-charge switch. The control unit provides a control signal according to a PWM signal, and the conversion unit provides a control voltage according to the control signal. The pre-charge switch adjusts a magnitude of the current flowing through the input path of the electronic circuit according to the control voltage.

Abstract: In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300 V.

Abstract: An electrical switching system includes a constant-power controller and a switching device electrically coupled between a first node and a second node. The constant-power controller is configured to (a) generate a digital control signal to control the switching device, (b) control a duration of an active phase of the digital control signal at least partially based on a voltage across the switching device, and (c) control a peak value of the digital control signal to regulate a peak magnitude of current flowing through the switching device.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

Abstract: A power converter is provided. The power converter includes two or more hybrid switching circuits electrically connected to a source or storage element. Each switching circuit includes a wide bandgap device that is parallel-connected to a silicon-based device. The converter further includes a controller that is operatively coupled to each device of the first and second switching circuits. The controller is configured to operate each hybrid switching circuit by (i) activating the silicon-based device for an activation period, (ii) activating the wide bandgap device for a predetermined duty cycle less than the activation period, (iii) deactivating the silicon-based device while the wide bandgap device is activated, and (iv) deactivating the wide bandgap device. The hybrid switching circuits are sequentially operated to convert an alternating current of a power supply into a link voltage for a power converter, for example.

Abstract: A drive circuit has a control signal input for receiving a first control signal at a first circuit input, an optocoupler which is connected to the control signal input and which is adapted to generate a galvanically decoupled second control signal in accordance with the first control signal, an output circuit for controlling at least one circuit output terminal of the drive circuit in accordance with a third control signal, and an electronic control circuit comprising an energy supply, an input for receiving the second control signal, and an output for outputting the third control signal in accordance with the second control signal received at the input.

Abstract: The invention provides a voltage-following series power supply circuit, comprising a power supply end and a ground end; a power supply module comprising an input end connected to the power supply end, and an output end for providing a power supply to two or more to-be-powered chips, the power supply module and the to-be-powered chips connected in series between the power supply end and the ground end; and at least one auxiliary power supply module for supplying an auxiliary power supply to the to-be-powered chips, wherein a voltage following module is further connected between the power supply end and the auxiliary power supply module for adjusting a voltage of the auxiliary power supply.

Abstract: An apparatus leverages the existing power interconnect for DC power delivery by including a persistent DC power module into a power panel, thereby enabling a more efficient use of the energy. The persistent DC power module includes, in part, a control unit which is adaptive to the variations and availability of the external DC power source to ensure a constant and consistent delivery of DC voltage. The apparatus minimizes energy waste and e-waste, and is compatible with the existing legacy AC infrastructure.

Abstract: A system and method for measuring optical power is described. The optical system and method may include a module configured to generate a secondly modulated signal based on secondly modulating a firstly modulated signal with an amplitude modulated signal. The firstly modulated signal may include data that is modulated for transmission by a laser diode array. The firstly modulated signal may then be secondly modulated using amplitude modulation techniques. The system may further include a photodiode configured to generate a photodiode current based on optically sensing a laser diode array. The laser diode array outputs an optical output power based on being driven by the secondly modulated signal. The system may yet further include a controller configured to calculate the optical output power from the photodiode current based on the amplitude modulated signal.

Abstract: A driving circuit includes first and second driving units connected in parallel to each other, wherein both the first and second driving units start to supply a gate current to a gate of a switching device in a turn-on operation of the switching device, when a gate voltage of the switching device increases and has reached a threshold voltage of the switching device, the first driving unit continues to supply the gate current, and the second driving unit stops supply of the gate current before the gate voltage has reached the threshold voltage.

Abstract: A semiconductor device includes a normally-off power transistor integrated in a semiconductor die and a first failsafe pulldown circuit. A gate of the normally-off power transistor is electrically connected to a control terminal of the semiconductor die. The first failsafe pulldown circuit includes a first normally-on pulldown transistor integrated in the semiconductor die and a turn-off time control circuit. A gate of the first normally-on pulldown transistor is electrically connected to a first reference terminal of the semiconductor die. The first normally-on pulldown transistor is configured to pull down the gate of the normally-off power transistor to a voltage below a threshold voltage of the normally-off power transistor when no voltage is applied across the control terminal and the first reference terminal. The turn-off time control circuit is configured to control a turn-off time of the normally-off power transistor.

Abstract: A circuit and method for detecting a failure of a switching power device is disclosed. The circuit and method utilize a Kelvin connection of a four-terminal configuration of the switching power device to sense a resistance of at least one wire-bond. The resistance corresponds to a defect or defects in the at least one wire-bond and so it can be used to detect a failure before damage occurs. A threshold used for detecting the failure can be adjusted to accommodate variations in the switching power device and/or the application in which it is being used. Additionally, the failure detection is carried out at a period after the switching power device is turned ON to prevent switching transients from affecting the detection.

Abstract: The present disclosure relates to an insulated gate bipolar transistor (IGBT) and, more particularly, to an insulated gate bipolar transistor, in which a barrier region is in a mesa between adjacent trench gates to divide the width of the mesa, thereby inducing the accumulation of hole carriers, and thus reducing an on-resistance (e.g., of the IGBT).

Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: injecting charge carriers at a first rate into an upper base of the transistor, the injecting at the first rate results in current flow through the transistor from an upper collector-emitter to a lower collector-emitter, and the current flow results in first voltage drop measured across the upper collector-emitter and the lower collector-emitter; and then, within a predetermined period of time before the end of a first conduction period of the transistor, injecting charge carriers into the upper base at a second rate lower than the first rate, the injecting at the second rate results in second voltage drop measured across the upper collector-emitter and the lower collector-emitter, the second voltage drop higher than the first voltage drop; and then making the transistor non-conductive at the end of the conduction period.

Abstract: In an embodiment, an integrated circuit includes one or more GPIO pins coupled to a GPIO block in the integrated circuit. At least a first GPIO pin may include corresponding logic circuitry that may be programmed to apply one or more requirements to changes of the digital value received on the first GPIO pin before the change is forwarded to a destination within the integrated circuit. That is, if the requirements are not met for a given change, the logic circuitry may suppress the given change so that it is not provided to other circuits internal to the integrated circuit (e.g. the destination circuit that receives communication via the GPIO pins). The one or more requirements may be a form of hysteresis, for example.

Abstract: Driver circuitry for driving a power semiconductor switch having a control input and main terminals is described. The driver circuitry includes control terminal driver circuitry coupled to the control input and configured to provide a drive signal, a sense terminal coupled to the main terminal, a current mirror coupled to the sense terminal to mirror a current input into the sense terminal during turn-off, a first current comparator configured to compare a current signal received from the current mirror to a first current threshold and output a first signal representative of the comparison, and a second comparator configured to compare a signal received from the sense terminal to a turn-on threshold and output a second signal representative of the comparison. The turn-on threshold represents a highest voltage of the main terminal during turn-on. The first current threshold represents a highest voltage of the main terminal during turn-off.

Abstract: A device includes a heterojunction device, a unipolar power transistor operatively connected in series with said hetero junction device; an external control terminal for driving said unipolar power transistor and said heterojunction device; and an interface unit having a plurality of interface terminals. A first interface terminal is operatively connected to an active gate region of the heterojunction device and a second interface terminal is operatively connected to said external control terminal. The heterojunction device includes a threshold voltage less than a threshold voltage of the unipolar power transistor, wherein the threshold voltage of the heterojunction device is less than a blocking voltage of the unipolar power transistor.

Abstract: A semiconductor device includes: a test transistor which is formed over a substrate; a test pattern structure which is formed in an upper portion of the substrate to be spaced apart from the test transistor; and a protection transistor which is positioned between the test pattern structure and the test transistor.

Abstract: A driver circuit controls an output unit that switches whether or not to supply a current to an output line, in accordance with a potential difference between a first control signal to be input and a voltage of the output line. The driver circuit has a control line transmitting the first control signal to the output unit; a connection switching unit switching whether or not to connect the control line and the output line; a pre-stage control unit that is provided between a high potential line and a low potential line and selects and outputs a potential of any one of the high potential line and the low potential line in accordance with a second control signal; and a post-stage control unit causing the connection switching unit to connect the control line and the output line when the pre-stage control unit outputs a voltage higher than a predetermined threshold value.

Abstract: Transformer-driven power switch devices are provided for switching high currents. These devices include power switches, such as Gallium Nitride (GaN) transistors. Transformers are used to transfer both control timing and power for controlling the power switches. These transformers may be coreless, such that they may be integrated within a silicon die. Rectifiers, pulldown control circuitry, and related are preferably integrated in the same die as a power switch, e.g., in a GaN die, such that a transformer-driven switch device is entirely comprised on a silicon die and a GaN die, and does not necessarily require a (large) cored transformer, auxiliary power supplies, or level shifting circuitry.

Abstract: Techniques for controlling a power converter with a control signal and circuitry configured to translate the control signal into one or more pulse modulated drive signal(s) to operate the power converter. The translation circuitry may receive the control signal, extract frequency information, duty cycle, dead time, and other information from the control signal, and output at least one pulse modulated drive signal, based on the extracted information, to a driving stage that may operate the power converter. The control signal may be a digital signal that includes rising edges and falling edges. The edges of the first type may define the frequency information. The edges of the second type may define other information extracted by the translation circuitry, e.g., duty cycle, dead time and so on. In some examples the power converter may be a resonant power converter.

Abstract: The present invention discloses a double-gate trench-type insulated-gate bipolar transistor device. A first trench and a second trench, which are located in a P-type doped well layer, and separate from each other, are extended into a lightly-doped N-type drift layer. A heavily-doped P-type source region and a heavily-doped N-type source region, which are sequentially connected, are located between the first trench and the second trench, and are arranged at an upper part of the P-type doped well layer in a horizontal direction. The heavily-doped P-type source region is located at a periphery of the second trench, a middle part and the upper part of the P-type doped well layer are provided with an N-type doped well layer and a P-type doped base region layer, respectively. The heavily-doped P-type source region and the heavily-doped N-type source region are both located at an upper part of the P-type doped base region layer.

Abstract: An electronic circuit is disclosed. The electronic circuit includes a distributed power switch. In some embodiments, the electronic circuit also includes one or more of a distributed gate driver, a distributed gate pulldown device, a distributed diode, and a low resistance gate and/or source connection structure. An electronic component comprising the circuit, and methods of manufacturing the circuit are also disclosed.