Abstract: A current mode control modulation includes a ramp signal generator generating a slope compensated ramp signal with slope compensation. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator includes a switched capacitor circuit supplied by a current circuit to charge or discharge nodes in the switched capacitor circuit to generate the ramp signal with slope compensation.

Abstract: An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.

Abstract: A ramp signal generator generates a slope compensated ramp signal with optimal slope compensation for a current mode control modulator. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator is implemented using a switched capacitor circuit with charge scaling to generate the ramp signal with optimal slope compensation built into the ramp signal.

Abstract: An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.

Abstract: A switching power device (100) is provided which comprises: a normally-ON transistor (12), a normally-OFF metal-oxide-semiconductor field-effect transistor (MOSFET) (14), the normally-OFF MOSFET (14) being connected in series to a source terminal (12S) of the normally-ON transistor (12), and a driver (16) connected to and arranged to drive a gate terminal (12G) of the normally-ON transistor (12). A switching transistor (28) can then be positioned between the source terminal (12S) of the normally-ON transistor (12) and a common connection (30) of the driver (16) to protect the switching power device (100) from deleterious over-voltage and over-current spikes.

Abstract: A circuit according to an embodiment includes a first slicer connected to an input port and a threshold circuit connected to a threshold port of the first slicer and configured to generate a first threshold voltage according to at least a first magnitude of a nominal value of a leading bit in a signal received at the input port. The first slicer is configured to slice the signal according to the first threshold voltage. In some embodiments, the threshold circuit calculates the first threshold voltage according to at least the first magnitude of the nominal value of the leading bit in the signal and a second magnitude of an interference voltage caused, in the leading bit, by a preceding bit.

Abstract: Voltage generation circuits are useful in the generation of internal voltages for use in integrated circuits. Voltage generation circuits may include a stage capacitance and a voltage isolation device connected to the stage capacitance. The voltage isolation device may include a first current path between an input and an output of the voltage isolation device through a diode, and a second current path between the input and the output of the voltage isolation device through a gate. The gate is responsive to the contribution of a low-pass filter between the output of the voltage isolation device and the gate, and to the contribution of a high-pass filter between a clock signal node and the gate.

Abstract: One embodiment of the present invention relates to a waveform generator that includes a first pair of capacitors, a second pair of capacitors, an op amp and control logic. The op amp has inputs and provides a differential triangular waveform at its outputs as an output signal. The control logic includes capacitor control logic, ramp control logic, reset control logic and charge control logic. The capacitor control logic connects a current pair of the first and second capacitors to the inputs of the op amp. The ramp control logic provides ramp currents to the current pair. The reset control logic resets capacitors of a next pair to selected voltage(s), such as zero. The charge control logic charges the next pair of capacitors, typically after the next pair of capacitors has been driven to the selected voltage(s).

Abstract: The antenna driving device of the present invention is composed of a trapezoidal-wave signal generating circuit for generating a trapezoidal-wave signal from a reculangular-wave signal having a predetermined frequency; and a trapezoidal-wave signal amplifying circuit for amplifying the trapezoidal-wave signal and feeding the amplified signal to an antenna load.

Abstract: The present application discloses trapezoidal fire pulse generating methods and devices. According to the devices and methods of the present application, the voltage value of the positive DC control voltage signal, the voltage value of the negative DC control voltage signal, the voltage value of the rise-time DC control voltage signal and a fall-time DC control voltage signal can be determined according to the parameter values of a trapezoidal fire pulse required to be output. Thus, corresponding DC control voltage signals can be generated. Further, the positive DC control voltage signal and the negative DC control voltage signal can be modulated to a square-wave pulse. Then, the rise-time DC control voltage signal, the fall-time DC control voltage signal and the square-wave pulse can be input to a inverse integrator so as to generate a trapezoidal fire pulse.

Abstract: The antenna driving device of the present invention is composed of a trapezoidal-wave signal generating circuit for generating a trapezoidal-wave signal from a reculangular-wave signal having a predetermined frequency; and a trapezoidal-wave signal amplifying circuit for amplifying the trapezoidal-wave signal and feeding the amplified signal to an antenna load.

Abstract: The present application discloses trapezoidal fire pulse generating methods and devices. According to the devices and methods of the present application, the voltage value of the positive DC control voltage signal, the voltage value of the negative DC control voltage signal, the voltage value of the rise-time DC control voltage signal and a fall-time DC control voltage signal can be determined according to the parameter values of a trapezoidal fire pulse required to be output. Thus, corresponding DC control voltage signals can be generated. Further, the positive DC control voltage signal and the negative DC control voltage signal can be modulated to a square-wave pulse. Then, the rise-time DC control voltage signal, the fall-time DC control voltage signal and the square-wave pulse can be input to a inverse integrator so as to generate a trapezoidal fire pulse.

Abstract: A correlated double sampling circuit includes a first capacitor and a comparator. The first capacitor may be configured to receive a ramp signal via a first end. The comparator may be configured to receive the ramp signal and an output signal of a unit pixel circuit via a differential amplifier included in the comparator. The comparator may be also be configured to compare the output signal with the ramp signal and may be configured to directly receive the output signal of the unit pixel circuit at a first input terminal of the differential amplifier. A second input terminal of the differential amplifier is connected to a second end of the first capacitor.

Abstract: To output a digital signal corresponding to illuminance without being adversely affected by circuit delay. A photoelectric conversion device includes a photoelectric conversion element; a ramp-wave output circuit; a first comparator for comparing the ramp-wave signal and a first potential; a second comparator for comparing the ramp-wave signal and a second potential; a flip-flop circuit for generating a clock signal whose frequency is changed in accordance with the amount of photocurrent; a circuit for calculating a negative OR of the output signal of the first comparator and the output signal of the second comparator; a counter circuit for counting the pulse number of the clock signal; and a pulse output circuit for generating a period during which the pulse number is counted in the counter circuit. The pulse output circuit includes a switch for stopping the generation of the period during which the pulse number is counted.

Abstract: A PWM driver for driving an electric device by a PWM signal includes an ECU that provides a command signal, first circuit that provides a carrier signal of a triangular shape having a preset frequency, a second circuit that forms a PWM signal having a duty ratio formed based on the carrier signal and the command signal and an output circuit that drives an output device. The second circuit includes a duty ratio limiting circuit that limits the duty ratio of the PWM signal to a range between a first duty ratio and a second duty ratio to prevent the wave shape of the PWM signal from becoming a shape of an impulse.

Abstract: In the present invention, a device and method for generating one-shot bipolar waveforms are provided. The provided device can generate bipolar sawtooth waves, bipolar sinusoidal waves and bipolar square waves by employing a division circuit, an one-shot circuit, an analog switch and a synchro-trigger gate-controlled circuit.

Abstract: A serial communication transceiver includes a trapezoidal wave signal generation circuit for producing a trapezoidal wave signal responsive to a control signal. The trapezoidal wave signal generation circuit decreases harmonic components in the trapezoidal wave signal and suppresses superimposed noise. The serial communication transceiver also includes a driver circuit for delivering the trapezoidal wave signal to a communication line and a receiver circuit for receiving the trapezoidal wave signal over the communication line. The receiver circuit includes a filter circuit that has a filtering time at the rise of a logically bi-leveled signal substantially equal to a filtering time at the fall of the logically bi-leveled signal.

Abstract: A trapezoid signal generating circuit has a charging and discharging circuit for a capacitor to generate a trapezoid signal which has less change at its rising portion and falling portion. Current output circuits supply a charging current and a discharging current in accordance with a voltage outputted from a current control circuit, respectively. The current control circuit has a charging and discharging circuit similar to the charging and discharging circuit, and produces an output voltage. This voltage increases in accordance with a linear function for a period from a time point when an input signal changes its level to a time point when the voltage reaches a reference voltage, and decreases thereafter in accordance with a linear function. The current flowing into the capacitor also increases and decreases in accordance with the linear function, so that the terminal voltage of the capacitor increases and decreases in accordance with a quadratic function.

Abstract: Circuitry is disclosed for controlling the slope of rising and falling edges of a signal. The circuitry includes a ramp signal generator that receives an input signal and that generates a trapezoidal signal based on the input signal, and a circuit array that receives the trapezoidal signal and that generates control signals based on the trapezoidal signal. Output transistors have gates that receive a set of the control signals. The output transistors include a top transistor and a bottom transistor. The top transistor has a source connected to a supply potential and a drain connected to an output. The bottom transistor has a source connected to a reference potential and a drain connected to the output. The top transistor and the bottom transistor are gated by the control signals to control a shape of an edge of an output signal at the output.

Abstract: A low power analog output circuit is disclosed that utilizes a low pass filter driven by a bit stream to render a waveshaped output signal based upon a raw digital data signal. The analog output circuit includes sequential bit pattern selection logic that receives as an input, the raw digital data signal. The analog output circuit also includes a bit pattern storage that specifies bit stream sequences that are selected in accordance with control signals generated by the state machine based upon its current state and the current raw digital data signal. The analog output circuit includes an output stage driven by a digital input signal corresponding to values provided by a bit stream sequence selected from the bit pattern storage. The output stage comprises a low pass filter circuit having an effective time constant that is greater than a hold period associated with a single bit of the bit stream sequence that drives the digital input signal.

Abstract: A process, temperature and supply insensitive trapezoidal pulse generator includes a stable reference current source for generating a stable reference current. The trapezoidal pulse generator includes a current amplification circuit adapted to receive the stable reference current and operable responsive to the stable reference current to amplify the stable reference current to a mirrored current. The trapezoidal pulse generator includes an output circuit coupled to the current amplification circuit and adapted to receive the mirrored current and operable in a second frequency to generate a trapezoidal pulse.

Abstract: Generating a waveform having one signal level periodically and different signal levels in other durations. Two input signals are received, one having a desired constant level and another having desired signal levels. The desired output waveform is generated by selecting one of the two input signals. As a result, the output waveform may be generated to have (transitions) with high frequency even if the signal levels between adjacent portions are substantially different. Such waveforms are useful to test CDS (correlated double sampling) samplers.

Abstract: Systems and methods for enhancing slew control of output signals. An output driver receives an input signal and controllably increases the gain of that signal to provide a high quality output signal for use by an electronic device coupled thereto. The output driver includes an operational amplifier that maintains stability of the output signal through a feedback of the output signal. A control circuit supplies a signal to the output driver such that the driver to improve the shape of the output signal as the input signal is applied. After the operational amplifier regains control, the control circuit disengages. One embodiment of the present invention may be particularly useful as a USB output driver.

Abstract: A system and method are provided for controlling the on/off timing relationship between two transistors in a differential that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns one while the other is turning off. An overlap signal is derived from the tail node excursion and is indicative of whether the on/off signals are overlapping too much or too little. A control signal is generated based on the overlap signal. The timing of driver signals used to derive the on/off signals is adjusted based on the control signal. When more overlap is needed, the timing of the driver signals is adjusted such that there is more overlap of the derived on/off signals. When less overlap is needed, the timing of the driver signals is adjusted such that there is less overlap of the derived on/off signals.

Abstract: Charge accumulated at an output node of an output transistor is discharged to the ground through the output transistor as a spike current. To reduce noise of the spike current, a control signal is sent from an output transistor driving circuit set to a low impedance to the output transistor in a first driving stage to quickly turn on the output transistor, a control signal is sent from the output transistor driving circuit set to a high impedance to the output transistor in a second driving stage to output the spike current through the output transistor at a fixed rate, and a control signal is sent from the output transistor driving circuit set to a low impedance to the output transistor in a third driving stage to quickly discharge all the charge. Therefore, a time-current characteristic of the spike current is set almost in a trapezoid shape, and both a spike current peak value and a spike current occurrence time period in the spike current can be sufficiently lowered.

Abstract: The present invention discloses an output circuit, by which it is possible to reduce power consumption while maintaining maximum voltage value to be outputted at high level. In this output circuit, a charge-and-discharge circuit uses a terminal voltage Vc of a capacitor as a trapezoidal wave voltage, and a drive circuit drives an output transistor based on the terminal voltage Vc, and a voltage Vo equal to the terminal voltage Vc is outputted to the load. A voltage detection circuit detects an emitter voltage (Vc+VF) of the transistor and generates an electric current proportional to the terminal voltage Vc. This electric current is turned to a base current of the output transistor via a variable current circuit. Therefore, a base current proportional to the output voltage Vo is supplied to the output transistor.

Abstract: Charge accumulated at an output node of an output transistor is discharged to the ground through the output transistor as a spike current. To reduce noise of the spike current, a control signal is sent from an output transistor driving circuit set to a low impedance to the output transistor in a first driving stage to quickly turn on the output transistor, a control signal is sent from the output transistor driving circuit set to a high impedance to the output transistor in a second driving stage to output the spike current through the output transistor at a fixed rate, and a control signal is sent from the output transistor driving circuit set to a low impedance to the output transistor in a third driving stage to quickly discharge all the charge. Therefore, a time-current characteristic of the spike current is set almost in a trapezoid shape, and both a spike current peak value and a spike current occurrence time period in the spike current can be sufficiently lowered.

Abstract: The present invention discloses an output circuit, by which it is possible to reduce power consumption while maintaining maximum voltage value to be outputted at high level. In this output circuit, a charge-and-discharge circuit uses a terminal voltage Vc of a capacitor as a trapezoidal wave voltage, and a drive circuit drives an output transistor based on the terminal voltage Vc, and a voltage Vo equal to the terminal voltage Vc is outputted to the load. A voltage detection circuit detects an emitter voltage (Vc+VF) of the transistor and generates an electric current proportional to the terminal voltage Vc. This electric current is turned to a base current of the output transistor via a variable current circuit. Therefore, a base current proportional to the output voltage Vo is supplied to the output transistor.

Abstract: A ramp generator for use in a video mixing system to produce various transition effects between edited video frames. The ramp generator produces a ramp signal R according to the equation R=Ah+Bv+C. The ramp signal R corresponds to a video frame comprised of v video lines (where v is an integer from 0 to m), each video line having h pixels (where h is an integer from 0 to n), and where A, B, and C are coefficients. Multiple ramp signals can be combined to a ‘solid’ signal. Solid signals can be used to generate masks or wipe patterns. Each ramp be edge modulated before combining into a solid signal. A solid signal can also be solid modulated.

Abstract: A driver amplifier for a bus feeds single polarity signals of controlled slew rate to the bus. The slew rate control is effected by a feedback capacitor connected from the output to the input of the amplifier. A clamp is provided for selectively connecting the input of the amplifier through a low impedance path to a point of reference voltage so that when the amplifier is quiescent signals on the bus cannot be fed through the capacitor to turn on the amplifier. A current source and a switchable current sink are connected to the input of the amplifier to change the capacitor to produce the slew rate controlled transitions. Another driver amplifier of the same design but using components of the opposite conductivity type can be used to apply signals of the opposite polarity to the same bus.

Abstract: An object of the present invention is to provide a waveform shaping circuit for producing a trapezoidal pulse whose leading edge and trailing edge have the same slope and not inducing and radiating harmonic components under any conditions. A waveform shaping circuit comprises a common-emitter transistor 1, a first resistor 2 and second resistor 3 connected in series between a signal input terminal 9 and the base of the transistor 1, a third resistor and first capacitor 5 connected in parallel between a node a between the first resistor 2 and second resistor 2 and a ground, a feedback capacitor 6 connected between the collector of the transistor 1 and the node 1, and a collector load resistor 7 connected in series with the collector of the transistor 1. The waveform of a pulse to be applied to the signal input terminal 9 is reshaped to produce a trapezoidal pulse whose leading edge and trailing edge have a substantially equal slope, and then the trapezoidal pulse is led through a signal output terminal 10.

Abstract: An integrated circuit pulse generator for per pin testing of electronic circuits. The pulse generator allows for independent adjustment of the slew rates of the rising and falling edges of the pulses. The pulse edges are generated by summing two separately controlled falling edge ramp generators. The circuit design of the pulse generator is structured to allow implementation with NPN transistors. The falling edge ramp generators operate by discharging a capacitor with a current source. The slew rates are varied by incrementally adding capacitance to the capacitor being discharged.