Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.

Abstract: Over-current detection circuits and methods for adiabatic power converters that provide numerous advantages over known solutions, including simple digital control, enabling trimming to be done in the low voltage domain, and avoidance of high-voltage sense current mirrors. Embodiments include a slope detector circuit configured to measure a slope of the immediate output voltage VX of an adiabatic power converter during a charge pump clock cycle, compare the measured slope to a pre-determined value representing a slope of an over-current condition, and assert a flag if comparison indicates an over-current condition. An auto-calibration circuit may be included which presents a set of known loads across the output of an adiabatic power converter at device startup, measures the resulting counts from the slope detector counter, and extrapolates to a count that corresponds to a maximum allowed current.

Abstract: A portable device including drift-compensated capacitive proximity sensor that exploits a special method of drift compensation based on the variation of the measured proximity signal. The drift is tracked when the variation is within a stated interval, and frozen when the variation is outside. The sensor is capable of following a drift not only when the phone is inactive, but also when it is close to the body of the user, by freezing the tracking when the capacity varies steeply, as when the user moves the device, and resuming it when the variation is within acceptable limits.

Abstract: The application provides a method and an apparatus for controlling a laser projection device, the laser projection device being provided with a thermoinduction sensor on housing for acquiring an infrared signal in environment where the laser projection device is located, the method including: acquiring first signal outputted by the thermoinduction sensor in first moment and second signal outputted in current moment, the first moment being prior to the current moment, first signal and second signal being signals outputted by the thermoinduction sensor according to the infrared signal; determining a first signal change rate according to first difference between first signal and second signal and second difference between first moment and current moment; reading a preset signal change rate and a threshold signal; determining an operation mode of laser projection device according to magnitude relation of first signal change rate and preset signal change rate, second signal and threshold signal.

Abstract: Aligning a closed caption track to a media content includes calculating the offset and the drift between the closed caption track and the media content item. The closed caption track is aligned to the media content item as a function of the calculated offset and drift.

Abstract: Method, apparatus and system for calibrating and synchronizing a seismic acoustic source array (50) by taking into account both a time-break signal (500) and a near-field signal (504). A time delay between the time-break signal and the near-field signal is used to calculate an offset for adjusting the shooting of the source elements of the source array.

Abstract: Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.

Abstract: A proximity switch assembly and method for detecting activation of a proximity switch assembly is provided. The assembly includes a plurality of proximity switches each having a proximity sensor providing a sense activation field and control circuitry processing the activation field of each proximity switch to sense activation. The control circuitry monitors the signal responsive to the activation field and determines a differential change in generated signal, and further generates an activation output when the differential signal exceeds a threshold. The control circuitry further distinguishes an activation from an exploration of the plurality of switches and determines activation upon detection of a stable signal. The control circuit further determines a rate of change and generates an output when the rate of change exceeds a threshold rate to enable activation of a switch.

Abstract: A controller for controlling an LED assembly is described. The controller is arranged to—receive an input signal representing a required characteristic of the LED assembly,—convert the input signal to a control signal for the LED assembly,—apply a correction to the control signal to obtain a corrected control signal, the correction being based on a predetermined transient characteristic of the LED assembly,—output the corrected control signal. As such, a better correspondence between a required characteristic and an actual characteristic of the LED assembly is obtained.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: A method for arc detection includes detecting a changing rate of a signal indicative of light strength, detecting the amplitude of the signal, and indicating an occurrence of an arc if the changing rate of the signal exceeds a first predetermined threshold and the amplitude of the signal exceeds a second predetermined threshold. An arc detecting device, an arc detecting system, and an arc protecting apparatus thereof are provided. The arc detecting system includes a light collector (101) for collecting light, a light converter (103) coupled to the light collector (101) for converting the collected light into an electric signal, and an arc detecting device (106) coupled to the light converter (103) for detecting the occurrence of the arc.

Abstract: A semiconductor device includes a clock input block to receive a system clock and a data clock, a clock frequency dividing block to generate a plurality of multi-phase data frequency division clocks each of which has the phase difference of a predetermined size by dividing a frequency of the data clock and to determine whether or not phases of the plurality of multi-phase data frequency division clocks are reversed in response to a frequency division control signal, and a first phase detecting block to detect a phase of the system clock based on a phase of a first selected clock that is predetermined among the plurality of multi-phase data frequency division clocks and to determine a logic level of the frequency division control signal in response to the detected result.

Abstract: A phase detection system (100) comprises an input terminal (101), first and second peak detectors (103, 113), an averaging unit (107), an offset unit (122), and a comparator (126). Input terminal (101) is coupled to the first and to the second peak detectors (103, 113) and provides an input signal to phase detection system (100). Averaging unit (107) is coupled between offset unit (122) and both the first peak detector and the second peak detector (103, 113), and generates an intermediate signal. Offset unit (122) is coupled to input terminal (101) and generates two comparable signals by applying a predetermined offset in signal strength to the input signal or the intermediate signal. The comparator (126) is coupled to the offset unit (122) and generates an output signal by comparing the two comparable signals which is indicative of the phase of the input signal.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: A variety of edge-detection related devices, methods and systems are implemented in various fashions. One implementation is directed to an edge detector circuit (100) for detecting an edge of an input signal and producing an output level-sensitive signal that is synchronous to a clock signal having an active edge corresponding to a transition from a first-signal level to a second-signal level. A first flip-flop (102) has the input signal as a clock input and produces an internal level-sensitive signal and is reset by the output level-sensitive signal. Logic passes (104) the level-sensitive signal when the clock signal is at the second-signal level and blocks the internal level-sensitive signal when the clock signal is at the first-signal level. A second flip-flop (106) is set by the passed internal level-sensitive signal to produce the output level-sensitive signal. The second flip-flop (106) is cleared in response to the output level-sensitive signal, a reset input and the clock signal.

Abstract: A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e.g., NBTI, hot electrons).

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A signal can be analysed to determine statistical characteristics indicative of, for example, the predictability or time reversibility of the signal. The signal is examined to locate events corresponding to the crossing of predetermined levels with predetermined slopes. Multiple versions of the signal are combined, the versions being shifted with respect to each other by amounts corresponding to the spacings of the detected events. The shape of the resulting representation provides statistical information regarding the signal.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: An apparatus for indicating clock skew within integrated circuits (ICs) of a system. There are first and second IC chips operating on respective clocks in the system. According to the invention, the first IC chip operating on a first clock is configured to provide the first clock as output. The second IC chip operating on a second clock has a detection circuit to receive as input the first and the second clocks and to generate a compare signal as output, where the width of the compare signal is proportional to the amount of skew between the input clocks. The second IC chip also includes a sampling circuit coupled to receive the compare signal. With the sampling circuit, an output signal indicative of skew existing between the first and the second clocks can be asserted according to the compare signal.

Abstract: A fail-safe circuit for a differential receiver can tolerate noise. A latch is enabled when both differential inputs V+, V− rise above a reference voltage that is close to Vcc. The latch, once enabled, is set by an offset amplifier, signaling the fail-safe condition. The offset amplifier sets the latch when V+ is above or equal to V−. The differential amplifier has a small offset voltage to allow the latch to remain set when V+ and V− are equal in voltage. An output from a differential amplifier receiving V+ and V− can be blocked by a gate when the fail-safe condition is latched. Pullup resistors pull V+, V− to Vcc when an open failure occurs. The latch remains set when common-mode noise occurs on V+, V−, preventing noise from prematurely disabling the fail-safe condition. Such noise coupled into a broken cable is usually common-mode.

Abstract: Apparatus for detecting presence of a sensor includes a signal source for providing an excitation signal for the sensor. A detector circuit detects a response signal from the sensor in response to the excitation signal for presence detection. A switch is responsive to a control signal for switching between a first switch state for coupling the signal source to the sensor and a second switch state for coupling the detector circuit to the sensor. A controller provides the control signal and analyzes the detected response signal. The excitation signal can be a chirp signal that spans a range of frequencies. First and second tests of the sensor are conducted with the presence of the sensor determined from the first and second tests. Parameters of the detection including gain can be changed for the first and second tests to provide a more accurate test result.

Abstract: Method and apparatus for controlling a turn-off power converter valve having at least two series connections. Each non-latching power semiconductor switch of this power converter valve has an active collector-emitter limiting circuit. When a rising edge of a drive signal that is provided arrives, a predetermined value of the reference limited voltage of the active collector-emitter limiting circuit is decreased to a low value and is increased to the predetermined value again during a turn-off operation. Using a switch-on command, it is possible to balance the voltage sharing on the non-latching power semiconductor switches of a turn-off power converter valve having at least two series connections.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: The signal regeneration circuit recovers a digital signal from an input signal that is supplied via metallic isolation (galvanic separation). The circuit has two input terminals for the input signal and one output terminal for the recovered digital signal. A current direction sensor detects the current direction prevailing between the input terminals and outputs the signal in accordance with the last prevailing current direction. The circuit is advantageously used in connection with digital circuits that require potential isolation at their input terminals.

Abstract: In a method for switching between multiple system hosts (154,164,174,184) on a CompactPCI bus (110,120), a hot swap controller (166,186) provides to a special arbiter (820) a high priority request signal and the special arbiter (820) provides to the hot swap controller a grant signal only when the CompactPCI bus is idle. The hot swap controller (166,186) provides to the special arbiter (820) a float signal causing the special arbiter (820) to disable the system host signals, which include one or more grant signals for granting bus access to devices on the CompactPCI bus (110,120), one or more reset signals for resetting the devices, one or more interrupts and one or more clock signals provided to devices. The hot swap controller (166,186) transfers control of the CompactPCI bus (110,120) to a standby system host 154,164,174,184).

Abstract: A method and circuit for reducing the leading edge spike in a current sense signal. The current sense signal is a measure of the current through a switched power device controlled by a switching regulator controller. The slew rate of the current sense signal is limited to prevent the slew rate from exceeding a predetermined maximum. The limited slew rate signal is provided to the switching regulator controller. A transconductance amplifier may be used to limit the slew rate of the current sense signal. A capacitor at the output of the transconductance amplifier contributes to controlling the maximum slew rate of the amplifier. The capacitor is charged by the current output of the amplifier to provide a voltage signal for use in place of the original current sense signal. A switch may be provided for selecting between the slew rate limited current sense signal and the original current sense signal.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A magnetic-field-to-voltage transducer includes a Hall element and a digitally gain-controlled Hall-voltage amplifier that produces an analog signal voltage Vsig having excursions of one polarity corresponding to the passing of magnetic articles. The gain of an AGC Vsig amplifier is only decreased in small sequential gain increments during an initial interval defined as that in which two excursions in Vsig have occurred, and the gain remains unchanged thereafter. Vsig is applied to the input of a peak-referenced-threshold signal detector that generates a binary output voltage, Vout, having transitions of one direction and the other direction corresponding respectively to the approach and retreat of the passing articles. The peak-referenced-threshold signal detector includes a dual-threshold-voltage comparator which is set to a large threshold at start-up.

Abstract: A circuit (11) for tracking rapid changes in peak and trough voltages of a data signal includes a peak detector circuit (13) and a trough detector circuit (14) coupled to the input for detecting peaks and troughs in the data signal and providing a peak and trough detect output signals, respectively. A peak level rate of change detector (17) is coupled to the peak detector circuit (13) for detecting a rate of increase in the voltage level of detected peaks and to the trough detector circuit (14) for controlling the trough detector circuit to detect troughs when the voltage level of detected peaks rises rapidly. Similarly, a trough level rate of change detector (18) is coupled to the trough detector circuit (14) for detecting a rate of decrease in the voltage level of detected troughs and to the peak detector circuit (13) for controlling the peak detector circuit (13) to detect peaks when the voltage level of detected troughs falls rapidly.

Abstract: An integrating circuit internally included in a semiconductor device includes a constant voltage circuit 11 for generating a predetermined constant voltage VREF, and a voltage-to-current converting circuit 12 for converting the voltage VREF into a constant current I0, which is supplied to a capacitor 15 externally connected to a connection terminal CPT. In order to detect an integral potential charged in the capacitor 15, a voltage comparator 14 having one input connected to the capacitor connection terminal CPT and the other input connected to an input terminal IN for receiving a signal VIN to be measured, inverts its output voltage when both the input voltages becomes consistent with each other. The integrating circuit also includes a switching circuit 13 having an input connected to an output terminal of the constant voltage circuit 11, an output connected to the capacitor connection terminal CPT.

Abstract: A method for measuring the rise/fall time and pulse width of RF pulses using multi-purpose, commercial-off-the-shelf test devices, such as an RF signal down converter, a digitizer and a signal processor. The method is based on digitizing the RF signals and developing an average sample pulse waveform. The rise/fall time and pulse width are then calculated from data points on the sample waveform. The method is suitable for real-time calculations of the rise/fall time and pulse width.

Abstract: A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitu

Abstract: A logic filtered address transition detection circuit that receives a chip select signal and an ATD pulse, and which produces an internal clock pulse using:an AND gate, a filtered input terminal, a delay unit and a comparator unit. The AND gate outputs an AND logic signal after processing the chip select signal and ATD pulse, the filtered input terminal and delay unit both receive the AND logic signal from the AND gate; and send their signals to the comparator unit. The comparator unit performs a logic function on the AND logic signal and a delayed AND logic signal to produce the internal clock signal.

Abstract: A drive circuit includes first and second circuit sections. The first circuit section maintains, during an initial stage of a transient period of an input signal, its output level before the signal transition and supplies after the transient period an output signal responsive to the signal transition. The second circuit section has a first circuit portion receiving the input signal and a second circuit portion, responsive to the input signal, and the output of the first circuit section, to accelerate the signal transition of the first circuit portion. Signal delay in a signal transition due to a large parasitic capacitance and resistance can be recovered by the drive circuit. The drive circuit has a large noise margin and operates at a high-speed and in a wide frequency range.

Abstract: A digital resampling system is provided for converting a first digital signal to a second digital signal, where both signals represent the same analog signal but sampled at two different clock rates which are not phase-locked together. A filter is clocked by the first clock and outputs filtered samples at the first clock rate, optionally omitting samples which will not be used. A phase indicator determines the relative phase position of the first and second clocks and indicates an integer phase value and a fractional phase value which together indicate where a tick of the second clock falls among the ticks of the first clock. The integer phase value identifies a clock cycle of the first clock in which a tick of the second clock occurs, and the fractional phase value represents a fraction identifying a position of the tick of the second clock within the clock cycle of the first clock. A sample selector selects M filtered samples from those provided by the non-decimating filter based on the integer phase value.

Abstract: An address transition detection (ATD) circuit provides an address transition detection pulse in response to either a high-to-low or low-to-high external address transition. The ATD circuit includes an address buffer that translates an externally applied address signal into an internal address signal and its logical complement. Two delay chains, each of which includes inverters, capacitors, a NAND gate and a CMOS pass gate, combine with the address buffer and an n-channel pull-down transistor to provide the ATD circuit. The outputs of the CMOS pass-gates are connected to the gate of the pull-down transistor. The drain of the pull-down transistor serves as the local ATD node of a dual-load feed-back controlled ATD pulse generator. The ATD local node is common to address buffers that select memory cells within a particular memory block. Address buffers responsible for switching between blocks have separate feedback-controlled ATD pulse generators in order to optimize the access time of the memory device.

Abstract: An apparatus and method for a transition detector and pulse width qualifying circuit for a differential receiver. The circuit generates pulses at every transition of a differential input signal and asserts a time-out signal upon detection of an end-of-transmission delimiter pulse. The circuit also detects true or inverted linkpulses.

Abstract: A rate of change comparator uses an RC charging circuit and a separate RC discharging circuit to follow a transducer output. The resistor component of each RC circuit is shunted by a diode, each biased in a different orientation so that the charging circuit charges quickly through its diode but discharges slowly through its resistor and the discharging circuit discharges quickly through its diode and slowly through its resistor. The difference in output between the charging and discharging circuits is detected with a comparator, biased off by a threshold bias voltage developed from one of the circuits. The comparator is unaffected by slow changes in transducer signals due to drift, ambient condition and similar changes because the differential voltage between the circuits is minimized for transducer signal changes below the level set by a threshold bias level.

Abstract: Two edge detectors (12, 13) at the input (10.1) and the output (10.2) of a delay line (10) of the edge detector arrangement (11) generate detection signals of identical shape at the detected signal edges of a signal traveling over the delay line. The delay time of the delay line is selected so that the two detection signals partly overlap in time. A subtraction arrangement (16) generates, from the two detection signals, a difference signal that contains, in the overlap region, a zero crossing that can be detected by a zero crossing detector (17). At the time of this zero crossing, the zero crossing detector generates the switching edge of an edge detection signal that controls, for example, a signal switcher (9).

Abstract: A circuit for detecting the transition of the state of logic signals at a plurality of input terminals is provided. The circuit has a transition detecting block connected to each input terminal which generates a pulse at the transition of a logic signal at the input terminal, an OR logic block connected to each transition detecting block for generating a combined logic signal from the transition detecting blocks, and a latch having SET and RESET input nodes and an output node. The SET input node is connected to the OR logic block so that the output node switches into a first logic state from a second logic state responsive to the combined logic signal on the SET input node. The circuit also has a delay unit connected to the OR logic block and to the RESET input node of the latch which precisely delays the combined logic signal to the RESET input node so that the output node of the latch switches back to the second logic state.