Abstract: Apparatuses and techniques for operating devices with multiple differential write clock signals having different phases are described. For example, a memory controller (e.g., of a host device) can provide two differential write clock signals to a memory device over an interconnect. The two differential write clock signals may have a phase offset of approximately ninety degrees. Instead of generating its own phase-delayed write clock signals using a component (e.g., a clock divider circuit) that can enter the metastable state, the memory device can use the multiple differential write clocks signals provided by the memory controller to process memory requests.

Abstract: Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

Abstract: The embodiments of the present disclosure provide a reset method, a reset device, a reset system and a pixel array using the same. The reset method includes an electric charge accumulation unit being configured to store a first electric charge and an electric charge storage unit being configured to store a second electric charge. A polarity of the first electric charge is opposite to a polarity of the second electric charge. The reset method includes controlling the electric charge storage unit to obtain the second electric charge; and resetting the electric charge accumulation unit so as to transfer a preset amount of the second electric charge from the electric charge storage unit to the electric charge accumulation unit, which includes a third port of the control module applying a control voltage to a second end of the electric charge storage unit; and meanwhile charging the electric charge storage unit during the process of transferring the second electric charge.

Abstract: A semiconductor apparatus including a sudden power detection circuit, a power-on reset circuit, and a driving circuit. The sudden power detection circuit configured to detect an external power supply voltage and generate a sudden power detection signal. The power-on reset circuit configured to detect the voltage level of the external power supply voltage according to a reset reference voltage and generate a power-on reset signal. The driving circuit configured to perform a sudden power-off operation and a power-on reset operation.

Abstract: Methods, apparatus, and systems are disclosed for voltage supervisors. An example apparatus includes a first switch having a first source, a first drain, and a first gate, a first resistor having a first terminal and a second terminal, the first terminal coupled to the first source and second terminal coupled to the first drain, a second resistor having a third terminal and a fourth terminal, the third terminal coupled to the second terminal, a third resistor having a fifth terminal and a sixth terminal, the fifth terminal coupled to the fourth terminal, a fourth resistor having a seventh terminal and an eighth terminal, the seventh terminal coupled to the sixth terminal, a second switch having a second source, a second drain, and a second gate, the second source coupled to the seventh terminal, and a comparator having an output, the output coupled to the first gate and the second gate.

Abstract: A method of detecting a cold-boot attack on an integrated circuit, including the steps of: periodically sampling a signal delivered by at least one ring oscillator; and verifying that the proportion of states “1” and of states “0” of the result of the sampling is within a range of values.

Abstract: A driver circuit and corresponding methods and systems are disclosed, the driver circuit comprises a signal generation circuit to generate a linearly varying signal at a first node based on a clock signal and an output transistor to receive the linearly varying signal and output a drive signal to a bus. A buffer amplifier is coupled between the first node and a gate of the output transistor to disable the gate capacitance of the output transistor. The driver circuit further comprises a capacitor coupled between the first node and a feedback node of the driver circuit such that the Miller effect occurs at the capacitor and a slew rate for the drive signal is generated at the feedback node.

Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.

Abstract: A system-on-chip (SoC) is provided that includes security control registers, the security control registers including security flags for security critical assets of the SoC, wherein each security flag includes multiple bits. A set of security critical bits is signaled from a configuration storage of the SoC with a set of validation bits to be used to validate the set of security critical bits.

Abstract: A phase lock loop (PLL) includes a phase detector configured to output a signal indicative of a phase difference between a reference signal and a feedback signal, a loop filter configured to filter an output of the phase detector, and a voltage-controlled oscillator (VCO) configured to output an oscillating signal having a frequency corresponding to an output of the loop filter. The PLL further includes a frequency divider configured to output the feedback signal by frequency dividing the oscillating signal output by the VCO, and a reset circuit configured to reset the frequency divider in an initialization mode such that a phase difference between the reference signal and the feedback signal corresponds to a lock angle of the PLL.

Abstract: A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency.

Abstract: A dynamic flip flop is provided. The dynamic flip-flop comprises a transmission gate, a first inverter, a second inverter, a pull-up transistor and a pull-down transistor. The pull-up transistor and the pull-down transistor constitute a feedback inverter, and the feedback inverter is configured as a weak keeper circuit compared to the first inverter serving as a tri-state inverter. Therefore, the dynamic flip-flop can be such that makes a master latch to use the tri-state inverter for capturing data in order to reduce electric leakage. In addition, the dynamic flip-flop can also be such that makes a slave latch to use the weak keeper circuit for storing data, thereby avoiding floating point to drive the output.

Abstract: A driver circuit and corresponding methods and systems are disclosed, the driver circuit comprises a signal generation circuit to generate a linearly varying signal at a first node based on a clock signal and an output transistor to receive the linearly varying signal and output a drive signal to a bus. A buffer amplifier is coupled between the first node and a gate of the output transistor to disable the gate capacitance of the output transistor. The driver circuit further comprises a capacitor coupled between the first node and a feedback node of the driver circuit such that the Miller effect occurs at the capacitor and a slew rate for the drive signal is generated at the feedback node.

Abstract: In described examples, an integrated circuit comprising a first pin and a second pin. A switchable resistive element is coupled between the first pin and the second pin and has a pull down resistance state or a high resistance state. A comparator has a first comparator input coupled with the first pin, a reference signal input, and a comparator output. A logic circuit has an input coupled with the comparator output, an internal power good signal input, and a control signal output. The control signal output is coupled with the switchable resistive element to select the pull down resistance state or the high resistance state.

Abstract: A dual voltage power system for selectively providing direct current (DC) at two different voltages. The system includes a plurality of universal rectifiers each of which may be configured to operate under a plurality of operating modes using a plurality of switches which may be controlled by a power shelf controller.

Abstract: A semiconductor device and a method of generating a power-on reset signal are provided. The semiconductor device includes a regulator configured to generate a regulated power supply voltage having a lower voltage value than a power supply voltage based on the power supply voltage and output the regulated power supply voltage to an internal power supply line, and a power-on reset circuit configured to generate a signal which has a first level at which reset is prompted immediately after power for the power supply voltage is turned on and which transitions to a second level at which reset release is prompted from the first level when a voltage value of the internal power supply line has risen as a power-on reset signal.

Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.

Abstract: A technique for providing electric power to an electric power utility grid includes driving an electric power alternator coupled to the grid with a spark-ignited or direct injection internal combustion engine; detecting a change in electrical loading of the alternator; in response to the change, adjusting parameters of the engine and/or generator to adjust power provided by the engine. In one further forms of this technique, the adjusting of parameters for the engine includes retarding spark timing and/or interrupting the spark ignition; reducing or retarding direct injection timing or fuel amount and/or interrupting the direct injection; and/or the adjusting of parameters for the generator including increasing the field of the alternator or adding an electrical load.

Abstract: A system for storing transducer information in a memory device includes a memory device connected with a transducer by a circuit that enables a meter or data acquisition circuit to access transducer signals and the transducer information from the memory device over a single pair of wires.

Abstract: The disclosure is directed to a power drop reset circuit which includes not limited to: a first step circuit configured to detect a change of a power supply voltage per unit of time and transmit an enable signal in response to the first step circuit having determined that the change of the power supply voltage per unit of time has dropped below zero, wherein the first step circuit does not consume any current when the Vcc change per unit of time is greater than or equal to zero; and a second step circuit electrically connected to the first step circuit and configured to detect the Vcc in response to having received the enable signal and generate a power drop reset signal in response to having determined that the Vcc has dropped below a predetermined operating voltage, wherein the second step circuit consumes an operating current after receiving the enable signal.

Abstract: A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function(Vtp,Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp,Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.

Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.

Abstract: Hardware may be created with different clock speeds used for different components of the system. Clock and throughput requirements on the interface circuitry of hardware components may set limits which are lower requirements for functional components. It may be advantageous to use more or fewer of some functional blocks or interface circuits in order to reduce cost, increase performance or reliability, reduce the requirements for additional parts, or other beneficial factors. Accordingly, it may be advantageous to generate hardware utilizing more than a single clock frequency. Generating instructions which indicate different clock frequencies for separate components may be difficult or time consuming; generating these instructions automatically may provide significant benefits in time savings, increased productivity, increased performance of hardware, or other benefits.

Abstract: An electronic apparatus includes a first processor and a second processor. The first processor includes a detection unit to detect output of an internal-reset occurrence signal from the second processor, and an identification unit to identify, as a source of the internal reset, the second processor in response to the internal-reset occurrence signal and an input of an identification signal from the second processor. The second processor includes an internal reset unit to internally reset the second processor in response to a malfunction of the second processor, a reset occurrence signal output unit to output the internal-reset occurrence signal in response to occurrence of the internal reset of the second processor, and an identification signal output unit to output, to the first processor, the identification signal indicating the source of the internal reset, in response to the occurrence of the internal reset of the second processor.

Abstract: A power-on reset circuit arranged to generate a reset signal according to a power supply voltage includes: a power supply voltage detector, a holding circuit, a reference voltage generator and a reset determination circuit. The power supply voltage detector is controllable by the reset signal, and arranged to detect a level of the power supply voltage to generate a detection signal. The holding circuit is arranged to output an enablement signal according to the detection signal, wherein the holding circuit selectively maintains a level of the enablement signal according to a level of the detection signal. The reference voltage generator is controllable by the enablement signal to selectively output a reference voltage. The reset determination circuit is arranged to output the reset signal according to the power supply voltage and the reference voltage.

Abstract: A microcontroller unit (MCU) is provided. The MCU includes a reset circuit, a clock circuit, a detection circuit, a counter and a control circuit. The detection circuit detects a first EFT event, and when a first EFT event is detected, the detection circuit generates a first block signal. The counter is coupled to the detection circuit, and when the counter receives the first block signal, the counter starts to count. The control circuit is coupled to the reset circuit, the clock circuit and the counter, and receives the first block signal from the counter. When the control circuit receives the first block signal, the control circuit maintains output signals of the reset circuit and the clock circuit in a prior state, in which the output signals have not been influenced by the first EFT event, until the count number of the counter reaches a default value.

Abstract: A method can be used for managing the operation of a phase-locked loop. The loop includes an oscillator voltage controlled by a control signal and a phase comparator receiving a reference signal and a feedback signal which arises from the output signal of the oscillator. The method includes a detection of a possible absence of transitions on the feedback signal for a first duration and, in response to such an absence, a forcing of the lowering of the voltage of the control signal at least until a reappearance of transitions on the feedback signal.

Abstract: A power-on reset (POR) circuit with an auxiliary control circuit and an enhanced resistor ladder for brownouts circuit detectors in low power applications includes a power-up detector circuit for detecting power supply ramp-up while charging; a brownout detector circuit for sensing power supply falling down; a set-reset (SR) latch to generate a power-on-reset (POR) signal; a start-up network; and an internal band-gap voltage reference circuit, wherein the internal band-gap voltage reference circuit is configured to be started by the start-up network to serve as a reference for the power-up detector circuit.

Abstract: An enable circuit includes a first detection controller, a second detection controller, and an enable switch. The first detection controller has a first input terminal coupled to a first input terminal voltage and a first output terminal. The second detection controller has a second input terminal coupled to the first input terminal voltage and a second output terminal. The enable switch has a control terminal coupled to the second output terminal, a third input terminal coupled to a second input terminal voltage, and a third output terminal. When the first input terminal voltage is higher than the first setting voltage but lower than the second setting voltage, the enable circuit is coupled to ground by the second output terminal, thus the enable switch is turned on to output an enable signal from the third output terminal, wherein the enable signal is provided by a second input terminal voltage.

Abstract: Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in the present disclosure. An example apparatus includes a first circuit configured to receive a supply voltage and further configured to provide an active first signal responsive to the supply voltage exceeding a threshold voltage. The example apparatus further includes a second circuit coupled to the first circuit and activated by the active first signal, the second circuit configured to provide an active second signal when a third circuit is ready for operation.

Abstract: A scannable data synchronizer including an input circuit, first and second pass gates, first and second inverters, and a gate controller. The input circuit drives the data nodes to opposite logic states in response to an asynchronous input data signal in a normal mode and in response to scan data in a scan test mode. Each pass gate is coupled between one of the data nodes and a corresponding one of the capture nodes, and each has at least one control terminal. The inverters are cross-coupled between the second capture nodes. The gate controller can keep the pass gates at least partially open during a metastable condition of the capture nodes, and can close the pass gates when both capture nodes stabilize to opposite logic states. In the scan test mode, the scan data is used to test the latch or register functions of the scannable data synchronizer.

Abstract: A semiconductor device includes an input determination circuit. The input determination circuit includes: a comparator that is driven based on a first reference potential and includes an input voltage terminal and a reference voltage terminal; a reference voltage generation circuit that inputs a reference voltage that is generated from a connection point between a constant current source and a resistor to the reference voltage terminal of the comparator, the constant current source and the resistor being interposed between a second reference potential that is separated from the first reference potential and a third potential that is higher than the first reference potential and the second reference potential; and a first low pass filter that is interposed between a signal input system that is connected to the input voltage terminal of the comparator and the second reference potential.

Abstract: Various features pertain to defending a smartphone processor or other device from a transient fault attack. In one example, the processor is equipped to detect transient faults using a fault detection system and to adaptively adjust a control parameter in response to the transient faults, where the control parameter controls a physical operation of the processor (such as by gating its clock signal) or a functional operation of the fault detection system (such as a particular Software Fault Sensor (SFS) employed to detect transient faults). In some examples, in response to each newly detected fault, the detection system is controlled to consume more processor time to become more aggressive in detecting additional faults. This serves to quickly escalate fault detection in response to an on-going attack to promptly detect the attack so that the device can be disabled to prevent loss of sensitive information, such as security keys or passcodes.

Abstract: A power-on reset signal generating apparatus and a voltage detection circuit thereof are provided. The voltage detection circuit includes a latch circuit, a pre-charge circuit, a pull-down switch and an output stage circuit. The pull-down circuit is turned on or cut off according to the power-on reset signal. The pre-charge circuit operates a pre-charge action according to a power-on reset signal or a power supply voltage. The output stage circuit receives the power supply voltage, based on the power supply voltage, generates a detection output voltage according to an input end of the inverter and the power-on reset signal.

Abstract: A switched mode power converter has an energy transfer element that delivers an output signal to a load. A power switching device coupled to the primary side of the energy transfer element regulates a transfer of energy to the load. A secondary controller is coupled to receive a feedback signal and output a pulsed signal in response thereto. A primary controller is coupled to receive the pulsed signal and output a drive signal in response thereto, the drive signal being coupled to control switching of the power switching device. A compensation circuit generates an adaptively compensated signal synchronous with the pulsed signal. The adaptively compensated signal has a parameter that is adaptively adjusted in response to a comparison of the feedback signal with a threshold reference signal. The parameter converges towards a final value that produces a desired level of the output signal.

Abstract: A power-on-detection (POD) circuit includes a detection circuit, first and second comparison circuits, and logic circuitry. The detection circuit includes a capacitor configured to charge from a first voltage level to a second voltage level. The first comparison circuit is configured to compare a third voltage level to a reference voltage level, and the second comparison circuit is configured to compare a fourth voltage level to the reference voltage level. The third and fourth levels are based on the second voltage level. The logic circuitry is coupled to an output of the first comparison circuit and to an output of the second comparison circuit and is configured to output a power identification signal based on the outputs of the first and second comparison circuits. The detection circuit is configured to turn on the first and second comparison circuits based on a voltage level of the capacitor.

Abstract: A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.

Abstract: A gate drive circuit includes a first switch electrically coupled to a single-supply input voltage node, the first switch electrically coupling the voltage node with a first capacitor if switched on; a second switch electrically coupled to a ground node, the second switch electrically coupling the first capacitor with the ground node if switched on; and the first capacitor. A first capacitor lead of the first capacitor is electrically coupled to the first and second switches and a second capacitor lead of the first capacitor is arranged to connect with a power transistor gate.

Abstract: A power-on control circuit controlling a first output switch and a second output switch is provided. A detecting circuit detects a first voltage to generate a detection signal to a first node. A switching circuit receives the first voltage and a second voltage and transmits the first or second voltage to a second node according to the voltage level of the first node. A setting circuit generates a feedback signal to the first node according to a voltage level of the second node. When the first voltage reaches a first pre-determined value and the second voltage has not reached a second pre-determined value, the switching circuit transmits the second voltage to the second node. When the second voltage reaches the second pre-determined value, the switching circuit transmits the first voltage to the second node.

Abstract: A method for determining performance of an integrated circuit (IC) is disclosed herein. The method includes following operations: disposing hardware performance monitors (HPMs) in each of ICs, in which each of HPMs generates a value for generating the performance of the IC; providing a performance function including of terms according to values generated by the HPMs, in which a weight is associated with each of terms; determining the weight of each of terms according to a first set of ICs of the ICs, wherein the performance of each of the ICs is known; and determining the performance of a first ICs of the ICs according to the performance function, wherein the performance function and the weights are built into the first ICs.

Abstract: Dynamic magnetic stripe communications devices are provided as magnetic stripe emulators on a card or device having one or more communication channels. An application specific integrated circuit (ASIC) may include one or more waveform generators that include spike suppression circuitry to reduce excessive signal excursions during power-up and/or activation of the one or more communication channels on the card or device. Data to be communicated by the magnetic stripe emulator may be encoded within the one or more waveforms and communicated to a magnetic stripe reader.

Abstract: An arbitrating circuit includes a first NOR gate, a second NOR gate, four resistors and a pull-up circuit. The first transistor is connected with the first node and the second node, and generates a first acknowledging signal. The second transistor is connected with a supply voltage, the second node and the first transistor. The third transistor is connected with the first node and second node, and generates a second acknowledging signal. The fourth transistor is connected with the supply voltage, the first node and the third transistor. The pull-up circuit is connected with the first node, the second node, the first NOR gate and the second NOR gate. If both of the first request signal and the second request signal have a low logic level, a voltage at the second node is pulled up to a high logic level by the pull-up circuit.

Abstract: A low voltage crystal oscillator (XTAL) driver with feedback controlled duty cycling for ultra low power biases an amplifier for an XTAL in the sub-threshold operating regime. A feedback control scheme can be used to bias the amplifier for an XTAL biased in the sub-threshold operating regime. The amplifier of a XTAL oscillator can be duty cycled to save power, e.g., the XTAL driver can be turned off to save power when the amplitude of the XTAL oscillation reaches a maximum value in range; but be turned back on when the amplitude of the XTAL oscillation starts to decay, to maintain the oscillation before it stops. In addition or alternatively, a feedback control scheme to duty cycle the amplifier of a XTAL oscillator can be used to monitor the amplitude of the oscillation.

Abstract: A semiconductor device may include a boot-up operation circuit configured for executing a boot-up operation during a boot-up operation period after a power supply voltage signal reaches a predetermined level. The boot-up operation circuit may be configured for generating a boot-up period signal. The boot-up period signal may be enabled during the boot-up operation period. The semiconductor device may include a sensing circuit configured for sensing the boot-up period signal and a clock enablement signal to generate a first detection signal and a second detection signal. The semiconductor device may include an initialization circuit configured for executing an initialization operation in response to the first and second detection signals. Related semiconductor systems may also be provided.

Abstract: Techniques are disclosed relating to generating an overdrive voltage for power switch circuitry. In some embodiments, the value of the overdrive voltage is adjusted dynamically in order to reduce leakage current during power gating. In some embodiments, an apparatus includes a power switch circuit element configured to gate power to circuitry in the apparatus based on a control signal. In some embodiments, the power switch circuit element is powered by a supply voltage. In some embodiments, the apparatus also includes control circuitry configured to generate the control voltage at a different voltage level than the supply voltage, based on comparison of leakage current of ones of a plurality of replicas of the power switch circuit element. In some embodiments, the replicas are configured to receive different reference voltages as respective replica control signals. In various embodiments, the disclosed techniques may generate overdrive voltages that reduce leakage current during power gating.

Abstract: Provided are a semiconductor device including a modulator for PSK communication and a semiconductor device including a demodulator for PSK communication, and a PSK communication system. The semiconductor device includes a reference clock generator to generate a reference clock signal, a phase locked loop (PLL) to receive the reference clock signal and generate a first clock signal, an integer divider circuit to generate a second clock signal by delaying a rising edge of the reference clock signal by a product of a predetermined integer value included in transmission data and a phase interval, and a processing unit to generate a first transmission signal. The first transmission signal is phase-shifted from a first rising edge of the second clock signal. The phase interval is dependent on a ratio of the frequency of the first clock signal to the frequency of the reference clock signal.

Abstract: A retention mode sequential logic circuit has no balloon latch, and all its P-channel transistors are disposed in a single N-well. In one example, the circuit is a retention flip-flop that has an active high retention signal input and an active low reset input. In another example, the circuit is a retention flip-flop that has an active low retention signal input and an active low reset input. In a multi-bit retention register example, one common clock and reset signal generation logic circuit drives multiple pairs of latches. Each retention mode logic circuit described has a low transistor count, is implemented with a single N-well, exhibits low retention mode power consumption, is not responsive to a reset signal in the retention mode, and has a fast response time when coming out of retention mode operation.

Abstract: Techniques are disclosed for managing the timing between two asynchronous clocks. The techniques are particularly well-suited for synchronizing the reference clock with the divided clock in a phase coherent DSM PLL application, but can be more broadly applied to any application that includes a need for synchronizing a data bus across a clock boundary. In one example embodiment, the techniques are implemented in a retime word circuit operatively coupled between a DSM and the divide-by-N integer divider of a PLL application. The retime word circuit receives the divide word from the DSM and generates a retimed divide word that can be applied to the divider. The retime word circuit maintains the reference clock frequency throughput, and forces the divide word seen by the divider to change only at end of a given divide cycle.

Abstract: An electronic apparatus and method for determining a reset thereof are provided. The electronic apparatus includes a switch, a sensor, a reset circuitry and a control circuitry. The switch generates a trigger signal as being triggered. The sensor senses a property of an object or an environment external to the electronic apparatus and to provide a sensing information based on the sensed property. The reset circuitry is coupled to the switch and counts from an initial value to a predetermined value when keep receiving the trigger signal from the switch, wherein the reset circuitry further resets the electronic apparatus when counting to the predetermined value. The control circuitry is coupled to the switch, the sensor and the reset circuit and generates a control signal, based on the sensing information, for controlling the reset circuit to re-count from the initial value to the predetermined value.