Abstract: A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.

Abstract: An apparatus and method for synchronizing and tracking an input data stream and for generating a synchronous clock therefrom, comprising means for generating a plurality of clock signals oscillating at substantially the same frequency, but with different phases; a plurality of delay lines having a common data input for receiving said input data stream, each delay line having multiple delay elements connected in series and having a common clock input for receiving one of said clock signals for clocking data of said data stream along said delay line in a direction away from said common data input; means for detecting which of said plurality of delay lines said data from said data stream is propagating therein; and means for generating the synchronous clock based on one of said clock signals that clocks the delay line that data from said data stream is propagating therein.

Abstract: Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate and receiving a clock signal having a first clock frequency, and alternating between a first level and a second level. The data signal is stored when the clock signal alternates from the first level to the second level, and the stored data signal is provided as a first signal a first amount of time later. The first signal is stored when the clock signal alternates from the first level to the second level, and the stored first signal is provided as a second signal a second amount of time later. A third signal is provided by delaying the first signal for a third amount of time. The third signal is stored when the clock signal alternates from the second level to the first level, and the stored third signal is provided as a fourth signal a fourth amount of time later. A fifth signal is provided by delaying the data signal a fifth amount of time.

Abstract: The present invention is a novel method and apparatus for implementing a high-precision timer utilizing a non-optimal oscillator and a high-speed oscillator wherein only one oscillator is enabled at a given moment in time. The high-precision timer method and apparatus comprises a timer and an error-correction technique. In one embodiment, the timer of the present invention is constructed from a high-speed oscillator and a low-speed non-optimal oscillator. The timer operates from the high-speed oscillator during on-the-air modes of operation and from the low-speed non-optimal oscillator during sleep modes of operation. The present inventive method corrects errors that are introduced by the non-optimal oscillator and a swallow counter. The errors are corrected using an error-correction technique having two steps: an error-determination step and an error-correction step.

Abstract: A synchronous delay circuit apparatus include two sets of synchronous delay circuits 100, 101 each including a first delay circuit chain for period measurement in which input clocks propagate and a second delay circuit chain for period reproduction and delay detection circuits 5, 7 for detecting the propagation delay time caused in propagating clocks from an input node to an output node of a clock propagation path to issue a control signal for halting propagation of the input clock signals to the respective synchronous delay circuits. A delay circuit 6 is introduced in an input of at least one 7 of the delay detection circuits to differentiate a delay time detected in one delay detection circuit 7 from a delay time detected by the other delay detection circuit 5 to differentiate detected period from the delay detected in the other delay detection circuit 5.

Abstract: A clock recovery circuit is provided for use in a memory with a clock synchronized interface or the like, wherein an external clock is temporarily intercepted to shorten the lock-in time when an internal clock is to be generated from the external clock. The clock recovery circuit includes a delay circuit array, into which an external clock is inputted, for generating a plurality of reference clocks, a control circuit for comparing the phases of the external clock and of the plurality of reference clocks and detecting the number of delay stages of the delay circuits required for locking in, and latching circuit for holding the number of delay stages required for locking in. Once synchronism is detected and the number of delay stages required for locking in are held in the latching circuit, the generation of the internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.

Abstract: A digital PLL circuit is formed by a first digital PLL circuit, a signal generation circuit that generates a plurality of signals that have the same frequency as the output of the first PLL circuit but differing phases, and the second digital PLL circuit having a signal selecting circuit that can select the signals from the signal generation circuit, a frequency divider circuit that divides the output signal of the signal selecting circuit, a phase comparator circuit that compares the phase between the a signal used as a reference and the output signal from the frequency divider circuit, an up/down counter that detects the phase difference of the phase comparison circuit, and a digital filter that is provided between the up/down counter and the signal selecting circuit, the second PLL circuit selecting the signals from the signal generation circuit based on the output from the up/down counter.

Abstract: An apparatus and method for distributing a clock signal within circuitry disposed on a number of separate system cards includes a first system card that generates a reference clock signal representative of a fixed delay of a system clock signal. A number of variable clock signals are produced using the system clock signal. Each of a number of system cards separate from the first system card receive one of the variable clock signals. A delay associated with the reference clock signal is typically longer than a delay associated with each of the variable clock signals. The phase of each of the variable clock signals is adjusted to a substantially in-phase relationship with respect to the reference clock signal in response to a phase difference between the reference clock signal an output signal received from each of the separate system cards.

Abstract: A synchronization circuit for gradually shifting the phase domain of a control signal to permit synchronization of a signal with a clock signal in a different phase domain in a system with a single frequency, but arbitrary phase relationship. The present invention allows a control signal in the phase domain of an internal clock to be synchronized with an external clock, when the phase domain of the external clock differs substantially from that of the internal clock. In synchronizing the control signal to the external clock, the present invention avoids the generation of runt pulses while providing a control signal synchronized to the external clock in the least amount of time feasible (i.e., with the lowest latency time). Because the present invention has no failure modes due to timing relationships, MTBF is infinite for failures caused by such relationships and therefore need not be a concern. This also implies that no risk is posed to the proper operation of the circuits driven thereby.

Abstract: The delay unit has first delay elements each having a first delay time and second delay elements each having a second delay time. The second delay time is greater than the first delay time. A control unit controls the delay time of the delay unit by, first, incrementally increasing or by incrementally reducing the number of second delay elements in the signal path and thereby altering the actual value of the delay in the direction towards a desired (setpoint) value until the desired value is exceeded. The control unit then, by incrementally reducing or increasing, respectively, the number of first delay elements in the signal path, alters the actual value of the delay in the direction towards the desired value until the desired value is exceeded once more. In the event of subsequent changes in the desired value or in the actual value, the number of first delay elements is incrementally altered, while the number of second delay elements in the signal path is kept constant.

Abstract: A clock generation circuit is provided within an electronic computer system to adjust the phase of a clocking signal provided to various subsystems of the electronic system. A first phase-locked loop (PLL) is provided to establish multiple phases of a first reference clock. One of those phases is selected as a second reference clock, and a second PLL synchronizes the clocking signal to that second reference clock. Each subsystem and associated load which receives the clocking signal has a corresponding clock generation circuit comprising the second PLL. The second PLL for one subsystem can adjust the clocking signal phase prior to that subsystem receiving the clocking signal. The amount by which the second PLL adjusts phase on clocking signal may be different than that by which another, second PLL adjusts the clocking signal arriving on another subsystem.

Abstract: A high resolution delay line includes a coarse delay having a minimum period of delay and a fine delay having a total delay, wherein the total delay is equal to or greater than half the minimum period. Each delay can be implemented in analog or digital form and the delay line can be implemented with one portion in analog form and the remainder in digital form. The digital delay can provide a delay upward of 1,500 milliseconds. The fine delay provides a resolution of ten microseconds or less. An unknown delay is measured by coupling a signal into two channels, wherein the first channel includes the unknown delay and the second channel includes the coarse delay and the fine delay. The output signals from the channels are correlated while adjusting the coarse delay for maximum correlation and then adjusting the fine delay for maximum correlation.

Abstract: A conversion (20, 120, 220) system for converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) in a communications system (10), the conversion system (20, 120, 220) including an oversampled analog-to-digital converter modulator (24, 124, 224) for receiving an oversampling-clock signal (29, 129, 229) and a transmitted analog signal (18, 118, 218), the oversampled analog-to-digital converter modulator (24, 124, 224) operable to sample the analog signal (18, 118, 218) and to convert the analog signal (18, 118, 218) to a first digital signal (32, 132, 232), a time adjustor (41, 141, 241) coupled to the oversampled analog-to-digital converter modulator (24, 124, 224) for receiving the first digital signal (32, 132, 232) and a first adjustment signal (48, 148, 248), and for producing an output digital signal (54, 154, 254), and a digital signal processor unit (56, 156, 256) coupled to the time adjustor (41, 141, 241) for receiving the output digital signal (54, 154, 254) and performing timing

Abstract: Digital signal processing circuitry implemented in ASICs or FPGAs is built by combining multi-component constructs (e.g. macrocells). These circuits may be modified to include a timing channel by augmenting selected ones of the constructs to include a path which propagates a timing signal with a delay that compensates for the signal processing delay through the construct. The selected constructs are those that are used in a critical processing path in the digital signal processing circuitry. A timing compensation circuit may also be defined as a construct. This block receives two digital data signals having accompanying timing signals and delays the first signal that provides valid data until the second signal also provides valid data, as determined by their timing signals. A configurable arithmetic and logic unit (ALU) made using these techniques includes a timing compensation circuit, a look-up table and an accumulator.

Abstract: A clock control circuit receives an external clock signal and generates an internal clock signal. Through use of internal programming and an external trigger signal, the clock control circuit blocks out one or more of the clock cycles of the external clock signal to generate the internal clock signal. The clock control circuit can be used in any semiconductor device, and especially in synchronous flash memory devices with a burst operation. In the synchronous flash memory devices, one or more of the internal clock cycles are blocked out to account for increased delays during certain data sensing operations such as word line switching during data reading. In the synchronous flash memory devices, the sensed data is stored in input/output buffers and transferred out synchronously to the external clock signal.

Abstract: An apparatus for deskewing clock signals in a synchronous digital system. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates an output based on a phase relationship between those clock signals. A controller then receives the output of the phase detector and determines which one of the plurality of clock signals requires adjustment based on the output of the phase detector and a bit from a delay shift register. The controller transmits a delay signal to one of a plurality of delay circuits which modifies the delay of the clock signal that the controller determined to require adjustment.

Abstract: An apparatus and method for synchronizing and tracking an input data stream and for generating a synchronous clock therefrom, comprising means for generating a plurality of clock signals oscillating at substantially the same frequency, but with different phases; a plurality of delay lines having a common data input for receiving said input data stream, each delay line having multiple delay elements connected in series and having a common clock input for receiving one of said clock signals for clocking data of said data stream along said delay line in a direction away from said common data input; means for detecting which of said plurality of delay lines said data from said data stream is propagating therein; and means for generating the synchronous clock based on one of said clock signals that clocks the delay line that data from said data stream is propagating therein.

Abstract: Device for delaying a clock signal using a ring delay is disclosed. The device can include a delay for delaying an external clock signal eCLK as much as time delays d1+d2 of a time delay d1 occurring on reception and a time delay d2 occurring on driving an output buffer, a pulse generator for receiving the clock signal from the delay and generating rectangular pulses synchronous to rising edges, and a ring delay having a plurality of unit delays connected in a ring form for delaying and circulating the pulse signal generated in the pulse generator as well as latching a signal from each unit delay synchronous to the clock signal rCLK received in the chip. The first clock signal delay is for delaying the clock signal rCLK in a course corresponding to a number of circulation, and a second clock signal delay is for making a fine delay of the clock signal from the first clock signal delay in response to a latch signal from the ring delay.

Abstract: A synchronous delay circuit of multiplex configuration is disclosed that has a delay time that corresponds to the pulse separation immediately preceding input of the pulse signal. For the purpose of reducing dependence of the delay time differential between the delay signal and the external clock signal upon the external clock signal cycle, the multiplex synchronous delay circuit of this invention is provided with a plurality of synchronous delay circuits; a delay time differential than is smaller that the delay time of each gate section of the delay circuit bank that makes up each of these synchronous delay circuit is arranged at the input/output portion of the signal path of the synchronous delay circuits, and the outputs of these synchronous delay circuits are multiplexed by their logic output.

Abstract: (1) A bit phase adjusting circuit receives input data Din and passes it to a first group of delay gates which are connected in series to generate a set of data available for selection, the set including the input data Din and the input Din delayed by different amounts. The bit phase adjusting circuit selects one of the data from this set and outputs it to a bit change detecting circuit having a second group of delay gates which are connected in series. (2) In the bit change detecting circuit, at a time controlled by a reference clock signal, it is judged whether or not the input and the output data of a pth-stage delay gate of the second delay gate group coincide with each other and whether or not the output data of the pth-stage delay gate and a (p+1)th-stage delay gate coincide with each other. A change point detecting signal is generated which shows whether or not a change point of the output data from the pth-stage delay gate is within a specified range before and after the judgement time.

Abstract: A clock signal generator having a pre-phase converter for generating in response to an input clock signal a plurality of pre-delay clock signals with different phases; and main phase converters each of which receives one of the pre-delay clock signals, and generates a plurality of main delay clock signals with their phases different from each other, thereby generating multiple main delay clock signals with their phases different from each other.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: A chip-to-chip Cycle Alignment Circuit is implemented on the CP chip with a phased lock loop so that a chip knows what is the cycle of a connected chip. Once the PLL is locked, the timing relationship is developed between a reference oscillator and the 3.5 ns on-chip clock which clocks three latches (latch 1,2,3). The Cycle Alignment Circuit has a first part for a rising edge detecting clock chopper and the second part for a self resetting toggle latch. The rising edge detecting clock chopper works by detecting the reference oscillator's rising edge after it has gone through a small delay. The purpose of this delay is to ensure that a latch 1 detects the rising edge on the second 3.5 ns cycle after the reference oscillator rises. A latch 2 is then used to generate a one (3.5 ns) cycle pulse at point that starts on the second 3.5 ns cycle and ends on the third 3.5 ns cycle. The pulse that is produced at that point forces a latch 3 to be reset to a 1 at the beginning of cycle 3.

Abstract: The circuit of the present invention prevents a multi-locking phenomenon, reduces power consumption and provides an accurately locked internal clock signal. A delay unit sequentially delays an external clock signal through a plurality of unit delay terminals. A sampling and computation unit maintains the levels of signals from the unit delay terminals connected after a predetermined unit delay terminal, in which a locking phenomenon occurs, to a predetermined level when a delay clock signal among a plurality of delay clock signals from the unit delay terminals is locked. An output unit outputs a delay clock signal locked to an external clock signal in accordance with an output from the sampling and computation unit.

Abstract: An improved clock signal modeling circuit capable of more quickly generating an internal clock signal in an external clock signal without using a phase locked loop and a delay locked loop, which includes a delay unit for receiving an external clock signal and for outputting a delay clock sinal; a sampling unit for receiving the delay clock signal and for sampling in accordance with an external clock signal; a comparing unit for receiving the output of the sampling unit and for sequentially comparing the output; and an output unit for receiving the delay clock signal outputted from the delay unit and for outputting an internal clock signal in accordance with an output signal of the comparing unit and an externally applied switching signal.

Abstract: The present invention provides a high speed digital data retiming apparatus, in which, in binary data bits transmitted at a high speed, the data can be retimed in a stable manner, even if there are present a static skew due to a delay difference between the retiming clock pulse and the data and a dynamic skew due to the characteristic variation according to time and temperature. Therefore, the present invention has the following advantages compared with the conventional apparatus. First, periodical and regular external clock pulses are delayed by means of a delaying section, so that system performance is independent of the pattern of data. Second, even if the data phases show a continuous difference (wandering) for more than a certain period of time, an elastic buffer absorbs the wandering, and therefore, no data loss is generated, with the result that the system is not put to a disorder condition.

Abstract: A synchronization system aligns video signals without the use of a phase locked loop. One embodiment includes a delay line and a selection circuit. A clock signal with a desired frequency for a pixel clock is applied to the delay line to generate a series of delayed signals at taps on the delay line. When a transition in a horizontal sync signal occurs, the selection circuit senses delayed signals and selects a delayed signal having a transition aligned relative to the transition in the horizontal sync signal. This delayed signal is a pixel clock signal which is not subject to frequency fluctuation of a phase locked loop. Selecting a new delayed signal at each horizontal blanking period keeps the pixel clock for each line of video aligned to the horizontal sync signal.

Abstract: A method and system are provided. A clock signal is input and output at first and second nodes of integrated circuitry. The first node is connected through a selected one of a plurality of metallization paths of the integrated circuitry to the second node. Each of the metallization paths is connectable between the first and second nodes for delaying the clock signal by a respective amount of time between the first and second nodes, so that the clock signal at the second node is always delayed relative to the first node by the respective amount of time of the selected metallization path.

Abstract: It is an object to realize a synchronization circuit with small size and low consumption power which enables capturing and phasing of external data without running external clock in parallel. Internal clock (2) is delayed by a delay line (1) to produce delay clocks (3), and one of the delay clocks (3) having its rise almost corresponding to that of an external data signal (6) becomes a select clock (5). An elastic store circuit (7) is a circuit which controls a row of D-latches with a row of C elements. Thus the elastic store circuit (7) captures the external data signal (6) with enough set up hold time at timing of the select clock (5) and then outputs the captured external data as an internal data signal (8) in synchronization with the internal clock (2).

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: The present invention provides a delay clock generator where a plurality of stable delay clocks can be generated and digitizing is easy. The delay clock generator comprises first to nth (n: integer not less than 2) delay circuits (11 to 1n) connected in cascade connection for delaying the basic clock (KO) in sequence, a phase comparator (21) for comparing phase of a delay clock from the nth delay circuit (1n) with that of the basic clock, and a delay control circuit (31) for generating a delay control value to make the phase of the delay clock from the nth delay circuit synchronize with that of the basic clock based on a phase comparison result, and for controlling delay amounts of the first to nth delay circuits respectively by the delay control value.

Abstract: A system and method for detecting timing design errors in a design having multiple state devices clocked by multiple clock signals. The design includes at least first and second state devices clocked by first and second clock signals. A reference time is designated, and a time differential between successive triggering edges of the first and second clock signals is calculated. The time of the occurrence of each triggering edge of the first and second clock signal is calculated with respect to the reference time, rather than directly with respect to each other. The calculation of the time differential includes storing a period time and a time offset the first and second clock signals. The time offsets are time durations measured from the reference time to the first pulse of each of the first and second clock signals that occur simultaneously with, or subsequent to, the reference time.

Abstract: A method and apparatus for clocking latches in a system having both pulse latches and two-phase latches includes a clock generating circuit for generating a local clock signal based on a global clock signal and also includes a pulse generating circuit for generating a pulse signal based on the global clock signal. A clock signal path transfers the local clock signal from the clock generating circuit to both a first portion and a second portion of the two-phase latch. Similarly, a pulse signal path transfers the pulse signal from the pulse generating circuit to the pulse latch. According to one embodiment, the pulse generating circuit and the clock generating circuit have paths of equal delay, thereby causing a rising edge of the local clock signal to occur at the same time as a rising edge of the pulse signal.

Abstract: A digital delay line supplies from a periodic input signal n signals with the same period mutually shifted by one n-th of the input signal period. The digital delay line includes n cells, each of which includes m delay elements in series, each output of a delay element being connected to an input of a multiplexer. The output phase of the n-th cell is compared with that of the input signal phase. The output of a multiplexer of the n cells is modified after each comparison.

Abstract: An improved clock signal modeling circuit capable of more quickly generating an internal clock signal in an external clock signal without using a phase locked loop and a delay locked loop, which includes a delay unit for receiving an external clock signal and for outputting a delay clock signal; a sampling unit for receiving the delay clock signal and for sampling in accordance with an external clock signal; a comparing unit for receiving the output of the sampling unit and for sequentially comparing the output; and an output unit for receiving the delay clock signal outputted from the delay unit and for outputting an internal clock signal in accordance with an output signal of the comparing unit and an externally applied switching signal.

Abstract: A digital delay line supplies from a periodic input signal n signals with the same period mutually shifted by one n-th of the input signal period. The digital delay line includes n cells, each of which includes m delay elements in series, each output of a delay element being connected to an input of a multiplexer. The output phase of the n-th cell is compared with that of the input signal phase. The output of a multiplexer of the n cells is modified after each comparison.

Abstract: A data transfer apparatus includes a transmitting apparatus having a pulse generation circuit for generating a plurality of data and a clock having a predetermined timing relation to the plurality of data, a receiving apparatus having latch circuits supplied with the clock and data for latching the plurality of data at a timing of the clock, respectively, transmission lines for connecting the transmitting apparatus and the receiving apparatus, a variable delay circuit for delaying the clock or data to be supplied to the latch circuits, and a variable delay control circuit for controlling an amount of delay of the variable delay circuit by means of output signals of the latch circuits to thereby minimize the cycle time of the data and clock in the data transfer between apparatuses.

Abstract: A synchronization mechanism for synchronizing an outside clock with a delayed inside clock is provided. The delayed inside clock is distributed across a network of clock lines within the integrated circuit to deskew the clock signal at the supply points. Although the inside clock signal is deskewed, it is nevertheless delayed compared to an input clock signal provided by a pad of the integrated circuit. A distribution line provided on the periphery of the integrated circuit supplies an outside clock signal that is not substantially delayed compared to the input clock signal at the IC's pad. The synchronization mechanism provides synchronization between the outside clock, as received by an input/output block, and the inside clock. The synchronization is required because configurable logic blocks (CLBs) of the IC are typically referenced by the delayed inside clock.

Abstract: A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay chain is sampled once each clock cycle, and the point to which the wave has progressed is encoded. Programmable, fine leading and fine trailing edge registers store, as a fraction of the clock cycle time, the desired locations of the timing signal leading and trailing edge relative to the clock edges.

Abstract: A circuit for providing a phase controlled clock output includes a ring oscillator having a delay line for providing an internal clock signal whose period varies with on-chip variations due to temperature, voltage, and process. The circuit also includes a clock phase select circuit having a counter and divider for determining the number of delays in one external clock period and an input for a phase select value. A delay line having delay elements similar to those of the ring oscillator provides multiple delayed clock signals from the reference clock signal. A multiplexor having odd and even sides is used to select the desired clock signal in a glitchless manner. The phase controlled clock signal output is controlled by the phase select signal and is compensated for on-chip variations due to temperature, voltage, and process.

Abstract: A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay chain is sampled once each clock cycle, and the point to which the wave has progressed is encoded. Programmable, fine leading and fine trailing edge registers store, as a fraction of the clock cycle time, the desired locations of the timing signal leading and trailing edge relative to the clock edges.

Abstract: The invention is a delay locked loop circuit comprising a delay line with an input signal and a plurality of tap outputs, and a selector to select from a range of tap outputs. Each tap outputs a delayed copy of the input signal. The invention further comprises a comparator to compare the input signal to an ouput signal, and to output an indication of the phase difference between the signals. A detector coupled to the tap outputs detects a transition from a first predetermined signal level output by a first tap output to a second predetermined signal level output by a second tap output. The detector outputs an indication of the tap outputs between which the transition first occurs to a range determiner. The determiner determines a range of tap outputs to select from and outputs the determined range to the selector. The selector selects a tap output within the range, the selected tap output becoming the output signal.

Abstract: Disclosed is a clock distributing apparatus for distributing clock signals with a desired phase to each of devices provided between a clock generating section (10) for generating clock signals and a plurality of devices (30) for receiving the clock signals. A delay generating section (21) generates a plurality of delay clock signals by imparting a plurality of delay quantities to the clock signals from the clock generating section. A clock distributing section (22) has a plurality of input terminals corresponding to the plurality of delay clock signals and a plurality of output terminals corresponding to the respective devices. The clock distributing section (22) distributes desired delay clock signals to one or more output terminals by selecting the input terminals corresponding to the desired delay clock signals.

Abstract: A data processing system having a first circuit and a second circuit that together control a third circuit by a respective first control signal and a second control signal. The first circuit issues a request signal to the second circuit to trigger initiation of the operation of the third circuit and the second circuit returns a grant signal to the first circuit to indicate that operation of the third circuit has completed. An advance controller within the second circuit serves to start to synchronize the grant signal back to the clock signal of the first circuit at one of a plurality of possible times that is selected to match the relative frequencies of the clock signals driving the first circuit and the second circuit.

Abstract: A data phase alignment circuit (34) is provided to align incoming plesiochronous data with a known clock phase. Multiple phases of a clock signal are provided to a data capture circuit (40), which captures the incoming plesiochronous data with at least one of the clock phases. A data transition decoder (44) then determines the time of data transition with respect to the multiple phases of the clock. The captured data is then realigned with a selected phase of the multiple clock phases by a data retimer circuit (50) and provided as the output (64). The resultant data is therefore aligned with a known phase of the clock signal and is no longer plesiochronous with respect to the clock signal. Data shifting due to data jitter, drift and wander may also be correct with a slip buffer (38).

Abstract: The present invention provides a voltage controlled oscillating circuit comprising a multi-staged phase inversion circuit composed of 4 or more even-number stages of phase inversion devices connected in series; and a switch circuit having a delay time characteristic similar to that of said phase inversion circuit, wherein the switch circuit satisfies oscillation conditions by converting an output phase of the even-numbered inverters connected in series into a phase that is the same as those of the outputs of odd-numbered inverters connected in series; thereby obtaining timing signals having a period equal to 1/N of the oscillation period.

Abstract: A frequency dividing circuit/delay circuit is provided to generate a plurality of system clock signals according to the combination of frequency division and the delay based on a fast-speed basic clock signal to determine according to the address signal from a central processing unit (CPU) what the operating cycle of the slave is to select a system clock of optimum frequency or duty ratio for that slave. As a result, it becomes possible to shorten the time required for executing one cycle and, hence, to improve the performance of the whole personal computer system.