Abstract: Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The time delay ensures proper setup and hold time parameters for the second clock domain relative to the first clock domain. A differentiator generates output information in the second clock domain by delaying the second domain accumulation and subtracting the delayed second domain accumulation from the second domain accumulation. The systems and methods preserve temporal characteristics of the input information in the first clock domain when it is transferred to the second clock domain as the output information.

Abstract: A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from an input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates a final output clock having a phase between phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: In some embodiments, a synchronizing circuit includes at least one synchronization device that operates at a lower clock frequency than another synchronization device in the synchronization circuit. In at least one embodiment of the invention, a method includes sampling a first signal at a first frequency to thereby generate a plurality of sampled versions of the first signal. The first frequency is a frequency of a clock signal divided by N. N is a number greater than one. The method includes sampling a second signal at the frequency of the clock signal. The second signal is based on sequentially selected ones of the plurality of sampled versions of the first signal to thereby generate an output version of the first signal.

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract: A method for sending and receiving a clock and an apparatus for transmitting the clock. Several kinds of clocks are encoded and framed at a sending port so that the clocks needed by all modes of base stations are transmitted in one pair of interconnecting lines. A receiving port can precisely recover the needed clock out. This not only reduces the number of interconnecting lines on the backboard and improves flexibility, but also avoids that the clock decoded out by the receiving port might be imprecise.

Abstract: Circuits, demultiplexers, and methods are disclosed. A circuit includes a reference clock input to receive clock pulses at a reference clock speed. An internal divided clock input receives a divided clock signal from a clock divider that is driven by the clock pulses. The clock divider generates the divided clock signal at a second clock speed that is a fraction of the reference clock speed. An external divided clock input receives an external divided clock signal. The external divided clock signal is driven by the clock pulses and operates at the second clock speed. A clock transition synchronization circuit suppresses application of one or more of the clock pulses to the clock divider when the divided clock signal transitions between clock states out of synchronization with the external divided clock signal.

Abstract: Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional apparatus, systems, and methods are disclosed.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A clock divider for a DLL circuit reduces power consumption by reducing the number of times of performing phase comparison in the DLL circuit when a synchronous memory device is in a power-down mode. The clock divider includes M dividers and a power-down controller for receiving an output signal of the (M?1)-th divider and an output signal of the M-th divider and selectively outputting the output signals. Each divider divides the clock signal frequency inputted to the divider by ½. The output signal frequency of the power-down controller is obtained by dividing the frequency of the clock signal inputted to the first divider into ½M or ½(M-1) depending on the logic level of a control signal, which is indicative of the power down mode of the memory device.

Abstract: Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock signals including those having 90, 180, 270 and 360 degrees phase difference with a first clock signal. One of the intermediate clock signals may be used as an enable signal to guide locking of all signals. For example, the 180 degree clock signal may be inverted and used as an enable signal to guide locking of the initial and 360 degree signals in a single phase adjustment procedure. The 0 and 360 degree signals may be delayed before their phase is compared to compensate for duty cycle error in the clock signals.

Abstract: A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.

Abstract: One inventive aspect relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimizing the influence of another digital sub-circuit on the at least partially digital circuit, the other digital sub-circuit being part of the at least partially digital circuit. The influence of the other digital sub-circuit may, for example, be the introduction of ground bounce by switching of the other digital sub-circuit. Another inventive aspect relates to an at least partially digital circuit comprising such a digital sub-circuit for minimizing the influence of another digital sub-circuit to the at least partially digital circuit and to a method for reducing the influence of another digital sub-circuit to an at least partially digital circuit.

Abstract: A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals including those having 90, 180, 270 and 360 degrees phase difference with a first signal. The rising edge of an intermediate signal is compared with the rising edges of two of the other signals to generate an UP and DN pulse signal, respectively. The UP and DN signals are used to adjust the delay of a delay line producing the signals to synchronize the signals. In some embodiments, a reset signal generator is used to truncate the UP or DN signal pulse.

Abstract: A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.

Abstract: A pulse width modulation (PWM) signal generator generates multiple output PWM signals from an input PWM signal. The output PWM signals are synchronized to synchronization events. Each output PWM signal has a duty ratio substantially equal to the duty ratio of the input PWM signal, and each output PWM signal has a fixed phase-shift in relation to the other output PWM signals. The PWM signal generator samples an input PWM cycle to determine sample parameters representative of its duty ratio. The sample parameters are then used to generate a corresponding output PWM cycle for each of the output PWM signals. In response to a synchronization event, the PWM signal generator prematurely terminates the current PWM cycle and initiates the next PWM cycle while ensuring that the portion of the current output PWM cycle completed by the leading output PWM signal up to the point of the premature termination is replicated for the corresponding output PWM cycles of the other non-leading output PWM signals.

Abstract: A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.

Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Abstract: Methods, circuits and systems for balanced distribution of source-synchronous clock signals are described. Multiple data sets together with one or more clock signals associated with the multiple data sets may be received at a number of interface devices. The multiple data sets may be captured in a number of data buffers. The clock signals may be programmably distributed to a group of the multiple data buffers that retain the one or more data sets, using a balanced clock network. Additional methods, circuits, and systems are disclosed.

Abstract: Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed.

Abstract: Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

Abstract: A PLL frequency generator is disclosed for generating an output signal with a settable target frequency, comprising a) a voltage-controlled oscillator for generating the output signal depending on a control voltage, b) a switchable frequency divider, which is connected to the voltage-controlled oscillator and is designed to derive a frequency-divided signal whose instantaneous frequency depends on a value of an adjustable divisor, from the output signal c) a switchable delay unit, which is connected to the frequency divider and is designed to generate a delayed signal in that the frequency-divided signal is delayed by delay times that in each case depend on a control word and a control signal, and d) a phase detector, which is connected to the switchable delay unit and is designed to determine the phase difference between a reference signal and the delayed signal and to provide it for the generation of the control voltage.

Abstract: A metastability hardened synchronizer circuit includes a plurality of transmission gates, each transmission gate responsive to an input signal and a clock signal to generate a driver signal. The synchronizer circuit also includes a plurality of latches. The plurality of latches includes a first one of the latches in electrical communication with any one of the plurality of transmission gates and responsive to a driver signal to resolve to a stable state and a second one of the latches in electrical communication with another transmission gate of the plurality of transmission gates and responsive to another driver signal to resolve to the stable state.

Abstract: A signal adjusting system includes: a signal generating device for generating a plurality of output signals according to a plurality of pre-output signals, a plurality of signal transmitting paths being coupled to the signal generating device for transmitting the plurality of output signals; and a controlling device coupled to the plurality of signal transmitting paths for receiving a first transmitted signal corresponding to a first output signal and a second transmitted signal corresponding to a second output signal, and detecting a phase different between the first transmitted signal and the second transmitted signal to generate a detected result to the signal generating device, wherein the signal generating device adjusts the phase difference between the first output signal and the second output signal according to the detected result.

Abstract: A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

Abstract: A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit.

Abstract: A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal.

Abstract: A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector compares the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases. A controller synchronizes the rising edge of the rising clock with the rising edge of the reference clock according to the first detection signal of the first phase detector. A second phase detector compares the phases of the synchronized rising clock and the synchronization clock to output a second detection signal corresponding to the compared phases. The DLL apparatus compensates for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.

Abstract: A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.

Abstract: In an embodiment, a method is disclosed that includes receiving a clock signal at a delay chain of a circuit device and determining a value of the clock signal at a selected point within the delay chain. The method also includes adjusting the selected point when the value does not indicate detection of an edge of the clock signal.

Abstract: A data outputting apparatus of a semiconductor integrated circuit if presented for use in standardizing output timing brought about by different electrical output path lengths. The apparatus includes a data clock signal generating section and a data output section. The data clock signal generating section is configured to use an external clock signal in order to generate a plurality of data clock signals in which output timings of the data clock signals vary depending on a data output mode. The data output section is configured to be controlled by the plurality of data clock signals to output inputted data to the outside through a plurality of data input/output pads that have different path lengths.

Abstract: A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit.

Abstract: Deskewing method and apparatus, including: an up/down detection unit samples a received data signal and determines in which of first through third areas of the data signal the logic level of the data signal transitions by using the result of the sampling, a lower limit detection unit detects a lower limit of the first area if the logic level of the data signal transitions in the first area, an upper limit detection unit detects an upper limit of the third area if the logic level of the data signal transitions in the third area, a phase detection unit determines a delay amount according to the upper limit detected by the upper limit detection unit and the lower limit detected by the lower limit detection unit, a buffer unit delays the data signal by the delay amount determined by the phase detection unit.

Abstract: Methods and apparatus are provided for digital compensation of clock timing errors in a VCDL. Clock timing errors in a clock and data recovery system having a voltage controlled delay loop comprised of a plurality of delay elements are compensated for by evaluating a phase of data recovered from an input signal; generating one or more uncompensated clock phase adjustment values based on the phase evaluation; generating one or more compensation terms that compensate for a non-ideal delay for one or more of the delay elements; and determining an adjustment to one or more clock phases produced by the voltage controlled delay loop based on the uncompensated clock phase adjustment values and the one or more compensation terms. The one or more compensation terms can be subtracted from the uncompensated clock phase adjustment values to generate the adjustment to the one or more clock phases.

Abstract: Embodiments for positioning rising and/or filling edges of data strobe signals are disclosed. One example embodiment may comprise receiving a data signal, positioning an edge of a first delayed data strobe signal associated with the data signal by a first programmable amount, and positioning an edge of a second delayed data strobe signal associated with the data signal by a second programmable amount, wherein the second delayed data strobe signal is shifted approximately one bit-time in relation to the first delayed data strobe signal.

Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Abstract: A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.

Abstract: A control signal generation circuit includes a pulse signal generator configured to delay a column control signal by delay times different from each other and to generate first and second pulse signals, a reset signal generator configured to transfer alternatively the first and second pulse signals as a reset signal in response to a write/read flag signal, and a write-enable signal generator configured to generate a write-enable signal from the first pulse signal in response to the write/read flag signal.

Abstract: Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed.

Abstract: A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.

Abstract: Delay lock loop circuits are described, which may include two or more delay stages that each includes a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, which provides a first output. The first output drives an input of the second delay stage, which provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the values maintained in the first and second selector registers are synchronized to the first and second outputs, respectively.

Abstract: A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal enabled in synchronization with a rising edge of a second period of a first clock after the reference enable signal is enabled, a first output unit configured to receive the reference enable signal and the first clock to generate a first internal clock, and a second output unit configured to receive the delayed enable signal and the second clock to generate a second internal clock.

Abstract: A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output.

Abstract: A multi-phase clock generator circuit receives an input clock signal and produces multiple output clock signal, each from a respective delay stage of a multi-stage voltage-controlled delay line (VCDL). The rising edges of the multiple output clock signals produced by the circuit are substantially equidistant in time from one another and have substantially equal phase spacing.

Abstract: A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line.

Abstract: According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.

Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract: A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal, each having timing characteristics, and differentiating between four conditions based upon the timing characteristics of the signals. The phase detector and associated circuitry then determines, based upon the timing characteristics of the signals, which of a number of phase conditions the signals are in. Selectors select the signals to be introduced into the synchronous mirror delay or delay-locked loop by the timing characteristics of the phase conditions. The system is able to utilize the falling clock edge of the clock input signal, and the lock time is decreased under specific phase conditions.