Abstract: An apparatus and method for synchronizing a triggered system to a triggering system by tracking the timing of rising and falling edges of a clock signal at the triggered system and using the tracked timing values for phase shift adjustment of a time base at the triggered systems.

Abstract: A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.

Abstract: A sequence signal generator and a sequence signal generation method are provided. In the sequence signal generation method, a waveform output instruction sent by a host computer is received to acquire waveform data. The waveform data includes original square wave sequence data and target square wave sequence data, and the target square wave sequence data includes a preliminary delay parameter and a secondary delay parameter. An original square wave sequence signal is acquired according to the original square wave sequence data. According to the preliminary delay parameter, preliminary delay processing is performed on the original square wave sequence signal to acquire an intermediate square wave sequence signal, and according to the secondary delay parameter, secondary delay processing is performed on the intermediate square wave sequence signal to acquire a target square wave sequence signal.

Abstract: An interface connection apparatus disposed in a first electronic device is provided that includes an analog physical layer circuit, a waveform generation circuit and a media access control circuit. The analog physical layer circuit receives an analog handshake signal from a second electronic device and generates a digital handshake signal. The waveform generation circuit determines whether a matching times that a pulse parameter of each of pulses included in the digital handshake signal is within a predetermined pulse parameter range reaches predetermine times and generates a digital output signal when the matching times reaches the predetermine times, and an output pulse parameter of all output pulses of the digital output signal is within the predetermined pulse parameter range. The media access control circuit determines that the analog handshake signal is valid when the media access control circuit receives the digital output signal to keep performing handshake.

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

Abstract: An example process for aligning channels in automatic test equipment (ATE) includes programming a first delay associated with receiving first data over a channel so that timing of the channel is aligned to timings of other channels in the ATE; programming a second delay associated with a driver driving second data over the channel based on receipt of an edge of the second data so that timing of the second data is aligned to the timing of the channel; and programming a third delay associated with a signal to enable the driver to drive the second data over the channel, with the third delay being programmed to align timing of the signal to the timing of the channel, and with the third delay being based on an edge that corresponds to an edge of the signal created by controlling operation of the driver.

Abstract: An electronic circuit is configured to output an output signal after elapse of a predetermined time from a received trigger signal, and includes an oscillator configured to output a pulse signal having a predetermined oscillation frequency; a counter circuit configured to count the pulse signal from the oscillator upon receiving the trigger signal and to output the output signal in response to a count value reaching a predetermined value; and a trimming circuit including a plurality of trimming elements which includes a cuttable conductive part and configured to output a selection signal corresponding to a trimming element having a cut conductive part. In the trimming circuit, the trimming element, which corresponds to the oscillation frequency of the pulse signal output from the oscillator among the plurality of trimming elements, is cut, and the counter circuit is configured to set the predetermined value according to the selection signal.

Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.

Abstract: A new computational machine is invented, called a clock machine, that is a novel alternative to computing machines (digital computers) based on logic gates. In an embodiment, computation is performed with one or more clock machines that use time. In an embodiment, a cryptographic cipher is implemented with random clock machines, constructed from a non-deterministic process, wherein the compiled set of instructions (i.e., the implementation of the cryptographic procedure) is distinct on each device or chip that executes the cryptographic cipher. In an embodiment, by using a different set of clock machines to execute two different instances of the same cryptographic procedure, each execution of a procedure looks different to malware that may try to infect and subvert the cryptographic procedure. This cryptographic process also makes timing attacks more challenging. In an embodiment, a detailed implementation of the Midori cipher with random clock machines is described.

Abstract: A synchronization circuit may include: a variable delay circuit configured to delay a first clock signal by a varied delay time according to delay control signals, and configured to output a delayed signal of the variable delay circuit as a second clock signal; a phase detector configured to generate a phase detection signal by detecting a phase difference between the first and second clock signals; and a delay control circuit configured to perform a phase unstable period detection operation according to the phase detection signal, and configured to perform a delay skip operation to adjust the delay control signals such that a phase unstable period, detected in the phase unstable period detection operation, is skipped in a delay time tuning operation.

Abstract: A memory device includes a memory array including a plurality of memory cells; and an array timer coupled to the memory array, configured to generate an output timing signal based on a V-I stable input and an analog reference signal, wherein: the V-I stable input is from a bandgap supply circuit, the analog reference signal is from an analog reference block, and the output timing signal is configured to control the memory array.

Abstract: According to an embodiment, a semiconductor device may be provided. The semiconductor device may include an internal clock generation circuit configured to generate a plurality of internal clock signals respectively from a plurality of division clock signals. The semiconductor device may include a data input and output (I/O) circuit configured to output input data as output data in synchronization with the plurality of internal clock signals. Each bit of the output data may be outputted in sequential order in synchronization with an internal clock signal from the plurality of internal clock signals.

Abstract: A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.

Abstract: Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.

Abstract: A method for analyzing the behavior of an integrated circuit implemented by computer comprises: the extraction of the names of the physical components described at the RTL (or higher) level, therefore of the physical components represented, as well as the names of the modules; the extraction of the names of the physical components of a path of the circuit at the logic gate level; the labeling of the names of the physical components of the paths with the names of the known physical components or the names of the parent modules; the extraction of the physical parameters of results of simulation/analysis of the circuit at the higher level. The output is composed of associative arrays containing the physical parameters of the physical components described at the envisaged level; the assignment of the physical parameters determined in the previous step, to the labeled components of the paths.

Abstract: A timer block includes: a digital control block including a mode selector and a register loading a time delay; a counter coupled to the register of the digital control block, wherein the counter loads a counter value corresponding to the time delay based on an operational mode selected by the mode selector and generates a digital output indicating the counter value that is decremented at each clock; and a pulse generator configured to generate a pulse signal based on the counter value of the counter. The timer block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper that is configured to provide signals between the timer block and the programmable fabric. The operational mode of the timer block is programmably configured using the programmable fabric and the signal wrapper.

Abstract: An improved method and apparatus for performing power management in a memory device is disclosed.

Abstract: The Direct Synchronization of Synthesized Clock (DSSC) contributes a method, system and apparatus for reliable and inexpensive synthesis of inherently stable local clock synchronized to a referencing signal received from an external source. Such local clock can be synchronized to a referencing frame or a data signal received from wireless or wired communication link and can be utilized for synchronizing local data transmitter or data receiver. Such DSSC can be particularly useful in OFDM systems such as LTE/WiMAX/WiFI or Powerline/ADSL/VDSL, since it can secure lower power consumption, better noise immunity and much more reliable and faster receiver tuning than those enabled by conventional solutions.

Abstract: A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.

Abstract: A circuit for processing data in an integrated circuit device comprises a selection circuit; a first register coupled to a first output of the selection circuit; a second register implemented as a latch and coupled to a second output of the selection circuit; and a signal line coupled between the output of the first register and an input of the selection circuit. The selection circuit enables the coupling of an output signal of the first register to an input of the second register. A method of processing data in an integrated circuit device is also disclosed.

Abstract: A circuit device includes a drive circuit that drives a physical quantity transducer, an FLL circuit that includes a frequency comparator and an oscillator, and generates a clock signal with a signal from the drive circuit as a reference clock signal, and a detection circuit that includes a circuit operated based on the clock signal, and performs detection processing on a detection signal from the physical quantity transducer.

Abstract: Disclosed herein is an apparatus for driving a gyro sensor including a driving displacement signal processing unit, a sensing signal processing unit and an automatic quadrature signal controller configured to control the variable resistor through digital correction when a quadrature signal exists, and minimize an amplitude of the quadrature signal.

Abstract: A circuit for producing USB host working clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a USB host interface, and a frequency division controller. According to the frequency multiplier providing clock, the USB host interface configures with USB peripherals for responding. The frequency division controller is connected to the USB host interface and the controllable frequency divider. The USB host interface transmits a response result that the USB host interface configures with USB peripherals for responding to the frequency division controller. According to the USB host interface feeding back the response result, the frequency division controller regulates a frequency dividing ratio of the controllable frequency divider in set scope of the frequency dividing ratio.

Abstract: A control logic of a switched DC-to-DC converter allows continuous switching to bring the DC-to-DC converter to a final output value during a startup phase, it allows skipping of clock switching pulses if they are not needed and allows burst mode of switching pulses dependent on a load applied to the output voltage of the DC-to-DC converter. No digital or analog regulator is required for the control logic.

Abstract: A synchronization apparatus synchronizing an operation of a first processing unit pre-processing an input signal and an operation of a second processing unit post-processing on signal from the first processing unit, may include: a counting unit that operates with a period sufficiently shorter than a period of a first reference signal governing timing of pre-processing in the first processing unit, and outputting, when counting a set target count value, a second reference signal governing timing of post-processing in the second processing unit; a phase control unit that generates a control value controlling a phase difference of the second reference signal with respect to the first reference signal in accordance with a count value when the first reference signal is input; and a filter unit that filters the generated control value so as to determine the target count value to be set in the counting unit.

Abstract: A circuit delay monitoring apparatus has a ring oscillator with a plurality of delay elements, a signal transition being propagated through the delay elements of the ring oscillator, and a plurality N of sampling points being distributed around the ring oscillator. Selection circuitry selects, in dependence on the indication of the current location of the signal transition generated by the fine sampling circuitry, one of the M transition counter circuits whose associated location is greater than said predetermined amount from the current location of the signal transition. Output generation circuitry then generates a count indication for a reference time period dependent on a sampled count value of the transition counter circuit selected by the selection circuitry, the indication of the current location of the signal transition within the ring oscillator, and reference count data relating to the start of the reference time period.

Abstract: A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses.

Abstract: Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked.

Abstract: A clock frequency adjusting system is disclosed. The clock frequency adjusting system includes a sensing clock generating unit, a frequency-dividing unit and a controller. The frequency-dividing unit makes frequency of the sensing clock signal be divided by a frequency-dividing modulus and then outputs a clock calibration signal. The controller includes a period counter and a frequency adjusting unit. The period counter samples the clock calibration signal through the external clock signal so as to acquire a second count value. The frequency adjusting unit calculates a frequency difference data between the clock calibration signal and the predetermined clock signal according to the first count value and the second count value, and determines a number of adjustment according to the frequency difference data and a step adjusting frequency so as to output a clock adjusting signal to the sensing clock unit to adjust frequency of the sensing clock signal.

Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

Abstract: Disclosed are methods and systems of conveying and reproducing independent timebases in a network. The methods include distributing a common measurement clock and a common measurement clock counter to a plurality of cards in a master chassis in the network. Distributed master clock counters are locked to an external input signal in each of the plurality of cards. Periodic snapshots of a count value generated by the master clock counter are taken. A counter speed of the master clock counter is analyzed to create a future snapshot of the count value. The future snapshot of the count value is transmitted from the master chassis to at least one receiving chassis in the network. The association between master counters and slave counters is programmable by various means including modifying the routing of the snapshot packets.

Abstract: A circuit includes a logic circuit, first and second storage circuits, a timing detection circuit, and a compensation circuit. The logic circuit generates a digital value in response to a first periodic signal. The first storage circuit stores time information in response to a second periodic signal. The second storage circuit stores the digital value in response to the second periodic signal. The timing detection circuit generates a detection signal indicating a timing difference between the first periodic signal and the second periodic signal based on the digital value. The compensation circuit generates adjusted time information based on the time information stored in the first storage circuit and the detection signal.

Abstract: A ring oscillator clock automatic synchronization method of a panel driving circuit includes steps of: when a vertical blanking interval happens, a master driver generates a pulse signal to slave drivers respectively. A pulse width of the pulse signal equals to N times of a master ring oscillator clock, wherein N is larger than 0. When a slave driver receives the pulse signal, the slave driver uses its slave ring oscillator clock to count the pulse width of the pulse signal to obtain that the pulse width of the pulse signal equals to M times of the slave ring oscillator clock, wherein M is larger than 0. The slave driver compares M with N and automatically adjusts the slave ring oscillator clock according to the comparison result to make it achieve synchronization with the master ring oscillator clock.

Abstract: In a synchronization system, a frequency divider circuit generates a divided clock by dividing a reference clock in a first division ratio. First and second devices operate in synchronization with the reference clock and the divided clock. A division ratio detection circuit, for each period of the divided clock, detects a division ratio of the divided clock based on a count value counted in synchronization with the reference clock and output the division ratio as a second division ratio. A decoder generates a strobe signal, which is for controlling a timing at which the first device transmits and receives a signal to and from the second device, based on the count value and the second division ratio. The first device communicates with the second device through a bus, which operates in synchronization with the divided clock, based on the strobe signal.

Abstract: A device reduces its energy consumption using a relatively lower frequency and lower power secondary oscillator to maintain timing information when a higher frequency and higher power primary oscillator is inactivated. The secondary oscillator maintains timing information at a higher resolution than the period of the oscillator, so as to conserve synchronization when the higher frequency, higher power primary oscillator is inactivated. In some embodiments, a microsequencer is programmably configured to control an integrated radio receiver and transmitter using less power than an associated microprocessor would use to perform the same functions. In other embodiments, flexible event timing facilitates the merging of wake-up events to reduce the energy consumed by wake-up operations in the device.

Abstract: A method and a system are provided for synchronizing a signal. A keep out window is defined relative to a second clock signal and an edge detection signal is generated that indicates if an edge of a first clock signal is within the keep out window. The edge detection signal may be filtered. An input signal is received in a domain corresponding to the first clock signal and a delayed input signal is generated. Based on the edge detection signal or the filtered edge detection signal, either the input signal or the delayed input signal is selected, to produce an output signal in a domain corresponding to the second clock signal.

Abstract: The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. Out-of-lock detection is accomplished by sampling retimed/recovered data with positive and negative edges of the received data. In example embodiments, an out-of-lock condition is determined either by detecting the occurrence of, or counting, missed edges corresponding to the failure of received data sampling to detect corresponding positive/negative edges of the retimed/recovered data.

Abstract: A semiconductor system includes a controller and a semiconductor device that may communicate signals with the controller through a single input/output pad. The semiconductor device includes a self power generation block that may generate a driving voltage in response to a first signal inputted from the controller through the single input/output pad, and generate a start-up signal when the driving voltage is over a set voltage, a state machine block that may detect a pulse width of a second signal inputted from the controller through the single input/output pad, in response to the start-up signal, and may generate commands and data in response to the pulse width, and a data output block that may convert the data into a third signal of a current level corresponding to the data and output the third signal to the controller through the single input/output pad, in response to the commands.

Abstract: A integrated circuit includes a clock control signal generation circuit configured to generate a clock control signal using transition of a control signal, a clock control unit configured to activate a control clock in an activated period of the clock control signal, and to deactivate the control clock in a deactivated period of the clock control signal, and a control circuit configured to operate in response to the control signal and in synchronization with the control clock.

Abstract: A method for initializing a delay locked loop having a delay circuit includes a plurality of serially connected delay elements and a counter circuit for selecting an output of one of the delay elements as an output clock signal. The method includes resetting an initial delay control circuit, generating, with the initial delay control circuit, a pulse based on a period of an input clock signal, determining, with the initial delay control circuit, a number of delay elements required to produce a delay time at least substantially equivalent to a pulse width for a preset signal, initializing the counter circuit based on the preset signal and adjusting the counter circuit in response to phases of the input and output clock signals.

Abstract: A frequency calibration method for a programmable oscillator includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than a predetermined value; and determining a frequency calibration step of the oversampling signal according to the difference. The present invention further provides a frequency calibration device for a programmable oscillator.

Abstract: The present invention relates to a signal synchronization circuit comprising at least one synchronizer (2.1-2.2) comprising a number N of series connected clock delay elements (3.1-3.3), N being equal to or greater than unity and a clock signal generator (1) arranged for generating a modulated clock signal adapted to clock the clock delay element (3.1-3.3) or elements of the at least one synchronizer (2.1-2.2). The clock generator (1) is arranged to receive a clock signal (5) and at least one operating value (6) and to generate the modulated clock signal (1 out) from the clock signal (5) modified based on the operating value (6).

Abstract: A clock trimming apparatus includes an oscillator, a judging unit, a latching unit, and a tracking unit. The oscillator has an input terminal receiving a bias signal and an output terminal generating a clock signal. After a frequency division is performed on the clock signal, the judging unit generates a frequency-divided signal. If the frequency-divided signal matches the reference signal, a pass signal generated by the judging unit is activated. The latching unit is used for generating a trimming completion signal. After the pass signal is activated, the trimming completion signal is activated. The tracking unit is used for counting a pulse number of the reference signal and providing the bias signal to the oscillator according to a trimming code. After the trimming completion signal is activated, the trimming code is stopped being adjusted.

Abstract: Systems and methods are disclosed relating to semiconductor memory devices. According to some exemplary implementations, there are provided innovations associated with power and ground pads in devices such as static random access memory (“SRAM”) devices and dynamic random access memory (“DRAM”) devices. Moreover, the systems and/or methods may include features such as minimization of simultaneous switching outputs (SSO) effects relating to echo clock circuitry.

Abstract: Groups of phase shifted Pulse Width Modulation signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

Abstract: The invention provides a phase-locked loop with loop gain calibration and methods for measuring an oscillator gain, gain calibration and jitter measurement for a phase-locked loop. The method for measuring an oscillator gain of a phase-locked loop includes the steps of providing a varying code at an input end of the oscillator; outputting excess reference phase information by a reference phase integral path and outputting excess feedback phase information based on the varying code by a feedback phase integral path; and obtaining an estimated gain information of the oscillator based on the excess reference phase information and the excess feedback phase information.

Abstract: A first phase alignment circuit generates an indication of a phase of a first clock signal. A second phase alignment circuit adjusts a phase of a second clock signal based on a data signal. The second phase alignment circuit adjusts the phase of the second clock signal based on the indication of the phase of the first clock signal. The second phase alignment circuit resets an indication of the phase of the second clock signal generated based on the data signal in response to the indication of the phase of the first clock signal. The second phase alignment circuit captures a value of the data signal in response to the second clock signal.

Abstract: The present invention is a noise tolerant communication protocol device and method where a clock signal input, triggers an internal delay clock in an integrated circuit. Data is presented to an input pin and sampled prior to the next external clock pulse based on the internal delay clock. A data pulse value is distinguished by input signal voltage level and not by pulse length. Sampling of data bits is deferred until a signal level is most likely stable, thereby avoiding sampling during periods around edges of changing data values. Therefore, error detection and correction circuitry is not required. A time reference pulse, produced by a bus master, is measured by the protocol device, in determine a data transmission rate by the master. The timing of sampling of input signaling from the master is determined by the protocol, device from measurement of the time reference pulse magnitude.

Abstract: Data transmission circuits are provided. The data transmission circuit includes a control signal generator and an output driver. The control signal generator generates a pull-up control signal and a pull-down control signal by using a count signal that changes in response to a clock signal during a drive control period. The output driver receives an internal data signal and drives a transmission data signal in response to the pull-up control signal and the pull-down control signal.