Abstract: A device and method are disclosed for synthesizing a waveform having pulse segments. An exemplary generator can include units having a time delay element and pulse generator generating the pulse segments. An input divider divides an input signal into signal instances that propagate through the units and an output combiner combines pulse segments to form the waveform. The pulse generators include a sharpening circuit for sharpening a rising edge and a falling edge of the pulse segments. The sharpening circuit includes a tunable delay element coupled to a non-linear transmission line (NLTL). Another NLTL can be coupled in parallel with the tunable delay element and the first NLTL. The NLTLs include input sections coupled to anodes or cathodes of Schottky diode elements, and the respective cathodes or anodes are coupled to a signal ground.

Abstract: The present invention discloses a level shift circuit and a control pulse shaping unit therewith. A level shift circuit for transition of a low-voltage input signal into a high-voltage output signal, the circuit comprising two pairs of transistors and a control unit. Two pairs of transistors, wherein the transistors in one of the pairs are both turned on in response to the input signal so that a voltage on a reference voltage node is coupled to a gate of one of the transistors in the other pair; a control unit decoupling a reference voltage from the reference voltage node during a first phase, and partially and fully coupling the reference voltage to the reference voltage node respectively during a second and third phases.

Abstract: A slew rate calibrating circuit and a slew rate calibrating method are provided which are capable of adjusting, with high accuracy, a slew rate of a signal to be output to a transmission path. A first clock is input and a delay time of a variable delay circuit is increased or decreased so that a phase of the first clock coincides with a phase of a first differential buffer output signal which rises when a voltage of a transmission path outgoing signal is at the same level as a first reference voltage or exceeds the first reference voltage. Then, a second clock is input and a slew rate of an output buffer is increased or decreased so that a phase of the second clock coincides with a phase of a second differential buffer output signal which rises when a voltage of a transmission path output signal is at the same level as a second reference voltage or exceeds the second reference voltage.

Abstract: In a charge-pump booster circuit, the control clock is controlled on a small-step basis to thereby suppress the boost amplitude and the occurrence of various noises. Provided are a charge-pump booster circuit section for boosting an external power voltage in absolute value level, a boost-voltage feedback section for controlling the booster circuit section, and a clock buffer section. In the boost-voltage feedback section, an output level of the booster circuit section is detected by a voltage detecting section. This is compared with a reference level, and depending upon the comparison result, a count operation is made in an up/down counter section. Based on the count value, the control amount is shifted on a small-step basis from the D/A converter section, thereby controlling the power voltage of the clock buffer section 300 through the level shifter section.

Abstract: One embodiment is a clock gater circuit comprising an inverter block for driving an output clock signal responsive at least in part to an input clock signal that is selectively driven via a clock generator circuit to an input node of the inverter block responsive to a qualifier signal. Also included is circuitry for restoring a logic level at the input node of the inverter block to a particular value, the circuitry operating responsive to the qualifier signal.

Abstract: An apparatus for controlling operation of a processor device during startup of the processor device includes: (a) a signal treating circuit receiving a voltage supply signal at a voltage supply locus; the signal treating circuit using the voltage supply signal for generating a first treated signal and a second treated signal; and (b) an output circuit coupled with the signal treating circuit; the output circuit receiving the first treated signal and the second treated signal and generating a control signal at an output locus based upon a relationship between the first treated signal and the second treated signal; the output locus being coupled with the processor device; the control signal effecting the controlling.

Abstract: A low-power, synchronous pulse width modulator utilizes a first clock signal at a first frequency to generate a pulse-width modulated signal at the first frequency without requiring a second over sampling clock signal that has a substantially higher frequency by selecting taps from a phase shifting structure to synthesize the waveform.

Abstract: A pulse duty cycle automatic correction device has a pulse width detector for detecting the high, low level pulse widths of the input cycle pulse so as to generate high, low level signals; a comparator encoder for comparing the high, low level signals, calculating out a correction delay time, and generating a correction delay signal and an output selection signal; a delay circuit for generating a delay cycle pulse; a compensation circuit for compensating the input cycle pulse so as to generate an input compensation pulse; a logic circuit for generating two cycle pulses according to the delay cycle pulse and the input compensation pulse; and a multiplexer for receiving the two cycle pulses and the input cycle pulse, and generating the output cycle pulse with duty cycle of 50% according to the output selection signal.

Abstract: A current-mode synapse multiplier circuit multiplies each of a plurality of pulse signals with each of a corresponding plurality of weight signals. The synapse multiplier includes a plurality of first switches each coupled to a corresponding pulse signal and the corresponding weight signal. An integral circuit is coupled to the first switches to receive the weight signals that pass through the first switches and integrates the sum of the weight signals that pass through the first switches over a period of time. A voltage-to-current (V-I) converter is coupled to the integral circuit to convert the integral of the sum of the weight signals that pass through the first switches into a current signal, wherein the current signal represents the sum of the multiplication products of each pulse signal and the corresponding weight signal. An external reset signal is coupled to the synapse multiplier through a second switch to reset the synapse multiplier.

Abstract: System and method for implementing a clock gater circuit are described. One embodiment is a clock gater circuit comprising an output clock signal generator electrically connected between a clock input for receiving an input clock signal and a clock output; a switch for selectively enabling or disabling generation of a clock signal by the output clock signal generator; and circuitry for causing a voltage level of the clock signal generated by the output clock signal generator to maintain a current voltage thereof responsive to a qualifier signal voltage level.

Abstract: The invention provides an output control apparatus for adjusting the output level of a pulse width modulation (PWM) signal by changing the amplitude level of the output PWM signal. The output control apparatus comprises a control signal generator, a digital-to-analog converter (DAC), and an output circuit. The control signal generator generates a digital control signal. The DAC outputs a predetermined level according to the digital control signal. The output circuit with a negative feedback loop receives the PWM signal and receives the predetermined level by the negative feedback loop. While the PWM signal is logic number “0”, the negative feedback loop is not switched on, so as to control the level of the PWM signal at a base level. While the PWM signal is logic number “1”, the negative feedback loop is switched on, so as to control the level of the PWM signal at the predetermined level.

Abstract: A sequential pulse train generator. Each stage of the sequential pulse train generator includes a dynamic shift register circuit, level shifter, and buffer composed of inverters. The dynamic shift register circuits, allow the pulse generator to operate with a low-voltage clock signal so that power consumption in transmission of the clock signal is reduced.

Abstract: A new magnetic RAM cell device is achieved. The device comprises a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A diode is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.

Abstract: Circuit arrangement and method for producing a pulse width modulated signal A circuit arrangement for producing a PWM signal (x) having a prescribed PWM frequency from two signals (a, b) which are input into the circuit arrangement, where the PWM signal (x) has a duty ratio which varies with the difference between the signals (a, b) comprises a signal generator (16) for producing a cyclic comparison signal, particularly an essentially trapezoidal signal (d), whose frequency is the same as the PWM frequency and whose shape is dependent on one (a) of the two signals (a, b), and a comparator (18) for comparing the other (b) of the two signals (a, b) with the comparison signal (d) and for providing the PWM signal (x) at the output of the comparator.

Abstract: System and method for implementing a clock gater circuit are described. One embodiment is a clock gater circuit comprising an output clock signal generator electrically connected between a clock input for receiving an input clock signal and a clock output; a switch for selectively enabling or disabling generation of a clock signal by the output clock signal generator; and circuitry for causing a voltage level of the clock signal generated by the output clock signal generator to maintain a current voltage thereof responsive to a qualifier signal voltage level.

Abstract: A pulse width detection circuit for accurately detecting a pulse width from an input signal. The detection circuit includes a first filter circuit for receiving the input signal and generating a first processed signal. The first processed signal includes a first component having an AC component of the input signal and a second component having a low frequency component or a DC component of the input signal. A second filter circuit is electrically connected to the first filter circuit. The second filter circuit includes a high pass filter for receiving the first processed signal and generating a second processed signal. A binary conversion circuit is electrically connected to the second filter circuit to receive the second processed signal and generate the binary signal.

Abstract: A circuit, system, and method is provided for regulating the pulse width and/or duty cycle of a signal indirectly or directly used to drive, e.g., a transmitter. The load of the transmitter can be, for example, an optical signal transmitter. The circuit includes a feedback loop that adjusts the output signal so that the lower voltages are chopped at a reference voltage input into the driver. The magnitude of the reference voltage will regulate the pulse width of the output signal, as well as the duty cycle of the output signal. A low input voltage swing is well-suited to be operated upon by the driver circuit to produce a symmetric pulse width that is particularly adapted to high-speed optical data communication applications. The gain and slew rate of the feedback circuit and, predominantly, the comparator and pull-down transistor of the feedback circuit is tuned to ensure the pull-down transistor is always on and, therefore, the comparator will toggle, but within constrained (i.e., regulated) voltage limits.

Abstract: A controllable pulse generator apparatus and method are provided according to the invention. The pulse generator generates an adjustable, high current, high voltage pulse train output that may be transmitted to an external device under operation. The pulse generator includes a controller device and a pulse generator device. The controller device accepts one or more pulse train requests, may accept one or more external signals, and may accept feedback from the device under operation. The controller device generates one or more pulse train signals in response to the pulse train requests, the external signals, and the feedback. The controller device transmits the one or more pulse train signals to the pulse generator device. The pulse generator device receives the one or more pulse train signals and in response generates a pulse train output of a predetermined current level and of a predetermined voltage level according to the one or more pulse train signals.

Abstract: An RF power oscillator for contactless card antennas shapes a carrier signal at the operating frequency utilizing a delay circuit having a number of taps for delaying the carrier signal by different lengths of time. The delayed signals are input into a buffer and output through resistors to a node coupled to the antenna. The resulting waveform for a square wave input signal, and equal-length delay taps, is a trapezoidal wave output. Any input wave form can be shaped in a variety of ways depending upon the combinations of delay taps used. Since the buffer drivers for each delayed wave switch state at slightly different times, the amplitude and bandwidth of emitted electromagnetic interference (EMI) is reduced for the transmission circuit.

Abstract: An apparatus comprising one or more output circuits each configured to configure a pad as either an input/output pad, a power pad, or a ground pad in response to a plurality of configuration inputs.

Abstract: The present invention provides a three-phase pulse width modulation waveform generator having at least an up-down counting circuitry which comprises: an up-down counter for performing an up-count or a down-count upon an external input of a count clock signal; and a count controller having an output side connected to an input side of the up-down counter for sending the input side of the up-down counter a count enable signal which enables the up-down counter to perform the up-count or the down-count.

Abstract: A circuit and method for implementing a configurable clock generator comprising a logic circuit, a configurable matrix and a phase-locked loop. The logic circuit may be configured to generate a plurality of control signals. The configurable matrix may comprise a plurality of interconnections that may be configured to (i) receive the plurality of control signals from the logic circuit and (ii) bus the control signals to the phase-locked loop. The plurality of control signals may control the operation of the phase-locked loop. In one example, the logic circuit may comprise a sea of gates logic array.

Abstract: A circuit for applying a compensating ripple signal at a low voltage point, such as the collector electrode of a travelling wave tube to compensate for pulse-top ripple extant on a high voltage pulse applied at the travelling wave tube cathode, to provide a substantially constant voltage across the travelling wave tube during pulsing to preserve its radio frequency phase and amplitude characteristics. The portion of the pulse-top including the undesired ripple is compared against the applied compensating collector signal and the result is digitized and stored discretely in a plurality of sample bins over the duration of the modulation pulse. The stored digital values are updated over a plurality of successive modulation pulses until an equalibrium is reached, a random access memory being arranged to provide a readout over one half of each of the sample bins and to receive updating in the remaining halves of the corresponding sample bins.

Abstract: A pulse signal output circuit charges and discharges a capacitor in response to a clock signal and outputs a pulse signal having a pulse width determined by a time for charging and discharging the capacitor. A control signal generation circuit outputs a control signal in response to the pulse signal, where the control signal has a first voltage level determined by the pulse width. An output circuit has a first output transistor and a first regulating transistor connected in series between the first power supply node and the output terminal. The first output transistor is operated in response to a signal transferred from inside or outside a semiconductor device, and the first regulating transistor is operated in response to the control signal.

Abstract: A method and system for providing a voltage-sensing preamplifier for use with a magnetoresistive sensor is disclosed. The method includes providing a gain stage and providing a control circuit. The system includes the gain stage and the control circuit. The gain stage includes at least one input device that is coupled with the magnetoresistive sensor through an interconnect having a characteristic impedance. The at least one input device has a first input impedance. The control circuit provides at least one signal to the at least one input device. The at least one signal controls the first input impedance of the at least one input device to control a second input impedance of the voltage-sensing preamplifier, such that the preamplifier input impedance is modified toward the characteristic impedance of the interconnect to improve the bandwidth of the signal amplified by the system.

Abstract: A current pulse generator device includes current pulse generator circuits and polarizer circuits. It further includes holding circuits for holding the polarization voltage connected to the generator circuits, the holding circuits connected via switch circuits to the polarizer circuits. The switch circuits can assume in succession a closed or adjustment position in which they connect the holding circuits to the polarizer circuits, and an open or operating position in which they isolate the holding circuits from the polarizer circuits so that the generator circuits generate at least one low-noise current pulse. The device can be used in a phase comparator and a radiocommunication terminal, and the phase comparator can be used in a synthesiser.

Abstract: A data communication receiving element includes a photo-receiving element for receiving an external light signal and for converting the light signal to a current signal. It further includes an amplifier circuit for amplifying the current signal after converting the current signal to a voltage signal. A waveform shaping circuit is included for shaping an output voltage waveform from the amplifier circuit to a substantially square pulse. Finally, an integrator is included for converting the substantially square pulse to a non-square pulse. This is achieved by extending a rising time necessary for shifting the substantially square pulse from a low potential level to a high potential level, and by extending a falling time necessary for shifting the substantially square pulse from the high potential level to the low potential level. As such, deterioration of an S/N ratio is suppressed.

Abstract: Method and device for generating bit information in a subscriber station of a bus system, in particular of the bus of the EIBA, essentially symmetrical AC voltage information being superposed as bit information on a DC voltage of the bus in that a DC voltage potential (19) of a line under inductive loading (9) is pulled, in each case in an active pulse (20) to the potential of another line and an equalizing pulse (22, 23) is formed with subsequent energy recovery. It is provided that the active pulse (20) of the bit information at a bit frequency is formed from individual pulses (17) of higher frequency.

Abstract: A level converting circuit for an input clock signal having a relatively low amplitude comprising a level converting circuit for converting the input clock signal to an output clock signal having a relatively high amplitude, the level converting circuit having an input transistor which has a predetermined threshold voltage, and detecting/offsetting circuit for detecting the threshold voltage of the input transistor and adding an offset voltage in response to the detected threshold voltage to the input clock signal and then for providing the offset input clock signal to the level converting circuit. The novel setup performs clock interfacing of a thin-film transistor integrated circuit device represented by an active-matrix liquid crystal display device at a relatively high speed at a low voltage below 3 V for example.

Abstract: A voltage stepup circuit having a plurality of setup circuit units connected in stages between an input voltage node and a stepup voltage node. Each circuit unit comprises at least two first and second MOS transistor T1 and T2. Each of first stepup capacitors is connected between a first clock signal supply node and a first connection node at which the drain and gate of a corresponding one of odd-numbered MOS transistors, of a plurality of MOS transistors connected in series through the plurality of stepup circuit units, are connected together. Each of second stepup capacitors is connected between a second connection node at which the drain and gate of a corresponding one of even-numbered MOS transistors of the plurality of MOS transistors connected together and a second clock signal supply node for supplying said second connection node with a second clock signal whose pulse width does not overlap in time with that of the first clock signal.

Abstract: A circuit arrangement with an adjustable amplitude-frequency response between an input signal terminal and an output signal terminal can be changed over simply between a fourth-order high-pass or low-pass characteristic and a second-order all-pass characteristic. The circuit includes first and third filters each with a filter function F, a second filter with a filter function G, a plurality of coefficient sections and first and second summing stages all coupled together so that the circuit has a transfer function A between the input signal terminal and the output signal terminal with a component complying withA=(C+(1-C).multidot.F-2.multidot.C.multidot.G).multidot.(C(1-C).multidot.F) ,whereF=FN=1/(1+a.multidot.s+b.multidot.s.sup.2)orF=FH=b.multidot.s.sup.2 /(1+a.multidot.s+b.multidot.s.sup.2)represents a first filter function with a second-order high-pass or a low-pass characteristic andG=a.multidot.s/(1+a.multidot.s+b.multidot.s.sup.

Abstract: A fixed impedance load is provided with a signal having a variable frequency F from a line capable of supplying a variable available power. The device comprises a pulse width modulator that operates at frequency F and supplies the load with pulses, the width of which varies in the same way as the available power, so that the consumed power on the line remains lower than the available power.

Abstract: A circuit which restores portions of an input signal lost due to clipping distortion includes a comparator which locates the portions of the input signal which have been subject to clipping distortion and generates a pulse signal where each pulse corresponds to a clipped portion of the input signal. This pulse signal is used to generate parabolic pulses which are combined with the input signal to generate a modified signal that approximates the input signal without the clipping distortion. One circuit generates the pulse signals by controlling an oscillator to produce a parabolic pulse train which changes in frequency and amplitude to match each pulse of the pulse signal and then selecting one of the parabolic pulses for each pulse of the pulse signal. Another circuit generates the parabolic pulses by doubly integrating the pulses of the pulse signal.

Abstract: A controller for a clock generator. The controller of the present invention enables a clock signal to the internal clocking mechanism of a device. The controller of the present invention includes a detector and a timer. The detector has two input sense levels, such that it is capable of detecting a clock signal at two separate levels, the first level being larger than the second. Initially, the detector only detects when the clock signal is at a level greater than or equal to the larger of the levels. When this occurs, the timer begins counting. When the clock signal has been at or above the greater level for a predetermined time as determined by the timer, the detector enables the clock signal to go to the internal clocking mechanism. Thereafter, the detector only senses when the clock signal falls below the second level. Thus, the detector enables the clock signal to go to the internal clocking mechanism while the level of the clock signal is above the second level.