Abstract: In an embodiment a circuit includes drive circuitry configured to be coupled to a control terminal of an electronic switch and configured to apply a discharge signal to the control terminal causing the electronic switch to become conductive and provide an electrical discharge path for an energized element, a sensing node configured to be coupled to the control terminal and configured to sense a voltage at the control terminal and a feedback network coupled between the sensing node and the drive circuitry, wherein the feedback network includes a comparator circuit coupled to the sensing node and configured to compare the voltage at the control terminal and sensed at the sensing node with a reference threshold and to provide a comparison signal having a first value and a second value, respectively, in response to the voltage at the control terminal being higher or lower than the reference threshold, and wherein the drive circuitry is configured to produce the discharge signal as a function of the comparison sig

Abstract: An example current mirror arrangement includes a current mirror circuit having an input transistor and an output transistor, where the base/gate terminal of the input transistor is coupled to its collector/drain terminal via a transistor matrix that includes a plurality of transistors. Transistors of the transistor matrix, together with the input transistor, form two parallel feedback loops, such that the input transistor is part of both loops. The first loop is a fast, low-gain loop, while the second loop is a slow, high-gain loop. At lower input frequencies, the high-gain loop may properly bias and accurately generate voltage at the base/gate terminal of the input transistor, while at higher input frequencies the fast loop may significantly extend the linear operating frequency band. Consequently, a current mirror arrangement with improvements in terms of linearity and signal bandwidth may be realized.

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract: An oscillation circuit includes a condenser, a charging/discharging part configured to switch between charging and discharging of the condenser according to a control signal, a comparator configured to compare a voltage of the condenser with a reference voltage and output a comparison result signal, a flip-flop configured to be set or reset according to the comparison result signal, supply an output signal as the control signal to the charging/discharging part, and output the output signal as an oscillation signal, and a current control part configured to control an operating current of the comparator in correspondence with the voltage of the condenser.

Abstract: A method and apparatus for generating a wave shaped pulse electronic signal of a predetermined format from a square pulse signal generator. A signal is applied from the square pulse generator to circuitry having a plurality of transmission lines. Each transmission line having a certain length creating a certain signal time delay and signal reflection for a signal applied to the circuitry from the square pulse generator so as to create a delay pulse from each transmission line. Each delay pulse is combined from each transmission line to generate the wave shaped pulse electronic signal of a desired predetermined format.

Abstract: Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.

Abstract: A relaxation oscillator has a comparator that includes first through third bias current transistors coupled to a first supply rail. First and second input transistors form a pair of parallel coupled transistors connected to the first bias current transistor. A first current mirror control transistor connects the first input transistor to a second supply rail. A first current mirror output transistor is coupled to the first current mirror control transistor, and connects the second bias current transistor to the second supply rail. A second current mirror control transistor connects the second input transistor to the second supply rail. A second current mirror output transistor is coupled to the second current mirror control transistor, and connects the third bias current transistor to the second supply rail. A transition time reduction transistor, coupled across the third bias current transistor, is coupled to the second bias current transistor, and provides a comparator output.

Abstract: A variable-capacitance device includes a first capacitance element coupled between a first power supply terminal and an output terminal, a capacitance selection switch that is turned on and off in accordance with a capacitance switching signal, a second capacitance element coupled in parallel to the first capacitance element and in series to the capacitance selection switch, and an error correction circuit configured to operate such that in a state in which the capacitance selection switch is in an OFF state, in response to a charge reset signal that causes a voltage at the output terminal to be reset to a reset voltage, the error correction circuit substantially eliminates a difference between the voltage at the output terminal and a voltage at a capacitance switching node at which the second capacitance element is coupled to the capacitance selection switch.

Abstract: A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.

Abstract: A waveform shaping circuit enhances a rise of a waveform of a voltage applied to a load and includes an input unit to which the voltage is input; a supply unit configured to apply the voltage input from the input unit to the load; a first resistor connected in series between the input unit and the supply unit; a second resistor branch-connected to a portion between the input unit and the supply unit; and a stub connected to the first resistor or the second resistor and including a transmission path of a given length configured to shuttle the voltage by transmitting and reflecting the voltage as a voltage wave.

Abstract: The relaxation oscillator includes a comparator and a latch. The comparator includes a comparator output and a comparator input that is configured to receive a first input signal in response to a first signal and configured to receive a second input signal in response to a second signal. The latch includes a latch-set input that is configured to be coupled to the comparator output in response to a third signal, a latch-reset input that is configured to be coupled to the comparator output in response to a fourth signal and a latch output that is configured to output the second signal. The relaxation oscillator is configured to achieve an approximately fifty percent duty cycle without requiring the use of a second comparator.

Abstract: An oscillator is provided. The oscillator comprises a flip-flop module, a first and a second setting module. The first setting module comprises: a first switch device to generates a first switch signal according to a first oscillating signal, an NMOS and an inverter. The NMOS comprises a drain to receive a first charging current and a gate to receive the first switch signal, wherein the drain is charged or discharged according to the first switch signal. The inverter is connected to the drain to generate a first setting signal. The second setting module comprises a second switch device to generate a second switch signal according to a second oscillating signal and a comparator to generate a second setting signal according to the second switch signal and a reference voltage. The flip-flop module generates the first and the second oscillating signal according to the first and the second setting signal.

Abstract: The pulse delay circuit includes a plurality of delay units connected in series or in a ring, each of the delay units being constituted of at least one inverter gate circuit grounded to a ground line, and configured to delay a pulse signal passing therethrough by a delay time thereof depending on an input signal applied thereto, and a capacitor connected between a signal line through which the voltage signal is applied to each of the delay units and the ground line. The capacitor serves as a current source to supply a current which each of the delay units consumes to invert a state thereof.

Abstract: An integrated oscillator (10), for an integrated circuit, comprises i) first (CI1) and second (CI2) compensated inverters mounted in series and each comprising first (PI11;PI21) and second (PI12;PI22) plain inverters mounted in parallel and comprising transistors having channel lengths respectively shorter and longer than an optimal channel length, the first compensated inverter (CI1) having input and output terminals respectively connected to first (N1) and second (N2) nodes and the second compensated inverter (CI2) having input and output terminals respectively connected to the second node (N2) and to a third node (N3), ii) a resistor (R) having a chosen resistance value and comprising first and second terminals connected respectively to the first (N1) and second (N2) nodes, and iii) a capacitor (C) comprising first and second terminals connected respectively to the first (N1) and third (N3) nodes, and having a chosen capacitance value to charge and discharge oneself in order to periodically deliver a clock

Abstract: An oscillator includes a first comparator circuit, a second comparator circuit, an oscillation signal generator circuit, and a frequency voltage generator circuit. The first comparator circuit generates a first pulse when a frequency voltage reaches a first reference voltage, and the second comparator circuit generates a second pulse when the frequency voltage reaches a second reference voltage. The oscillation signal generator circuit generates an oscillation signal by latching a first voltage in response to the first pulse and latching a second voltage in response to the second pulse. The frequency voltage generator circuit raises or lowers the frequency voltage in response to the oscillation signal. The driving capability of the first comparator circuit is reduced at the latching of the first voltage and is restored at the latching of the second voltage.

Abstract: The pulse delay circuit includes a plurality of delay units connected in series or in a ring, each of the delay units being constituted of at least one inverter gate circuit grounded to a ground line, and configured to delay a pulse signal passing therethrough by a delay time thereof depending on an input signal applied thereto, and a capacitor connected between a signal line through which the voltage signal is applied to each of the delay units and the ground line. The capacitor serves as a current source to supply a current which each of the delay units consumes to invert a state thereof.

Abstract: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.

Abstract: A PWM signal generating circuit according to the invention includes a digital PWM signal generating circuit that generates a digital PWM signal having a resolution of 2n based on a clock signal CLK and n-bits (n?1) of digital information; a triangular wave generator that generates a triangular wave (e.g. ramp wave) synchronized with the clock signal CLK; and a comparator that compares the triangular wave with a threshold value. The PWM signal generating circuit increases the resolution of the digital PWM signal based on an output from the comparator.

Abstract: An ultra low power relaxation CMOS oscillator for low frequency clock generation comprises a current source and a pair of capacitors that are alternatingly charged by the current source and discharged by thyristor-based inverters being used as comparators. No separate bias currents are needed.

Abstract: An analog delay circuit to impart a group delay to an analog input signal is described. The analog delay circuit may comprise a capacitor to impart at least a portion of the group delay to the analog output signal and a buffer circuit coupled between the capacitor and an input stage to substantially remove at least a portion of a capacitive load at the input stage.

Abstract: A timing circuit operates by applying an arbitrary voltage across a resistance, and using the resulting current to generate a charging current which charges and/or discharges a capacitance to an endpoint voltage. Additional circuitry is arranged such that the capacitance is charged and/or discharged until its voltage crosses a threshold which is proportional to one of the resistance's endpoint voltages, such that the capacitance's endpoint voltage tracks the resistance's endpoint voltage. Thus, the resistor voltage can vary with supply voltage or temperature, or the resistance value itself can vary, without materially affecting the timing relationships. The arbitrary voltage is preferably provided with a pair of diode-connected transistors connected in series with the resistance, so that a single transistor operated at the same current density as one of the diode-connected transistors establishes the threshold voltage and detects when the capacitor voltage reaches the threshold.

Abstract: Object To provide a highly accurate and stable pulse width modulation (PWM) pulse signal generation device compatible with high resolution images without increasing a basic frequency of an external oscillation circuit. Solving Means A PWM pulse signal generation device includes a first PLL control circuit 410, a ring oscillator 420 in which a plurality of basic delay elements are serially connected, and a delayed pulse generation circuit constituted by a delay ratio adjusting circuit 330 and a delay circuit 350. The delay circuit 350 is formed by setting one adjustment delay element having a delay ratio R that is adjusted by the delay ratio adjusting circuit 330 at a first stage and a plurality of serially connecting basic delay elements.

Abstract: An integrated circuit chip including a first delay circuit and a second delay circuit. The first delay circuit has a first delay circuit topology configured to delay a signal a first delay. The second delay circuit has a second delay circuit topology configured to provide a second delay in a circuit loop that is configured to be monitored and provide an oscillating signal. The second delay circuit topology is substantially the same as the first delay circuit topology and the first delay circuit is configured to be trimmed to adjust the first delay based on the second delay and the oscillating signal.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: Methods are described that involve characterizing an oscillator's jitter or phase noise over a plurality of the oscillator's effective number of delay stages. The oscillator comprises a series of delay stages. Each one of the effective number of delay stages, if selected for the oscillator, describes a respective permissible range of inverter drive strengths that may be used within each delay stage of the oscillator to achieve a respective jitter or phase noise characteristic.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: A method and systems to evaluate the propagation delay within a semiconductor chip (305) that is embedded in an electronic system without requiring measurement apparatus and specific electrical contacts is disclosed. Since most of electronic systems use a microprocessor, the basic principle of the invention consists in using the microprocessor capabilities to measure the propagation delay of a chip embedded in such an electronic system. Thus, according to the invention, the microprocessor transmits an instruction to the semiconductor chip that performs propagation delay evaluation and then read the result in a dedicated memory register (415) of the chip. As a consequence, the chip does not require dedicated pins and measurement apparatus. In order to measure the propagation delay, the chip comprise a logic path (400) wherein propagation delay is created, then a rising edge detector (405) is used to analyze logic path signals, A counter (410) based on a system clock is used to measure propagation delay.

Abstract: A voltage-controlled variable duty-cycle oscillator includes a current generator whose current Iref mirrored in three one-shots that each include two pair of series-coupled MOS transistors and a timing capacitor. The timing capacitor is precharged to Vcc in the first two one-shots, and to a lesser voltage Vcon in the third one-shot. The oscillator also includes pre and a post-NOR-gate logic. Output signals from the two one-shots are coupled to the pre NOR-gate logic to generate an intermediate oscillator signal whose duty cycle is determined by Iref and by the first two timing capacitors. The intermediate oscillator signal and output from the third one-shot are combined in the post NOR-gate logic to yield a VCO output signal whose duty cycle is determined by the ratio of the timing capacitor in the third one-shot compared to the sum of the timing capacitors in the first and second one-shots. VCO output signal duty cycle is a fairly linear function of Vcon.

Abstract: A delay locked loop includes a first delay device for obtaining a fine setting and a downstream-connected second delay device for obtaining a coarse setting of the delay time. The control signals for controlling the respective delay devices are provided by synchronization latches, which receive a clock obtained by the output signal of the first delay device for obtaining the fine setting. The delay locked loop enables a linear operating behavior at a high operating frequency and is particularly suitable when a differential embodiment of the two delay devices is used.

Abstract: A digital voltage controlled oscillator is disclosed. The digital voltage controlled oscillator includes an input for receiving input signals representative of a desired frequency. It also includes a pulse generator and a logic circuit. The logic circuit develops an oscillating signal having a predefined waveform and the desired frequency by controlling the energy contained in the pulses output by the pulse generator. The disclosed digital voltage controlled oscillator also includes a capacitor which is charged by the pulses to a voltage that generally varies in accordance with the predefined waveform and the desired frequency.

Abstract: The object of this invention are bistable, monostable and astable multivibrator in which the switching transition level is stable and relatively independent of ambient temperature. This reduction is accomplished by using an auto-zero amplifier system with an input offset voltage of substantially zero volts.

Abstract: A ring oscillator is formed by connecting three or more odd gate circuits in a ring. Each gate circuit includes a precharge dynamic gate. An output signal from the precharge dynamic gate of one gate circuit is used to precharge the precharge dynamic gates of all the remaining gate circuits. In measuring the gate delay time of the ring oscillator formed by connecting, in a ring, three or more odd gate circuits each including a precharge dynamic gate, the oscillation frequency of the ring oscillator is measured, and the reciprocal of the oscillation frequency is divided by the number of gate circuits constituting the ring oscillator.

Abstract: An astable multivibrator comprising a capacitor connected between a first output signal and a third output signal, an amplification circuit connected between the first and third output signals, a delay for delaying a signal logic-converted from the first output signal and for outputting a second output signal, and a variable resistor connected between the first output signal and an output node of the delay. High frequency oscillation performance is enhanced and a larger voltage operating range is obtained by excluding the effect of feedback current.

Abstract: This is an integrated timing circuit which can be formed on a microprocessor chip. The circuit uses an oscillator having a delay line and a variable delay element. The delay line and the delay element vary together to hold the velocity of signal propagation in the circuit substantially constant. The output, of the oscillator is coupled to one input of a comparator circuit. A series of inverter circuits, each of which has a respective variable delay are connected to the input of the oscillator and to a second input of the comparator circuit such that the comparator circuit senses the difference between the output signal of the inverter series and the output signal of the oscillator circuit to provide an error signal proportional to the sensed difference. A feedback loop is provided, to the variable delay means in said oscillator and to the inverter circuits to correct for the sensed difference, to establish a uniform and stable time standard at the output of the oscillator.

Abstract: A current source including a current mirror circuit and an active load circuit which form a reference branch, for setting a reference current value, and a mirroring branch, defining an output current value, connected between supply and ground. A voltage stabilizing transistor is interposed between the current mirror circuit and the load circuit in the reference branch only, and is so biased as to maintain its gate terminal at a predetermined voltage. As such, the potential with respect to ground of the drain terminal of the reference branch load transistor is fixed, so that its drain-source voltage drop (and the current through it) is substantially independent of supply voltage. The current source may be used to advantage in an oscillator for generating the: clock signal of a nonvolatile memory.

Abstract: A floating detection circuit detects the floating state of an input node which can receive an externally applied DC input signal, and includes a pulse generator, a counter and a floating state discriminator. The pulse generator is coupled to the input node and supplies a pulse signal to the input node when the input node is in a floating state. The counter receives the pulse signal and counts the number of pulses included in the pulse signal during predetermined intervals. The floating state discriminator compares the number of pulses with a predetermined reference number, so as to produce a floating detection signal, wherein the floating detection signal indicates whether or not the input node is in a floating state. A semiconductor circuit includes this floating detection circuit and a DC level detector. The floating detection circuit included in the semiconductor circuit detects the input node state during a first period and produces the floating detection signal during a second period.