Abstract: A metal-insulator transition (MIT) latch includes a first electrode spaced apart from a second electrode and an MIT material disposed between said first and second electrodes. The MIT material comprises a negative differential resistance (NDR) characteristic that exhibits a discontinuous resistance change at a threshold voltage or threshold current. Either the first or second electrode is electrically connected to an electrical bias source regulated to set a resistance phase of the MIT material.

Abstract: A logic circuit includes two two-terminal switching devices and receives first and second pulses as inputs. Each of the two devices has two different stable resistivity values for each applied voltage that is greater than a first threshold voltage (Vth1) and is smaller than a second threshold voltage (Vth2) that is larger than Vth1. Each switching device, when a voltage less than or equal to Vth1 is applied, becomes in a first state having the higher resistivity of the two resistivity values, whereas when a voltage more than or equal to Vth2 is applied, becomes in a second state having the lower resistivity of the two resistivity values. The two devices are connected in series in a direction with uniform polarity to each other. The first and second states are selectively generated in the first and second devices by a combination of inputs of the first and second pulses.

Abstract: The invention includes a two terminal switching device having two stable resistivity values for each applied voltage, which when a voltage of not more than a first threshold voltage (Vth1) is applied, becomes in a first state having a higher resistivity, whereas when a larger second threshold voltage (Vth2) or more is applied, becomes in a second state having a lower resistivity; a resistance connected in series to the switching device; a terminal for applying a bias voltage (Vt) to both ends of a series circuit of the switching device and the resistance; a first pulse inputting terminal; and a second pulse inputting terminal. The invention provides a simple realization of a flip-flop circuit for a sequential logic circuit.

Abstract: A pulse generating circuit for use in a semiconductor memory device is triggered by a transition of an input logic signal, to provide an output pulse having a predetermined pulse width or period. Feedback from the output pulse is used to isolate the input signal once the output pulse has begun, so as to prevent premature truncation of the output pulse if the input signal changes state during the output pulse period. This pulse generator is particularly advantageous in high-speed semiconductor memory integrated circuits where the input pulse may be relatively brief.

Abstract: A Schmitt trigger circuit has a field effect transistor coupled between a first fixed potential and an output terminal, and a variable negative resistance circuit coupled between the output terminal and a second fixed potential; the gate of the field effect transistor and the control input of the negative resistance circuit are coupled to the input terminal of the Schmitt trigger circuit; wherein the negative resistance circuit includes a first field effect transistor coupled between the output terminal and the second fixed potential, and a gate coupled to an internal node; a second field effect transistor coupled between the internal node and the second fixed potential, and a gate coupled to the input terminal; and a third field effect transistor coupled between the first fixed potential and the internal node, and a gate coupled to the output terminal.