Abstract: A controlling circuit for controlling on-off switching of a power supply for a CMOS circuit includes a CMOS circuit (20) and a switch (30). The CMOS circuit includes a first circuit (50) for storing the system time of the computer and a second circuit (70) for storing other system settings of the computer. One terminal of the switch is connected to the first circuit and a power supply (10) in parallel via a resistor (R2). The one terminal of the switch is connected to the second circuit, and another terminal of the switch is connected to ground. When the one terminal of the switch is connected to the another terminal, the data stored in the second circuit is cleared while the system time stored in the first circuit remains.

Abstract: CMOS semiconductor pass-transistor logic circuitry (200) is disclosed, comprising pass transistor circuitry (204, 212, 218), and tunneling structure circuitry (228) coupled to the pass transistor circuitry; where the tunneling structure circuitry is adapted to hold a node (222) voltage stable by compensating a leakage current (302) originating from said pass transistor circuitry.

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an analog input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A first negative-resistance device has a first terminal coupled to the clock terminal and a second terminal coupled to the input terminal. A second negative-resistance device has a first terminal coupled to the input terminal and a second terminal coupled to the inverted clock terminal. An output terminal coupled to the first negative-resistance device and the second negative-resistance device to provide a quantized output signal.

Abstract: The present invention includes: a series circuit which has a negative differential resistance element and another negative differential resistance element that has a control terminal capable of controlling a value of an element current; a transfer gate; a latch circuit which has negative differential resistance elements connected in series; and an inverter circuit which has an FET as a drive element and a negative differential resistance element as a load element. With this, such a flip-flop can be obtained that when a clock signal is applied to a power supply terminal of the series circuit and a control terminal of the transfer gate and an input signal is supplied to the control terminal of the negative differential resistance element, an output is placed at a terminal.

Abstract: A high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section. The input circuit section includes at least one transistor such as a field-effect transistor (FET) which determines the logic function of the flip-flop such as D, S-R, or T, and provides a first stage of latching. The input circuit section receives the logic control signals such as D, S-R, or T, and a clock signal. In one embodiment of the invention, the latch circuit section includes two series-connected negative differential resistance (NDR) diodes. In this embodiment, a common terminal of the two NDR diodes is connected to the data output of the input circuit section and to the data input of the output circuit section.