Abstract: A phase detector includes: a phase shift circuit to phase-shift a first positive-phase signal included in a first differential signal and a first negative-phase signal included in the first differential signal, and phase-shift a second positive-phase signal included in a second differential signal and a second negative-phase signal included in the second differential signal; a multiplication circuit to perform multiplication of two signals for all combinations of the first positive-phase signal and the first negative-phase signal with the phase-shifted second positive-phase signal and the phase-shifted second negative-phase signal, and perform multiplication of two signals for all combinations of the phase-shifted first positive-phase signal and the phase-shifted first negative-phase signal with the second positive-phase signal and the second negative-phase signal; and a phase difference calculating circuit to calculate a phase difference between the first differential signal and the second differential signa

Abstract: The operation range of a phase detector provided with a flip-flop is improved, and the jitter tolerance of a receiving circuit is enhanced. The phase detector includes a holding unit and a detection unit. In the phase detector, the holding unit holds an input signal in synchronization with a predetermined periodic signal. The detection unit detects a phase difference between a designated edge and the predetermined periodic signal on the basis of a signal held in the holding unit. The designated edge is designated by a control signal that designates one of a rising edge and a falling edge of the input signal as the designated edge.

Abstract: A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.

Abstract: A method, system, and apparatus for vector control of radio frequency signals in narrow band devices such as Super-conducting Radio Frequency (SRF) cavities driven by injection locked magnetrons using carrier amplitude modulation by spectral energy spreading via phase modulation comprises coupling a magnetron to a cavity associated with a particle accelerator and injection locking the magnetron. A modulated amplitude and modulated phase of a drive signal is provided to the magnetron powering the cavity associated with the particle accelerator by removing power from a carrier according to a modulation scheme and providing vector control of the cavity radio frequency vector.

Abstract: An apparatus is provided which comprises: a mixer to mix a first signal of a first frequency with a second signal of a second frequency, and to generate a first output; a switched-capacitor multiplier, coupled to the mixer, to receive the first output and to provide a second output with reduced noise; and an amplifier, coupled to the switched-capacitor multiplier, to amplify the second output.

Abstract: Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input dock signal. A duty phase interpolator circuit may be coupled to the dock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected dock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error.

Abstract: The invention provides a NAND gate latched driving circuit and a NAND gate latched shift register. The NAND gate latched driving circuit includes multiple cascade connected shift register circuits, each of the shift register circuits including a clock control transmission circuit and a NAND gate latch circuit. The clock control transmission circuit is triggered by a first clock pulse of a clock signal to transmit a driving pulse of a former stage to the NAND gate latch circuit, the driving pulse then is latched by the NAND gate latch circuit. The NAND gate latch circuit further is triggered by a subsequent second clock pulse of a first clock signal to output the latched driving pulse. By the above solution, the NAND gate latched driving circuit of the invention is suitable for CMOS process and can achieve low power consumption and wide noise tolerance.

Abstract: Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output.

Abstract: In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

Abstract: A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals.

Abstract: Traffic management reports are created from data provided by vehicle sensor devices placed at different fixed locations in a region. Data of vehicles that pass each of the vehicle sensor devices are captured and communicated to a central computer database. At the central computer database, a traffic priority enforcement report is created from the vehicle data. The traffic priority enforcement report incorporates vehicle data from a plurality of vehicles. The vehicle data is for a plurality of previous, non-current times so as to allow for analysis of past vehicle data.

Abstract: The present invention relates to a pulse signal generation circuit for changing a pulse width of an input pulse signal and outputting an output pulse signal having the changed pulse width. In an aspect, the pulse signal generation circuit may include a control signal generator configured to generate at least one control signal according to a pulse width of a input pulse signal and a pulse signal generator configured to control a pulse width of an input pulse signal in response to a control signal and to generate an output pulse signal with the controlled pulse width. The control signal controls the pulse width of the output pulse signal.

Abstract: A method and apparatus for performing a data strobe-to-data delay calibration is disclosed. In one embodiment, a data strobe signal, along with data, is conveyed from a memory controller to a memory. An initial delay calibration procedure may be performed to align the data and the data strobe signals at the memory, with subsequent calibrations performed there between in order to compensate for changes due to various factors such as voltage and temperature. In the calibrations performed between the delay calibration procedures, a calibrated delay value may be multiplied by a first scaling factor and a second scaling factor to generate a scaled code. A DLL configured to convey the data strobe signal may then be programmed based on this code.

Abstract: An eye quality monitoring system may include an eye quality monitor that includes a charge pump that is configured to output (a) a first charge in a first direction upon detection of a first transition of a sampled non-return-to-zero (NRZ) data signal in a first region of a unit interval of an eye pattern, and (b) a second charge in a second direction upon detection of a second transition of the sampled NRZ data signal in a second region of the unit interval of the eye pattern. The first direction is opposite from the second direction. The eye quality monitor is configured to form an eye quality output that relates to a quality of the eye pattern based on the first and second charges.

Abstract: A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.

Abstract: A system includes a control circuit and first, second, and third ground-referenced single-ended signaling (GRS) driver circuits that are each coupled to an output signal. The control circuit is configured to generate a first, second, and third set of control signals that are each based on a respective phase of a clock signal. Each GRS driver circuit is configured to pre-charge a capacitor to store a charge based on the respective set of control signals during at least one phase of the clock signal and drive the output signal relative to a ground network by discharging the charge during a respective phase of the clock signal.

Abstract: A method for clock recovery and data recovery from a data stream on a communication channel includes sampling a data stream on the communication channel at a sampling frequency determined by a clock signal and generating a sampled signal. The method further includes determining a phase shift between the communication data stream and the sampled signal and modifying the phase of the clock signal on the basis of the phase shift to obtain a desired phase difference between the sampled signal and the data stream.

Abstract: An apparatus for controlling a latency in a synchronous semiconductor device. The apparatus includes a first counting block for counting a cycle of a first clock signal to thereby generate a first binary code; a second counting block for counting a cycle of a second clock signal to thereby generate a second binary code. The second clock signal is obtained by delaying the first clock signal by a predetermined delay amount, A code comparison block stores the second binary code in response to a command and compares the first binary code with the second binary code to thereby generate a latency control signal.

Abstract: A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown.

Abstract: Systems and methods for transition delay measuring are presented. A transition delay measuring method can include oscillating a signal between states and tracking an indication associated with an isolated attribute of the transitions between the states. Oscillations can include asymmetric transitions between the states and the tracked isolated attribute can be a delay in completing transitions between the states in one direction or vice versa. The asymmetric transitions can include transitions between the first state and the second state that are faster than slower transitions between the second state and the first state or vice versa. The tracked indication can be utilized in analysis of the isolated transition delay characteristics. The results can be utilized in analysis of various further features and characteristics (e.g., examination of leakage current related power consumption, timing of asymmetric operation, etc.). The analysis can include examination of fabrication process and operating parameters.

Abstract: A phase detection device includes a clock divider configured to divide a clock signal and generate a plurality of divided clock signals, a recoverer configured to generate a recovered clock signal having substantially the same frequency as the clock signal based on the plurality of divided clock signals, and a phase detector configured to detect a phase of the recovered clock signal in response to a data strobe signal.

Abstract: A software optimization system isolates an effect of a change in a control variable from effects of ongoing, unknown changes in other variables. The system discards effects due to noise so that effects of interest to a programmer are more easily visible. The software optimization system treats variations in one or more control variables and in the output of the system as signals. The system varies the control variable at a specific frequency unlikely to correlate with uncontrolled variations in external variables. The system uses digital signal processing (DSP) techniques to filter the output, isolating the frequency of the control variable variation. The system then compares the resulting filtered output to the input to determine the approximate effect of the variation in the control variable.

Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes.

Abstract: During operation of the device, a drive circuit may provide a drive signal having a fundamental frequency to two electrothermal filters (ETFs) having different temperature-dependent time constants. In response to the drive signal, the two ETFs may provide signals having the fundamental frequency and phases relative to the drive signal corresponding, respectively, to the time constants of the ETFs. Then, phase-shift values of the phases may be measured using a phase detector, and a signal may be output based on the phase-shift values. Note that the signal may correspond to a value that is a function of a temperature of the device.

Abstract: A phase detector for a phase-locked loop includes a phase detector that is configured to become unstable, oscillate and drift rapidly in frequency in a predictable manner when a reference frequency signal is not available. When applied, for example, to a power converter connected to a power distribution grid, the predictable oscillatory and rapid frequency drift behavior when the phase detector is unstable allows very rapid and reliable detection of disconnection from the grid, referred to as islanding.

Abstract: In a multiphase electrical power assignment, a processor: receives instructions to connect a bi-directional power device to a multiphase premise power source; determines that the power device is to be coupled to a target phase's phase connection; confirms that the power device is not coupled to any phase connections; and couples the power device to the phase connection, where the power device's power signal is synchronized with the phase connection's power signal. When the power device is in a connected state, the processor: issues a command to place each phase connection switch in an open state; in response to confirming that the phase connection switches are in the open state, issues commands to the power device so that a power signal of the power device will be synchronized with the target phase; and closes the phase connection switch corresponding to the target phase.

Abstract: A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock.

Abstract: There is provided a phase locked loop circuit which includes a frequency divider, a phase comparator, a filter, and an output signal oscillator. The frequency divides a feedback signal by a specific ratio and the feedback signal is used for synchronizing a phase of a reference signal and a phase of an output signal. The phase comparator compares the phases of the reference signal, the output signal, and the feedback signal and adjusts a gain of an analog signal used for generating the output signal in accordance with increase or decrease of the ratio. The filter filters the analog signal to pass signals in a specific frequency band, the gain of the analog signal having been adjusted by the phase comparator and the output signal oscillator outputs the output signal on the basis of the analog signal.

Abstract: There is provided a frequency synthesizer capable of improving phase noise. A sinusoidal signal with a frequency set by a frequency setting part is output as a digital signal from a set signal output part, and the digital signal is D/A-converted. A difference between a sinusoidal signal with a frequency corresponding to an output frequency of a voltage controlled oscillating part and a sinusoidal signal output from a D/A converting part is amplified by a differential amplifier, and an amplified signal is input via an A/D converting part to a means for extracting a phase difference between the aforesaid sinusoidal signals. A voltage corresponding to a signal being the result of integration of the phase difference is input as a control voltage to the voltage controlled oscillating part. Then, a gain of the differential amplifier is set larger than a maximum value of phase noise degradation of the A/D converting part, whereby the phase noise degradation of the A/D converting part is cancelled.

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.

Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).

Abstract: A device for detecting non-phase-modulated pulsed signals includes at least one amplifier receiving a radiofrequency signal, and restoring at least one first signal representative of the envelope of the input signal, and a second normalized signal, characterized in that a module for estimating the stability of the phase includes means for estimating the phase of the radiofrequency signal, and means for evaluating the temporal stability of the phase, the presence of a characteristic pulse being detected if the phase is stable according to determined criteria.

Abstract: This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.

Abstract: An inverter delay compensation circuit includes a comparison determination unit including a first delay circuit configured for receiving a reference signal and having an inverter chain and a second delay circuit configured for receiving the reference signal and more insensitive to a PVT variation than the first delay circuit, and configured to compare delay amounts of signals obtained by passing the reference signal through the first and second delay circuits, respectively, and the comparison determination unit configured for generating a plurality of control signals; and a compensation circuit unit configured to compensate for a delay amount of an input signal in response to the plurality of control signals and configured to output an output signal.

Abstract: Phase detection techniques in which an input signal is sampled to obtain several samples at different points in time with respect to a clock, said different points in time comprising an earliest point and latest point. The detection techniques further include generating a phase control signal obtained from the several samples of the input signal.

Abstract: A phase-locked loop (PLL) includes PLL loop circuitry, a frequency divider, and a phase-frequency detector (PFD) that can produce both high-gain output signals to operate the PLL in a high-gain mode and normal output signals to operate the PLL in a normal (not high-gain) mode. A mode signal can be used to switch the PFD between high-gain mode and normal operational mode. When the mode signal indicates high-gain mode, the PFD output signals are extended by one or more additional clock cycles beyond their length when the mode signal indicates normal operational mode.

Abstract: A digital phase comparator is provided in which first phase difference signals and second phase difference signals are used as digital phase difference information. The first phase difference signals are generated by sampling a second clock signal with a first group of clock signals having regular intervals. The second phase difference signals are generated, using a second group of clock signals and a first group of signals which are obtained by delaying a second clock signal and a first signal generated by performing a logic operation on the first phase difference signal respectively at different regular intervals, by sampling the second group of clock signals with the first group of signals.

Abstract: The present invention provides a system and method for representing quasi-periodic (“qp”) waveforms comprising, representing a plurality of limited decompositions of the qp waveform, wherein each decomposition includes a first and second amplitude value and at least one time value. In some embodiments, each of the decompositions is phase adjusted such that the arithmetic sum of the plurality of limited decompositions reconstructs the qp waveform. These decompositions are stored into a data structure having a plurality of attributes. Optionally, these attributes are used to reconstruct the qp waveform, or patterns or features of the qp wave can be determined by using various pattern-recognition techniques. Some embodiments provide a system that uses software, embedded hardware or firmware to carry out the above-described method. Some embodiments use a computer-readable medium to store the data structure and/or instructions to execute the method.

Abstract: An apparatus and method for coupling a charging station to a power line segment that is terminated at a first end by a charging terminal are disclosed. The apparatus includes multiple taps coupled to the power line segment and circuitry coupled to the charging station and coupled to the multiple taps. The circuitry is configured to differentiate between communication signals propagating on the power line segment in the direction from the first end to a second end of the power line segment and communication signals propagating on the power line segment in the direction from the second end to the first end based at least in part on multiple measurements of respective phase shifts associated with different portions of a communication signal, each portion received over at least a first tap and a second tap.

Abstract: A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.

Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Abstract: The disclosure provides an effective means for fine-resolution determination of the frequency content of an RF signal using low speed digital circuits. The disclosure relates to a method and apparatus for decomposing a high frequency RF signal into several low frequency signals or data streams without loss of any information and without the use of extraneous circuit components such as local oscillators, mixers or offset phase-locked loops. Single or multiple phase oscillator outputs are fed directly to a single or multiple direct RF frequency-to-digital (DrfDC) circuits. The front end of the DrfDC circuit decomposes a high frequency signal into several low frequency signals without loss of any information. The low frequency signals are processed by the back-end of the DrfDC and converted into digital data streams. The digital data streams are then combined and averaged to represent the frequency of the input RF signal.

Abstract: A transmitting apparatus, receiving apparatus and communication system are disclosed, and great improvement in an S/N ratio, preventing an actual throughput from decreasing, and preventing the number of circuits for synchronizing spread spectrum signals from increasing can be expected at the receiving apparatus side. The transmitting apparatus includes a pulse generating circuit, pulse repetition cycle determining circuit, peak power determining circuit, and modulator. The pulse generating circuit generates pulse strings, pulse repetition cycle determining circuit determines, based on a clock signal, a pulse repetition cycle of the pulse string generated by the pulse generating circuit. The peak power determining circuit determines a pulse peak power of the pulse string. The modulator modulates the pulse string with transmission data, and then generates a transmission signal.

Abstract: A phase comparator is provided that solves the problem that a VCO cannot be controlled with high precision. A frequency divider frequency-divides a VCO signal applied as input to an input terminal (10) in steps, and supplies the VCO signals of each step as output. A latch unit latches the VCO signal that is applied to the input terminal (10) and each VCO signal that was supplied from the frequency divider based on a reference signal that is applied to an input terminal (11). An output unit supplies the latch results realized by the latch unit as phase difference signals that indicate phase differences of the reference signal and the VCO signals.

Abstract: A basic symmetric ?/2 phase-detector receives four control signals that control a differential current at the detector's output. Each respective control signal is a linear combination of a respective pair of signals chosen from a first input signal, its logic complement, a second input signal and the logic complement of the latter. Operation is based on time-averaging the differential current, the result being zero at a phase difference of ?/2. By means of adding one or more additional current sources to the output, controlled by one or more of the control signals, the basic operation is skewed. The time-averaged output current is now made zero only at a value of the phase difference different from ?/2. In an embodiment with uniform current sources and resistors, the modified detector is configured for a phase difference of ?/2N .

Abstract: An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.

Abstract: Efficient techniques improve the linearity of a charge pump in fractional-N PLLs. A feedback clock pulse several VCO clock periods wide is formed and supplied to a phase frequency detector (PFD). The down pulse generated by the PFD is fixed to eliminate the nonlinearity associated with up and down current source mismatch. The up pulse is made to fall when the down pulse falls, that is, when the feedback clock pulse falls.

Abstract: The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.

Abstract: A device for detecting non-phase-modulated pulsed signals or sequences of pulses of a determined frequency includes means for detecting tangling of pulses, at least one amplifier receiving a radiofrequency signal, and restoring at least one first signal representative of the envelope of the input signal, and a second normalized signal. A phase jump estimation module includes means for estimating the phase of the radiofrequency signal, means for evaluating a phase jump, the presence of pulse tangling being detected if the phase jump is of a greater value than a determined threshold value.

Abstract: A method for digital phase detection, comprises the steps of: providing a reference clock; receiving a feedback clock; determining a timing difference between the reference clock and the feedback clock; determining a polarity that indicates the leading or lagging relationship between the reference clock and the feedback clock; adaptively selecting one of at least two operating modes for generating a quantized level indicative of the timing difference, wherein in a first operating mode the quantized level is a constant maximum value and wherein in a second operating mode the quantized level is proportional to the timing difference; and generating a digital phase detection output as a combination of the polarity and the quantized level.