Abstract: A power control module includes a power device having a first side and a second side opposite from the first. The power control module includes a printed wiring board (PWB) spaced apart from the first side of the power device. The PWB is electrically connected to the power device. A heat sink plate is soldered to a second side of the transistor for heat dissipation from the transistor. The PWB and/or the heat sink plate includes an access hole defined therein to allow for access to the transistor during assembly. A method of assembling a power control module includes soldering at least one lead of a power device to a printed wiring board (PWB), pushing the power device toward a heat sink plate, and soldering the power device to the heat sink plate.

Abstract: A regulation system for controlling the vibratory behavior in twisting and/or the twisting stability of a drivetrain of a rotorcraft, the regulation system comprising two regulation loops that are interleaved one in the other, the two regulation loops being arranged “in cascade” relative to each other to regulate firstly a first speed of rotation NG of a gas generator of at least one turboshaft engine driving said drivetrain in rotation, and secondly a second speed of rotation NTL of a free turbine of the engine(s).

Abstract: A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.

Abstract: Embodiments of the present application provide a method for information transmission. The method includes determining multiple enhanced transmission occasion configurations; determining a first enhanced transmission occasion configuration according to a channel loss magnitude with a user equipment, a time width occupied by the enhanced transmission occasion is greater than a time width occupied by a non-enhanced transmission occasion; sending information according to the first enhanced transmission occasion configuration. Embodiments of the present application also provide a base station and user equipment, configured to determine an enhanced transmission occasion configuration according to the range which the channel loss magnitude belongs to. Therefore, the base station and user equipment may send and/or receive information on a suitable time-frequency resource and power configuration according to the channel loss magnitude, thus, the resource allocation is optimized, and the power consumption is saved.

Abstract: According to various embodiments, there is provided a method for generating a reference clock signal, the method including discharging a capacitive element to a discharged state, when a reset signal has a predetermined reset state; charging the capacitive element from the discharged state to a first voltage, when a charge signal has a predetermined charge state; comparing the first voltage to a zero voltage, when a compare signal has a predetermined compare state; generating a second voltage based on the comparing of the first voltage to the zero voltage; generating a clock signal based on the second voltage, using an oscillator; and generating each of the reset signal, the charge signal and the compare signal, based on the clock signal.

Abstract: A system that has a chirp generator for emitting signals and an amplitude modulator for shaping the signals emitted by the chirp generator. The signals are shaped using a calibration ramp. The system further includes a Radio Frequency (RF) power amplifier for amplifying the signals shaped by the amplitude modulator, an RF power detector for measuring power levels of the signals amplified by the RF power amplifier, and a pre-distortion coefficient generator for adjusting the measured power levels using power detector calibration coefficients that correspond to the RF power detector.

Abstract: An apparatus is provided including an unmanned aerial vehicle and a transformer monitoring device, particularly for use in a smart grid network system to support a wireless mesh network in the smart grid network and to collect metering data relating to electricity usage in the smart grid network. The transformer monitoring device is configured to receive signaling containing data from one or more network devices in a smart grid network and transmit signaling containing data to the one or more network devices in the smart grid network, and also to receive signaling containing metered usage data from at least one electric meter associated with a building receiving electricity from a transformer in the smart grid network.

Abstract: A pulse compression radar for performing pre-distortion is provided, which has a configuration simplified in circuit structure. A radar apparatus (pulse compression radar) includes an antenna configured to externally transmit a transmission signal transmitted by a power amplifier and receive a reflection signal caused thereby as a reception signal. The radar apparatus includes a reception circuit configured to propagate this reception signal to a radar image creating module. The radar apparatus corrects beforehand, by utilizing the transmission signal (feedback signal) transmitted from the power amplifier, a transmission signal to be inputted into the power amplifier so as to cancel distortion of the transmission signal caused by amplification effect of the power amplifier. Further, a circuit where the reception signal passes and a circuit where the feedback signal passes share a part of each other.

Abstract: A radar apparatus for performing pre-distortion is provided, which has a configuration instantly transmittable of a transmission signal without distortion even in a case where a power is turned off. A radar apparatus (pulse compression radar) calculates a correction coefficient based on a transmission signal before distortion occurs therein and a transmission signal (feedback signal) outputted by a power amplifier. The radar apparatus corrects the transmission signal outputted by an ideal transmission signal memory while taking into consideration distortion that is caused in the amplification by the power amplifier, by using the correction coefficient. The radar apparatus includes a non-volatile memory configured to store the calculated correction coefficient as backup.

Abstract: A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

Abstract: A lighting device is generally illustrated including a light body having forward facing light sources including a visible white light source, visible colored light source and an infrared light source. Additionally, a side facing light source is provided. The light body also includes switches for activating the visible light sources and a three-position switch for activating the IR light source and the side facing light source. The lighting device further includes boost circuitry for controlling electrical energy supplied to a light source.

Abstract: The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.

Abstract: According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase.

Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

Abstract: The present invention relates to a phase frequency detector (PFD) (100) for use as one of the blocks in a phase-locked loop. The PFD of the present invention has zero dead zone, has a simpler structure with a minimum number of transistors and requires a smaller area. The PFD of the present invention does not use any inverter or delay gate as found in the conventional PFD. Instead, the PFD of the present invention utilizes feedback transistors that save power and thus the PFD of the present invention is suitable to be used in low power applications.

Abstract: A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.

Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Abstract: A phase detector circuit compares the phases of first and second periodic input signals to generate an output signal. The phase detector includes a circuit that makes two different combinations of the first and the second periodic input signals to generate third and fourth periodic signals. This circuit causes the third periodic signal to be based on a first combination of the first periodic signal and the second periodic signal that imparts a first relative phase shift. The circuit causes the fourth periodic signal to be based on a second combination of the first periodic signal and the second periodic signal to provide a different relative phase shift. The phase detector also includes a comparison circuit that compares a measure of the power of the third periodic signal to a measure of the power of the fourth periodic signal to generate the phase comparison output signal.

Abstract: A basic symmetric ?/2 phase-detector receives four control signals that control a differential current at the detector's output. Each respective control signal is a linear combination of a respective pair of signals chosen from a first input signal, its logic complement, a second input signal and the logic complement of the latter. Operation is based on time-averaging the differential current, the result being zero at a phase difference of ?/2. By means of adding one or more additional current sources to the output, controlled by one or more of the control signals, the basic operation is skewed. The time-averaged output current is now made zero only at a value of the phase difference different from ?/2. In an embodiment with uniform current sources and resistors, the modified detector is configured for a phase difference of ?/2N .

Abstract: Efficient techniques improve the linearity of a charge pump in fractional-N PLLs. A feedback clock pulse several VCO clock periods wide is formed and supplied to a phase frequency detector (PFD). The down pulse generated by the PFD is fixed to eliminate the nonlinearity associated with up and down current source mismatch. The up pulse is made to fall when the down pulse falls, that is, when the feedback clock pulse falls.

Abstract: Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

Abstract: Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.

Abstract: A phase detection circuit determines phase difference between a periodic signal and a reference signal of substantially equal frequency. The circuit includes: a source input receiving the periodic signal; a feedback signal generator providing a feedback signal (PFB) with substantially the same frequency as the reference signal; a phase difference circuit coupled to the source input node and a second signal input node coupled to the feedback signal generator, determining an error signal from phase difference between the periodic signal and PFB; an integrator circuit integrating the error signal into an integration signal; and a digitizing circuit digitizing the integration signal. The feedback signal generator is coupled to the digitizing circuit, providing PFB based on the digitized integration signal, and selecting the phase of PFB from a number of fixed phases. The phase detection circuit generates a time-average of the phase of PFB selected from the plurality of fixed phases.

Abstract: A test apparatus includes a recovered clock generating circuit generating a recovered clock having substantially the same phase as an output of a device under test (DUT), a data acquiring section acquiring a value of the output data at a timing indicated by a strobe signal based on the recovered clock, a comparator comparing the value acquired by the data acquiring section to a prescribed expected value, and a judging section judging pass/fail of the DUT based on a comparison result. The recovered clock generating circuit includes a phase comparator comparing the phase of the output data of the DUT to the phase of the recovered clock, a control signal generating section generating a control signal such that the phase of the recovered clock is synchronized with the phase of the output data, and a phase shifter continuously shifting the phase of the reference clock based on the control signal.

Abstract: Apparatus and methods detect missing clock edges. An improved phase frequency detector (PFD) can be used in, for example, a phase locked loop (PLL) or a delay locked loop (DLL). Conventional PFDs can miss clock edges. Disclosed is a missing clock edge detection circuit that reliably detects these missing clock edges to correctly activate switches of a charge pump of the PLL or DLL. Embodiments exhibit relatively little of the characteristic polarity reversal of conventional PLL or DLL circuits, which then enables embodiments to operate faster and acquire phase lock quicker than conventional circuits. Such techniques are useful in clock synthesis, clock recovery, and the like. The invention can further include an optional circuit that detects when the missing clock edge detection circuit may have inaccurately determined (false positive) that a clock edge had been missed, to override the corrective action by the missing clock edge detection circuit.

Abstract: A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.

Abstract: A phase comparator includes an edge detecting unit to which a reference signal is input and to which a referred signal based on the reference signal is input as a feedback signal. The edge detecting unit detects an edge of the reference signal and an edge of the referred signal. The phase comparator also includes a phase-difference detecting unit that detects a phase difference between the edge of the reference signal and the edge of the referred signal. The phase comparator also includes a phase-difference-signal output unit that outputs a phase-difference signal for current control based on the phase difference. The phase comparator also includes an input-break detecting unit that detects an input break of the reference signal when an edge of the referred signal is again detected after an edge of the referred signal is detected and before an edge of the reference signal is detected.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: The disclosure provides systems and methods for programmable fixed frequency digitally controlled oscillators for multirate low jitter frequency synthesis. The present invention utilizes a digital control element, such as a complex programmable logic device (CPLD) or field programmable gate array (FPGA), to monitor the frequency offset of a DCO with respect to one or more timing module (TM) references. The frequency offset is measured by aligning the phase of a DCO feedback divider to the phase of a reference divider, and then counting the number of pulses in the DCO between the falling edges of the feedback to determine a frequency error. Falling edge detection is used to determine a sign of the error. The digital control element then calculates a frequency correction based on a linear scaling factor to send a new control word to the DCO to reduce the frequency error.

Abstract: A phase detector includes transistors that generate first and second phase error signals. The phase detector resets the first phase error signal in response to at least one of the first and the second phase error signals through a first reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the first reset path. The phase detector resets the second phase error signal in response to at least one of the first and the second phase error signals through a second reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the second reset path.

Abstract: A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

Abstract: Linear sample and hold phase detectors are disclosed herein. An example phase detector is coupled to an input data signal and a recovered clock signal and includes a linear phase difference generator circuit and a sample and hold circuit. The linear phase difference generator includes a first input coupled to the input data signal and a second input coupled to the recovered clock signal and outputs a first phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a rising edge of the input data signal and a second phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a falling edge of the input data signal.

Abstract: Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector samples the clock signal and the reference signal on positive edges of one or more of the clock signal and the reference signal, samples the clock signal and the reference signal on negative edges of one or more of the clock signal and the reference signal, and generates one or more error signals indicating a phase difference between the clock signal and the reference signal. A clock signal that is phase aligned with a reference signal can be generated by generating an error signal indicating a phase difference between the clock signal and the reference signal and applying the error signal to an oscillator to produce the clock signal.

Abstract: A floating DC-offset circuit for a phase detector. The circuit may provide a floating DC-offset to the phase detector, or to the voltage-controlled oscillator of the phase-locked loop. The circuit includes a voltage comparator, clock, digital resistor, and offset line to a DC-offset branch of the phase detector. The voltage comparator detects when the voltage at the output of the loop filter of the phase-locked loop has gone outside of a designated range, and activates the clock when the voltage is outside the designated range. The clock emits impulses that are counted by the digital resistor. The digital resistor shifts DC-offset at the DC-offset branch of the phase detector. The new DC-offset level is maintained once the loop filter output voltage has returned within the designated range. In an alternate embodiment, the DC-offset branch is connected to rough-tuning input of a wide-tuned voltage-controlled oscillator.

Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract: A phase detecting module includes a phase detecting unit, a comparator and a counter. The phase detecting unit is arranged to compare a first input signal and a second input signal to generate a phase detecting result. The comparator is arranged to compare the phase detecting result and a predetermined voltage to generate a comparing result. The counter is arranged to count one of the first input signal and the second input signal to generate a counting value. The phase detecting result and the counting value are reset if the counting value reaches a predetermined value, and the comparing result is outputted to a target device from the comparator if the counting value reaches a predetermined value.

Abstract: A feedback circuit includes a third variable delay device that controls the amount of phase delay of a first clock; a third logic gate that detects a phase difference between the first clock delayed by the third variable delay device and the first clock, and outputs a third signal of a pulse width corresponding to the phase difference detected; and a LPF that outputs, as a control signal Vcontrol, the integral of the pulse width of the third signal. The control signal Vcontrol, indicative of a delay amount, is fed back the third variable delay device and input to a first variable delay device and a second variable delay device of a phase-difference detection unit.

Abstract: A method and apparatus for pre-clocking have been disclosed. In one case pre-clocking is used to effectively decrease the delay to output timing with respect to a clock. In another case pre-clocking is used to allow an output signal more time to reach a given level. In another case a pre-clocking adjustment may be determined while a device is in operation.

Abstract: A phase comparator includes an edge detecting unit to which a reference signal is input and to which a referred signal based on the reference signal is input as a feedback signal. The edge detecting unit detects an edge of the reference signal and an edge of the referred signal. The phase comparator also includes a phase-difference detecting unit that detects a phase difference between the edge of the reference signal and the edge of the referred signal. The phase comparator also includes a phase-difference-signal output unit that outputs a phase-difference signal for current control based on the phase difference. The phase comparator also includes an input-break detecting unit that detects an input break of the reference signal when an edge of the referred signal is again detected after an edge of the referred signal is detected and before an edge of the reference signal is detected.

Abstract: Disclosed are embodiments of a phase control circuit with an analog phase controller having first and second order integration. In some embodiments, the analog control circuit generates first and second control signals and controls the first control signal based on the sign of the second control signal and controls the second control signal based on the sign of the first control signal.

Abstract: An apparatus and method for providing timing recovery under conditions of low signal to noise ratios (SNRs) is disclosed herein. A preliminary phase error signal is generated by comparing an input signal with a preliminary estimation of an output signal corresponding to the input signal. A correction signal is generated as a function of the output signal, input signal, and preliminary phase error signal. The preliminary phase error signal and the correction signal are combined to generate a final phase error signal.

Abstract: A radiation hardened phase frequency detector (PFD) is provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract: A phase-controlled current source for phase-locked loop is provided. The phase-locked loop includes a voltage-controlled oscillator to associate a charging path or discharging path in order to generate an output signal and the output signal is further sensed so as to generate a loop signal. The phase-controlled current source includes a status memory receiving the loop signal and the reference signal so as to output an energy-triggering/energy-removing signal; and a controllable current source, under the control by energy-triggering/energy-removing signal so as to decide whether a charging and discharging action should be performed, wherein after the charging action or discharging action is decided, the charging path or the discharging path is generated through the reference signal and the loop signal.

Abstract: An apparatus of phase-frequency detector for adjusting wobble clock signal and wobble signal in the same phase, comprising: a first logic gate, receiving a first protection signal and a second protection signal and outputting a third protection signal according to a logic operation; a first flip-flop, coupled to the first logic gate, outputting the third protection signal as a first output signal when the wobble clock trigger; a second flip-flop, coupled to the first logic gate, outputting the third protection signal as a second output signal when the wobble signal trigger; a second logic gate, coupled to the first and the second flip-flop, outputting a fourth protection signal according to a logic operation; a third logic gate, coupled to the second logic gate, receiving the third and the fourth protection signal, and outputting a fifth protection signal according to a logic operation; and a control signal generator, receiving the wobble clock, the input signal, and the fifth protection signal and determinin

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: An instantaneous phase error detector (IPED) and method includes a first gate configured to logically OR output phase error signals as data to a first latch, and a second gate configured to logically combine the output phase error signals to clock the first latch. A delay element delays to the data to the first latch where the output of the first latch provides instantaneous phase error change information. A second latch is coupled to the output phase error signals to output a lead/lag signal to indicate which of the output phase error signals is leading. A phase-locked loop employing the output of the IPED is also disclosed along with static phase measurement and jitter optimization features.

Abstract: The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a delayed reset signal and a second flip-flop configured to generate a second signal, the second signal transitioning to the first logic level in response to a second edge of a second input signal and transitioning to the second logic level in response to the delayed reset signal. The phase-frequency detector may further include a first delay unit configured to delay a reset signal to generate the delayed reset signal and a second delay unit configured to delay the reset signal to generate an output control signal for adjusting at least one of the first and second signals.

Abstract: A method and apparatus for pre-clocking have been disclosed.