Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Abstract: A serial data transmission system, includes a transmitting terminal for transmitting a data, a receiving terminal for receiving the data transmitted by the transmitting terminal, a first connecting capacitor connected between the transmitting terminal and the receiving terminal, and a second connecting capacitor connected between the transmitting terminal and the receiving terminal, wherein the transmitting terminal comprises a transmitting terminal driver unit and an amplitude detection unit connected with the transmitting terminal driver unit, the transmitting terminal driver unit outputs a pair of differential signals, the amplitude detection unit detects an amplitude variation of the differential signals output by the transmitting terminal driver unit, and outputs an indication signal indicating whether the transmitting terminal and the receiving terminal are properly connected with each other. A serial data transmission method is further provided.

Abstract: A waveform shaping device shapes a waveform of an externally input signal and outputs the input signal with the shaped waveform as an output signal to an equalizer for compensating a distortion of a signal, and includes a nonlinear process section for generating a nonlinear process signal (i) in which positive and negative signs of a low-frequency-free signal obtained by removing at least a direct current component from frequency components of the externally input signal are retained and (ii) which broadly monotonically increases nonlinearly with respect to the low-frequency-free signal when values of the low-frequency-free signal are at least in the vicinity of 0, the nonlinear process signal being added to the low-frequency-free signal so as to generate the input signal.

Abstract: According to one embodiment of the present invention, it is possible to realize a signal transmitter which is capable of reducing power consumption and which can be easily designed. A differential transmitter block outputs differential output signals fixed to a predetermined logic signal to a differential receiver block and disconnects terminating resistors from a signal transmission path in an idle state. In the differential receiver block, a differential comparator outputs a logic determined by symbols of the differential output signal from the differential transmitter block, and an operating state detector detects the idle state upon detection that time successively outputting a predetermined logic by the differential comparator reaches a predetermined time, and controls switches so as to disconnect the terminating resistors from the signal transmitter in the receiving side upon detection of the idle state.

Abstract: A mono-cycle generating circuit comprises a control circuit, a multiplexer, and a driver switch circuit. The control circuit generates sets of timing pulses. The multiplexer selects one of the sets of timing pulses. The driver switch circuit outputs a mono-cycle based upon the selected set of timing pulses. The driver switch circuit comprises complementary sets of switches, each complementary set of switches including complementary amplitude pull-up/pull-down functions such that the output mono-cycle is a full rail swing mono-cycle.

Abstract: A pulse generation circuit which can be controlled to generate on-signals and off-signals simultaneously for use in testing the protection circuit of a power device's drive circuitry. The protection circuit prevents faulty operation due to dv/dt transient signals which can cause the S and R input signals to a set-reset flip-flop circuit to simultaneously be HI, resulting in an error condition. Protection circuit 26a has the structure as shown in FIG. 1. A pulse generation circuit, as shown in FIG. 3, can be used to provide simultaneous changes of logic value at B and C to test the protection circuit.

Abstract: A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for

Abstract: An emitter-coupled multivibrator circuit comprises two transistors (Q1, Q2), between which a positive feedback is provided by connecting each transistor base via buffer transistors (Q3, Q4) to the collector of the other transistor. In the multivibrator, the transistors (Q1, Q2, Q3, Q4) are connected to operating voltages via coils (L1, L2, L3, L4, L5, L6) instead of using conventional resistors and current sources. This lowers the necessary operating voltage, since no DC voltage loss is provided across the coils. Additionally, this improvement increases amplification during the avalanche process and thus the speed of the whole circuit. Further at high frequencies, the waveform of a signal is closer to a sinusoidal form. The speed of the circuit can be increased further by providing an electromagnetic coupling between the coils (L1, L2, L3, L4, L5, L6).

Abstract: A power efficient implementation of a single-pulse generator requiring less chip area and fewer circuit devices.