Abstract: A circuit separately measures a selected one of the rising-edge and falling-edge signal propagation delays through one or more circuits of interest. A number of synchronous components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component clocks a subsequent synchronous component in the ring; the subsequent synchronous component responds by clocking a later component in the ring and by clearing a previous component to prepare it for a subsequent clock. The oscillator thus produces an oscillating test signal in which the period is proportional to the clock-to-out delays of synchronous components. This proportionality provides an effective means for measuring the clock-to-out delays of those components. Other embodiments include additional asynchronous test circuit paths for which the associated signal propagation delays are of interest.

Abstract: An oscillating means having an oscillator outputs a reference clock, and a frequency-dividing means sequentially frequency-dividing the reference clock into a half frequency. A temperature correction data creating means detects a temperature, calculates logical delaying/advancing data for a temperature change, and outputs the logical delaying/advancing data in every predetermined period. A temperature correction data input means receives the delaying/advancing data outputted by the temperature correction data creating means and outputs the logical delaying/advancing data to a logical delaying/advancing means. The logical delaying/advancing means operates a state of the frequency-dividing means in every predetermined period on the basis of the set logical delaying/advancing data to control the period of the frequency-divided output signal of the frequency-dividing means so as to be coincident with a desired period.

Abstract: A digital pulse delay system comprises: a counter incremented responsive to a succession of input pulses and generating a plurality of successive gating signals; a plurality of gates, each having a first input for receiving said input pulses and a second input the receiving a different one of said gating signals; a plurality of pulse delay circuits providing uniform time delays, each receiving an output pulse from a different one of said gates; and, an output circuit combining said uniformly delayed pulses from all of said delay circuits into a single output signal representing a uniformly delayed version of said succession of input pulses.

Abstract: A delay circuit is to produce a delay timing which is larger than one cycle time of a reference clock while the resolution of which is smaller than the one cycle time of the reference clock.

Abstract: A ring oscillator is an oscillator, which is composed of serially connected buffers, for outputting a plurality of phases, and a last buffer output is inverted and fed back to a first buffer. A decoder selects one of outputs from the ring oscillator according to externally supplied digital data indicating an amount of a delay time to be set. A counter counts an output from the decoder, and outputs a delay signal if a count value reaches a predetermined number. That is, the counter outputs a signal with an amount of delay time according to digital data.

Abstract: A ring oscillator is an oscillator, which is composed of serially connected buffers, for outputting a plurality of phases, and a last buffer output is inverted and fed back to a first buffer. A decoder selects one of outputs from the ring oscillator according to externally supplied digital data indicating an amount of a delay time to be set. A counter counts an output from the decoder, and outputs a delay signal if a count value reaches a predetermined number. That is, the counter outputs a signal with an amount of delay time according to digital data.

Abstract: A temperature balanced circuit is provided which is capable of, in case a CMOS.cndot.IC is utilized as a delay circuit, giving a constant delay time to an input signal to the delay circuit even if the frequency of the input signal is varied. A delay circuit 11 and a dummy circuit 11 having the same construction as that of the delay circuit are provided in a CMOS.cndot.IC. There are provided a counter counting first pulse signals CP1 supplied to the delay circuit during a fixed time interval and arithmetic unit finding a difference between a count value of this counter and a predetermined value, and the same number of second pulse signals as the difference value found by the arithmetic unit is supplied to the dummy circuit, thereby to define to a constant value both the number of the first pulses and the number of the second pulses supplied to the CMOS.cndot.IC within a unit time interval, which results in uniformity of an amount of heat generated in the CMOS.cndot.IC.

Abstract: A circuit for synthesizing, from a first signal having a first frequency, a second signal having a second frequency. This synthesis includes using a delay locked loop in combination with a minimal amount of logic circuitry to generate a synthesized output signal which is completely deterministic and does not require any analog control.

Abstract: A digital signal delay circuit includes a first pair of counters for setting a starting point of a digital output signal by counting an adjustably set number of clock pulses corresponding to an intended time delay from a starting point of a digital input signal. The circuit further includes a second pair of counters for setting an ending point of the digital output signal by counting an adjustably set number of clock pulses corresponding to an intended output pulse width from an ending point of the digital input signal. The state of the digital output signal is only determined by the state of the output signal of the last counter in the first pair of counters. The output signal from the last counter in the first pair of counters controls a count starting point of the first counter in the second pair of counters. The output signal from the second pair of counters controls an initializing point on which the state of the output signal from the last counter in the first pair of counters is inverted.

Abstract: A digital phase shifter phase shifts an input signal by a predetermined phase angle. A length of a cycle of the input signal is determined. Then an output signal is generated which is phase delayed from the input signal by a phase amount. The phase amount is approximately equal to the length of the cycle of the input signal multiplied by the predetermined phase angle.

Abstract: The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.

Abstract: The apparatus and method described herein provides for generating a delayed reference in response to a received reference. The occurrence of a first event in the received reference is detected and a delay period started in response thereto. At the end of the delay period a reset is generated. A delayed version of the received reference is then generated in response to the reset. In addition, a delayed signal is generated to steer a companion delay to the same value.

Abstract: A method and circuit for synchronizing input data with a sample clock in which, for each sample clock cycle, the position of input data transitions relative to an acceptable neutral zone is detected. The neutral zone is of predetermined time duration and is positioned in a predetermined location relative to the active edge of the clock signal. If the transition occurs during the neutral zone no corrective action is warranted. If the data transitions move beyond the neutral zone, into a predetermined time interval on either side of the active edge, this event is captured and used by control logic to effect a return of the data transitions to a location within the neutral zone.

Abstract: It is an object to accurately obtain the period of the horizontal synchronizing signal in the video signal. The number of internal pulses are measured in a predetermined measurement period defined by the horizontal synchronizing signal. It is assumed that the periods of the horizontal synchronizing signal and the internal pulse are denoted as T.sub.H and T.sub.S, and the measurement period is defined by one period of a divided signal NS which is obtained by N-dividing the horizontal synchronizing signal. In this case, the length of the measurement period is N.multidot.T.sub.H. The period of the horizontal synchronizing signal is obtained when the internal pulse is activated K times in the measurement period. After the measurement period is started, the divided signal NS transits between the Kth activation of the internal pulse and the (K+1)th activation, and the measurement period is ended. Accordingly, there is the relation of T.sub.S .multidot.K<N.multidot.T.sub.H <T.sub.S .multidot.(K+1). The error .

Abstract: A semiconductor integrated circuit detecting a change in the internal propagation delay and self-compensating such a change. A combination of semiconductor integrated circuits can self-compensate a change in the total propagation delay of the circuit. There is provided a ring oscillator composed of dummy device elements separate from an actually-used logic circuit portion. The oscillating pulses of the ring oscillator are counted relative to a reference pulse signal. The semiconductor integrated circuit has a delay time compensation control circuit block which generates control data used to compensate the change in the propagation delay based on the difference between the first-counted value and a subsequently counted value. In a combination of semiconductor integrated circuits, the delay time compensation control circuit block may be provided for each channel. Alternatively, the delay time compensation control circuit block may be provided for common use by many channels.

Abstract: A timer has a function of compensation calculation and includes a compensation value register 1 for holding a compensation value and an arithmetic unit 2 which adds or subtracts a compensation value ".alpha." held in the compensation value register 1 and a value "CC" of a count value C of a counter 3 at that time point, and by loading the operation result of the arithmetic unit 2 to the counter 3. Such a timer reduces a burden on a CPU and is capable of compensating the count value correctly regardless of a remaining time.

Abstract: An elapsed time recording device includes a counter (130) for incrementally advancing a count value from an initial value towards and beyond a threshold in response to successive clock pulses of a clock signal. Control logic (140) enables the counter (130) to incrementally advance the count value in response to a first input (pin 3) and a second input (pin 1) being at or near a first voltage level, and holds the count value in response to the first input (pin 3) being at or near a second voltage level and the second input (pin 1) being at or near the first voltage level. Setting logic (210) sets the count value to a value beyond the threshold in response to the first input (pin 3) and the second input (pin 1) being at or near the second voltage level when the count value is between the initial value and the threshold.

Abstract: Apparatus for determining the number of cycles occurring in a frequency modulated signal during a sample period, including not only the number of full cycles but any portion of a cycle, by determining the number of whole cycles and adding to this a value obtained by counting the number of high frequency clock cycles occurring between the time of the last rising edge of a full cycle and the end of the sample period, and the number of high frequency clock cycles occurring from the last rising edge prior to the start of the sample period and the start of the sample period and the number of high frequency clock cycles in a whole cycle.