Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.

Abstract: Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.

Abstract: In a phase difference signal generator, a first delay circuit has a delay time of nx where n ix 2, 3, . . . and x is a voluntary real number, the delay circuit receiving a first input clock signal having a phase of 0° to generate a first phase difference signal. At least one k-to-(n-k) weighted phase interpolator has a first input for receiving an output signal of said first delay circuit and a second input for receiving a second input clock signal having a phase of &thgr; to generate an output signal having a phase of (n-k)x+k&thgr;/n where k is 1, 2, . . . , n-1. At least one second delay circuit is connected to the k-to-(n-k) weighted phase interpolator. The second delay circuit has a delay time of kx to generate a k-th phase difference signal.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: A sync signal generating circuit has a first I/O replica for delaying an external clock signal, a comparator replica with a variable delay time for delaying an output of the first I/O replica, a first ramp-voltage generating circuit for outputting a first voltage whose potential level begins to rise at a time of transition of a level of the output of the comparator replica and stops rising at a predetermined timing, a second ramp-voltage generating circuit for outputting a second voltage whose potential level begins to rise after the rising of the potential level of the first voltage stops, a voltage comparator for comparing the first and second voltages and outputting an internal clock signal, a second I/O replica for delaying the internal clock signal with a delay time substantially equal to the delay time of the first I/O replica, and a phase comparator for comparing a phase of an output of the second I/O replica and a phase of an input to the first I/O replica.

Abstract: A ladder type clock network for reducing the skew of clock signals is provided. The clock network includes a buffer for buffering a clock signal, first delay units for delaying the output of the first buffer by a set time, second buffers connected to respective outputs of the first delay units, and second delay units connected to respective outputs of the second buffers. The first delay units and the second delay units consist essentially of the resistance and capacitance of lines through which the clock signal propagates. Accordingly, the skew of the internal clock signals is reduced, and internal clock signals having a stable duty with respect to variations in a semiconductor device manufacturing process, temperature, and power supply voltage, are generated.

Abstract: A variable-delay circuit on an integrated circuit is used to delay a periodic strobe signal. In normal operation, the strobe signal can be shifted 90 degrees to center it within a data bit cell. In test mode, it can also be shifted up to 270 degrees in N increments to measure the effective input latch setup and hold timings. The variable-delay circuit comprises a voltage-mixing interpolator circuit to produce phase delays in N increments. The variable-delay circuit can incorporate an existing delay locked loop. Also described are an electronic system, a data processing system, and various methods of performing on-chip testing and calibration.

Abstract: An improved edge-triggered fully digital delay locked loop (DLL), which maintains reliable synchronization from startup and in spite of system clock jitter is described. An internal clock signal is synchronized with a reference clock signal by propagating the reference clock signal through a variable digital delay path. A wide phase detection region surrounds a selected rising edge of the internal clock signal. The DLL loop is open as long as the internal clock signal and a target edge of the reference clock signal are not simultaneously within the phase detection region. To achieve a DLL locked condition, the variable delay is increased from a minimum setting until the edge of the phase detection region is shifted in time just past the target edge of the reference clock. Once the DLL loop has been closed, a clock jitter filter is enabled to reject reference clock jitter effects on the DLL locked condition.

Abstract: In an LSI design method, a delay adjusting block group including a plurality of buffer circuit blocks which have different delay amounts but which are the same in connection to the external shape and the external size of the block, the input terminal position and the output terminal position, the input terminal capacitance and the driving capability of the output part including the load dependency, is previously prepared and registered into a circuit library. One buffer circuit block selected from the delay adjusting block group is inserted into a signal path in question, and the delay amount of the signal path in question is roughly adjusted by an existing delay amount adjusting method without replacing the selected buffer circuit block, and thereafter, the delay amount of the signal path in question is roughly adjusted by replacing the selected buffer circuit block by another buffer circuit block included in the delay adjusting block group but having a different delay amount.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: Integrated circuit output buffers include an integrated circuit substrate, an output buffer in the substrate which drives a respective load, an supplemental voltage supply pad on the substrate, a first switch and at least one external capacitor which is electrically coupled to the supplemental voltage supply pad. The first switch is electrically coupled in series between an output of the output buffer and the supplemental voltage supply pad. During operation, the first switch is closed to facilitate the forward transfer of stored charge from the at least one external capacitor (e.g., 1 &mgr;F) to a capacitive load (e.g., 100 pF) during a first portion of a pull-up time interval. The output buffer is then turned on to complete the pull-up operation. Next, the transferred charge is recycled back from the load into the external capacitor by closing the first switch again during a first portion of a pull-down time interval. The output buffer is then turned on to complete the pull-down operation.

Abstract: A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).

Abstract: In an integrated circuit, a system and method of programmably controlling the delay between a second clock signal with respect to a first clock signal after fabricating the integrated circuit. Prior to fabrication, a programmable delay group is formed and will be included in the integrated circuit. The programmable delay group includes a plurality of parallel coupled sets of delay stages. Each set having at least one delay stage. For the sets having more than one delay stage, the delay stages are serially coupled. After fabrication of the integrated circuit and in operation, the first clock signal is applied to one end of each of the sets of delay stages. The enable signals are generated and applied to the programmable delay group in order to enable one of the sets of delay stages. The enabled set delays the first clock signal, thereby producing the second clock signal at the other end of the enabled set and hereby controlling the delay of the second clock signal.

Abstract: A method and circuit for flattening the output resistance response on a signal pad of an integrated circuit is presented. Impedance matching is accomplished using pull-up and pull-down FET arrays. Various combinations of pull-up PFETs in the pull-up FET array are programmably enabled by a pull-up calibration word when driving the output pad high. Various combinations of pull-down NFETs in the pull-down FET array are programmably enabled by a pull-down calibration word when driving the output pad low. An NFET in the pull-up FET calibration array and a PFET in the pull-down FET array respectively allow the output driver to supply more current during the initial stages of a voltage transition, resulting in a flatter overall output resistance Ro response.

Abstract: A VCO (voltage-controlled oscillator) that can realize stable oscillation operation over a broad frequency range with a low level of jitter. The VCO includes a plurality of basic cells having differential input/output, and a center frequency adjustment circuit. The plurality of basic cells are serially connected in a ring. Each basic cell includes a circuit constituted by two delay circuits and an adder circuit, the delay times of the two delay circuits being each independently determined by the center frequency adjustment circuit. The output amplitude of each of the basic cells is controlled to a fixed value. In the adder circuit, the output of one of the delay circuits is multiplied by an addition proportion coefficient, following which the outputs of both delay circuits are added. In this way, the delay time for each basic cell can be set over a broad range.

Abstract: A semiconductor device is provided which has a plurality of output drivers whose slew rates are differentially controlled. The slew rates of the output drivers are controlled by a control means such that the slew rate of at least one of the output drivers is different than the slew rate of another output driver. Preferably, the slew rates are differentially controlled such that an output driver that drives a signal that reaches an output pin of a semiconductor package later slews at a faster rate than an output driver that drives a signal that reaches an output pin of a semiconductor package earlier. In this way all of the output pins of a semiconductor package can be driven to change states at approximately the same time. The slew rates of the output drivers can be differentially controlled through the utilization of programmable resistors.

Abstract: A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.

Abstract: Delay circuitry includes a phase-locked loop or PLL for comparing the phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to the phase difference between the phases of the reference clock and other clock, for generating the other clock using at least a plurality of delay elements connected into a loop, a time delay provided by each of the plurality of delay elements being controlled by the control signal, and for changing the value of the control signal so that the other clock is made to be in phase with the reference clock.

Abstract: A delay circuit arrangement includes a delay cell and controller. The delay cell includes a differential pair of N-Channel devices and P-Channel devices coupling the differential pair to positive voltage rail. The controller provides conductivity adjustment in the P-Channel devices. Adjustment of the delay is made by adjusting the current in a device biased in its linear region and coupling the differential devices to a ground potential.

Abstract: In a semiconductor device capable of obtaining an optimum delay time, a plurality of delay circuits are connected in series to one another through points of connections between two adjacent ones of the delay circuits to produce a plurality of reference delay signals derived from the delay circuits. One of the reference delay signals is decided as the optimum delay time with reference to a practical condition. Thus, the delay time can be varied in the semiconductor device.

Abstract: One or more main programmed delay circuits (PDCs) are compensated to provide constant delays despite variations in environmental factors, such as temperature and power supply, by means of a dummy PDC that emulates the main PDCs in environmental sensitivity. While the main PDCs have dynamically changing programmed inputs, the dummy PDC has a constant programmed input. Changes in the dummy PDC's delay due to environmental changes are monitored and a correction signal is applied to the dummy PDC to maintain its delay substantially constant, with the same correction provided to the main PDCs to correct for the same changes in the delay of these circuits. The dummy PDC is preferably initially calibrated so that its fixed delay period coincides with an integer number of clock periods. Both the main and dummy PDCs preferably produce respective delays equal to the linear sum of a programmed delay and their correction delays.

Abstract: A delay locked loop in accordance with the present invention includes: a first delay delaying an external clock signal; a first pulse generator receiving an output from the first delay, and generating a first input signal in a short-pulse shape; a second delay delaying an inverted external clock signal; a second pulse generator receiving an output from the second delay, and generating a second input signal in a short-pulse shape; a direction control unit generating first and second control signals in order to control a forward or backward delay of the first input signal or the second input signal in accordance with a level of the external clock signal; and a delay chain consisting of a plurality of unit delays having first and second inverters, and delaying the first input signal or the second input signal in the forward and backward directions through the first and second inverters in accordance with the first and second control signals outputted from the direction control unit.

Abstract: Programmable delay lines include a delay circuit having an input and a plurality of outputs which each provide a respective delayed version of a periodic input signal provided to the input. A delay switch is also provided to pass at least one of the plurality of outputs of the delay circuit to a switch output, in response to a digital control signal (P1-Pn). A preferred phase comparing circuit is also provided. This phase comparing circuit compares the input signal against the delayed versions of the input signal (at the plurality of outputs) and generates a digital phase signal (F1-Fn) that identifies which of the delayed versions of the input signal is in-phase with the input signal. The programmable delay line also includes a pointer which generates the digital control signal in response to the digital phase signal and a plurality of pointer control signals (S0, S1 and WS).

Abstract: There is provided a circuit for controlling the setup/hold time of a semiconductor device, including: a setup/hold on signal generator for generating a setup/hold on signal of the semiconductor device; a comparison signal generator for converting the difference between pulse widths of the setup on signal and hold on signal of the setup/hold on signal generator into the voltage difference across an inner capacitor, to generate a comparison signal for the setup/hold time; a comparison signal detector for detecting the comparison signal generated by the comparison signal generator and amplifying it to a predetermined level; a clock delay path selection signal generator for generating a clock delay path selection signal according to the level of the signal detected by the comparison signal detector; and a clock/command signal processor for outputting a clock signal and command signal applied to input pads as an inner clock signal and inner command signal whose delays are compensated according to the clock delay p

Abstract: The present invention provides a time delay system that generates a selectable asynchronous time delayed signal from an incoming signal using a pulse having a minimum pulse width and stop-startable oscillator. The time delay system of the present invention produces a minimum data dependency error which is independent of the repetition rate of the incoming signal, the substrate settling time, and the length of the time delay of the delayed signal.

Abstract: A delay line, in accordance with the invention, includes a plurality of delay elements connecting an input and an output, the delay elements for causing a delay to be introduced to a signal passing through the delay elements. A voltage device is included for regulating power to the plurality of delay elements, the voltage device being adjustable to provide at least one predetermined voltage to the delay elements such that the delay in the delay elements is modified according to the predetermined voltage(s). The delay line may be employed in a delay locked loop, a clock circuit or other circuits.

Abstract: A semiconductor integrated circuit device includes a first delay circuit delaying a first clock signal, a second delay circuit delaying a second clock signal which has an inverted phase with respect to the first clock signal, a phase comparator outputting a phase error signal based on a comparison of the first clock signal and a feedback signal corresponding to an output signal from the first delay circuit, a delay control circuit generating a delay control signal based on the phase error signal, for variably controlling a delay quantity of the first and second delay circuits, and a timing adjusting circuit variably controlling a delay quantity of the second delay circuit by supplying the delay control signal to the second delay circuit at a timing synchronized to the second clock signal.

Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. In the lattice-like delay circuit, input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of a plurality of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.

Abstract: Rapid set-up is achieved in a programmable delay element having identical pairs of positionally corresponding delay stages in parallel arrays. The pairs of delay elements include identical arrangements of circuit elements and are replicable in a step-and-repeat fashion to simplify delay element manufacture for any arbitrary maximum delay time to be provided. Delay stages of the delay element are comprised of multiplexers. Outputs of respective delay stages are simultaneously stored as a signal transition is propagated through the delay stages in a first order to program the delay element. Thereafter, signals are propagated through selected delay stages in a second order controlled by the simultaneously stored outputs of respective delay stages during the propagation of the signal transition.

Abstract: In one embodiment, a multistage output buffer supplies current to a load by successively turning ON output buffer circuits which transition from an OFF state to approximately a saturated state during approximately mutually exclusive periods of time. Thus, the aggregate dI/dt of the contributed by the output buffer drivers is primarily associated with a single output buffer driver. Additionally, the respective output driver transition periods are controlled by delay stage impedance to reduce dI/dt. The consecutive activation of the output buffer drivers may be achieved by using respective delay stages to control activation of associated, respective output buffer drivers. Each delay stage receives a delayed output control signal from a previous delay stage, except for the first delay stage which receives a control input signal from a signal source. Each delay stage also delays activation of its own output control signal with delay circuit elements such as relatively HIGH impedance IGFETs.

Abstract: The variable frequency oscillator is capable of operation at a low power supply voltage and oscillating at a high frequency. A phase locked loop and a clock synchronizer use the variable frequency oscillator and have a wide oscillation frequency range. The variable frequency oscillator has plural delay cells which are cascaded and the output of the final stage delay cell is fed back to the input of the first stage delay cell. Each of the delay cells includes a differential amplifier and a positive feedback circuit, connected with input and output terminals intersecting with each other. The feedback circuit has complementary amplifiers each having an input terminal formed by connecting together gates of a pMOS and an nMOS transistor and an output terminal formed by connecting together the drains thereof.

Abstract: A delay locked loop comprising a chain (CHN) of at least two delay elements (DL1-DLN), of which a first delay element (DL1) has an input for receiving a reference signal (phi0), and of which a last delay element (DLN) has an output for delivering an output signal (phiN); a phase comparator (PHCMP) having a first input (PH1) for receiving the reference signal (phi0), a second input (PH2) for receiving the output signal (phiN), and an output for delivering a binary control signal (Bcntrl); and a converter (CNV) for converting the binary control signal (Bcntrl) into an analog control signal (Acntrl) for controlling a delay time of at least one (DL1-DLN) of said delay elements (DL1-DLN). The phase comparator (PHCMP) comprises at least one additional input (Aip) for receiving an output signal (phi1-phiN−1) of at least one of the delay elements (DL1-DLN−1) preceding the last delay element (DLN).

Abstract: Voltage controlling/oscillating device comprises a terminal for setting the delay rate in the delay unit and the delay interpolator. Clock signal whose phase is inverted by the inverting gate is inputted into a first input terminal of the delay interpolator and into the delay unit. The delay unit delays the signal by d1 and inputs into second input terminal of the delay interpolator. Oscillation frequency control voltage is fed into a terminal of the delay interpolator through an oscillation frequency control terminal of the device. Delay control voltage is fed into a terminal of the device in order to control a propagation delay rate in the delay unit and the delay interpolator. The delay rate in a delay unit and a delay interpolator can be adjusted by a delay control voltage.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: A synchronous delay circuit system comprises an input buffer having a first delay time and receiving an external clock, a clock driver having a second delay time and for an internal clock, a dummy delay circuit having a delay time equal to a sum of the first delay time and the second delay time, a first delay circuit array formed of a predetermined number of delay circuits having a predetermined delay time, for measuring a time difference of a constant period from an output of the dummy delay circuit, a second delay circuit array formed of a predetermined number of delay circuits having a predetermined delay time, for reproducing the measured time difference to output the reproduced time difference to the clock driver, a circuit for measuring the frequency of the external clock to output a frequency measurement signal, and a delay time control circuit responding to the frequency measurement signal to control the traveling speed of a pulse or a signal edge in the first delay circuit array and in the second del

Abstract: A oscillation circuit has a delay loop with a clock delay circuit for generating a delayed clock signal. The clock delay circuit has a selector and has multiple delay elements with delay times differing from each other. The clock delay circuit may produce a time lag which is less than the delay time of any single delay element, the time lag being based on the difference between the time delays of different delay elements. A phase comparator compares the phase of a signal associated the delay loop to that of a reference clock signal, generating a phase difference clock signal. A delay setting circuit can cause the selector to change the selection of one delayed clock signal according to the phase difference signal from the phase comparator in such a manner as to reduce the phase difference.

Abstract: Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

Abstract: A variable delay circuit comprises: a variable delay part having n (≧2) cascade-connected delay parts, each of which has a delay element, a selecting circuit for selecting whether an input signal is allowed to pass through the delay element, and an OR gate for outputting an output of the selected delay element or the input signal; and a control part for selecting at least one of the plurality of delay parts on the basis of desired delay time information to transmit a control signal for operating so that the selecting circuit in the selected delay part selects a corresponding one of the delay elements, wherein a designed delay time value Dk of the delay element of a number k (1≦k≦n) delay part meets the following conditions. Thus, it is possible to provide a smaller circuit scale of a variable delay circuit.

Abstract: A voltage controlled oscillator includes plural cascade-connected unit circuits supplied with selection signals corresponding to an oscillation frequency. Each unit circuit includes a voltage controlled delay circuit, selection circuit and adder circuit. The selection circuit has a first input terminal supplied with an output signal of the voltage controlled delay circuit and a second input terminal supplied with the selection signal. The adder circuit has a first input terminal supplied with an output signal of the selection circuit, a second input terminal supplied with a feedback signal from a next-stage one of the unit circuits and a third input terminal supplied with the selection signal. The adder circuit adds signals supplied to its first and second input terminals to form a feedback signal. The output signal of the voltage controlled delay circuit in each unit circuit is supplied to the voltage controlled delay circuit in the next-stage one of the unit circuits.

Abstract: A circuit comprising an input circuit and an adjustable delay. The input circuit may be configured to generate a differential signal in response to a single ended signal. The adjustable delay may be configured (i) delay or not change a rising edge or (ii) delay or not change a falling edge of a first portion of the differential signal. A second adjustable delay may be configured (i) delay or not change a rising edge or (ii) delay or not change a falling edge of a second portion of the differential signal. The differential signal may be presented to an output buffer in a Universal Serial Bus device. The present invention may also include a squaring circuit that may be configured to improve the differential alignment between the first and second portions of the differential signal.

Abstract: A delay circuit includes a primary circuit receiving an input signal and outputting two intermediate signals having a delay therebetween. A combination circuit with two modules that output a combination signal on the basis of the addition with weighting and effect of integration of the intermediate signals and of their conjugate. Each module includes a discharging circuit and a charging circuit, which each have switching elements controlling the connection between a common line and first and second supply potentials. These connections use a variable resistor and a non-variable resistor so as to ensure the permanent participation of the two modules in the charging or discharging of a capacitor. This delay circuit is particularly useful in CMOS circuits.

Abstract: Variable delay module (100) includes a clock generator (110), input A/D converter (120), buffering circuit (190), and output D/A converter (160). Clock generator (110) varies the output sampling rate of output D/A converter (160) relative to the input sampling rate of input A/D converter (120). Variable delay module (100) also uses a linear digital delay buffering circuit (190) to create a continuous delay of an analog signal through the module. Separate clocks (112, 114) are used to control the input and output stages of variable delay module (100). The second clock is asynchronous and continuously varying relative to the first clock. The second clock is generated using the coherent difference between the first clock and an autonomously generated reference phase (time) delay.

Abstract: The present invention provides a method for controlling a timing of a digital component having an impedance-input terminal. The method includes determining an impedance level present at the impedance-input terminal, and delaying the timing of the digital component based on the impedance level. The present invention also provides a digital component and a system, where the digital component includes an impedance-input terminal and an impedance matching circuit that is capable of determining an impedance level present at the impedance-input terminal. The digital component also includes a delay circuit that is capable of delaying a timing of the digital component based on the impedance level.

Abstract: A clock/data recovery device employs a phase-locked loop that supplies a single clock signal and a control voltage signal to at least one clock/data recovery circuit. The clock/data recovery circuit has a voltage-controlled delay line or direct phase controlled voltage-controlled oscillator that generates a multiple-phase clock signal, which is used to recover a clock signal and data from a received data signal. The voltage-controlled delay line or direct phase controlled vottage-controlled oscillator has a cascade or ring of voltage controlled logic gates, with propagation delays controlled by the control voltage signal from the phase-locked loop, and additional logic gates that supply the clock signal from the phase-locked loop to a selectable one of the voltage-controlled logic gates.

Abstract: A high resolution delay line includes a coarse delay having a minimum period of delay and a fine delay having a total delay, wherein the total delay is equal to or greater than half the minimum period. Each delay can be implemented in analog or digital form and the delay line can be implemented with one portion in analog form and the remainder in digital form. The digital delay can provide a delay upward of 1,500 milliseconds. The fine delay provides a resolution of ten microseconds or less. An unknown delay is measured by coupling a signal into two channels, wherein the first channel includes the unknown delay and the second channel includes the coarse delay and the fine delay. The output signals from the channels are correlated while adjusting the coarse delay for maximum correlation and then adjusting the fine delay for maximum correlation.

Abstract: To generate a signal delay, a current source, a reference voltage generator and a comparator are turned on. Once turned on, the current source raises the voltage across an initially discharged capacitor to a minimum required threshold. The comparator then compares the capacitor voltage to the reference voltage thereby to generate the delay signal. Thereafter, the current source, the reference voltage generator and substantial blocks of circuitry in the comparator are switched off to reduce quiescent power consumption.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.

Abstract: A structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.